Jim Grosbach
4d23e99d2a
Thumb .n mnemonic qualifiers can be ignored for now.
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We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 22:19:48 +00:00
Jim Grosbach
f69c804036
Thumb parsing and encoding for SUB (SP minu immediate).
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Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:42:27 +00:00
Owen Anderson
12a1e3bbcb
Be careful not to walk off the end of the operand info list while updating VFP predicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:35:46 +00:00
Jim Grosbach
72f39f8436
Thumb parsing and encoding support for ADD SP instructions.
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Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:22:15 +00:00
Jim Grosbach
df9ce6bbc5
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
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rdar://10015134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138467 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 20:06:14 +00:00
Jim Grosbach
f95aaf951b
Add missing explicit writeback operand to tSTMIA_UPD.
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rdar://10014745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:19:42 +00:00
Evan Cheng
3e74d6fdd2
Move TargetRegistry and TargetSelect from Target to Support where they belong.
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These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:08:43 +00:00
Jim Grosbach
c7e0bb2325
Thumb add SP assembly syntax fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:04:27 +00:00
Jim Grosbach
5b81584f74
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
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Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 17:46:13 +00:00
Owen Anderson
e234d02204
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 17:21:43 +00:00
Jim Grosbach
5aa29a0cff
Move ARM frame-unwinding EHABI handling a touch earlier.
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It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138386 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 21:32:34 +00:00
Jim Grosbach
d04f6a581c
[SU]XT[BH] are only available on ARMv6 and up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138373 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 20:53:08 +00:00
Evan Cheng
7801136b95
Some refactoring so TargetRegistry.h no longer has to include any files
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from MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 20:15:21 +00:00
Jim Grosbach
ec8b866434
Thumb parsing and encoding for SVC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138360 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 19:49:10 +00:00
Jim Grosbach
803b1aa8ef
Thumb parsing and encoding for tSTRspi.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 18:39:41 +00:00
Jim Grosbach
1e84f19337
Thumb parsing and encoding for STM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 18:15:37 +00:00
Jim Grosbach
aa875f8c6f
Factor low reg checking into a helper function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 18:13:04 +00:00
Owen Anderson
82265a2c72
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:51:38 +00:00
Owen Anderson
6153a036f5
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:45:18 +00:00
Jim Grosbach
cefe4c9c48
Clean up Thumb load/store multiple definitions.
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There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:41:15 +00:00
Owen Anderson
e732cb0043
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:37:32 +00:00
Jim Grosbach
04d55f1905
Thumb parsing and encoding for SBC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:55:58 +00:00
Jim Grosbach
934755ac04
Thumb parsing and encoding for RSB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138308 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:47:13 +00:00
Owen Anderson
8e1e60b5f8
Reject invalid imod values in t2CPS instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138306 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:44:04 +00:00
Owen Anderson
c6788c83b4
t2SMLAD is a four-register instruction, not a three-register one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138301 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:31:45 +00:00
Owen Anderson
22d35086fe
Correct operand naming of t2USAT16 to allow proper decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:27:47 +00:00
Jim Grosbach
86b5d2b02d
Revert r138278 now that r138289 has fixed the root issue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:25:48 +00:00
Owen Anderson
2379fc235f
Match operand naming to allow correct decoding of t2LDRSH_POST.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138298 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:22:05 +00:00
Jim Grosbach
6dcafc0d0b
Improve error checking for tPUSH and tPOP register lists.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:17:34 +00:00
Owen Anderson
796c3659c9
Match operand names to provide correct decoding for Thumb2 SMULL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138294 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:16:48 +00:00
Owen Anderson
2c9f83533b
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:10:16 +00:00
Jim Grosbach
7260c6a4ea
Thumb assemmbly parsing diagnostic improvements for LDM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:01:07 +00:00
Jim Grosbach
5e8701002b
Temporarilly mark tMUL as not commutable.
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It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 22:00:18 +00:00
Owen Anderson
838130e3b9
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138273 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 21:34:00 +00:00
Owen Anderson
357ec6850b
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 20:27:12 +00:00
Jim Grosbach
11e03e7c2d
Tighten up ARM reglist validation a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:50:36 +00:00
Owen Anderson
2cbf210450
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:42:13 +00:00
Owen Anderson
f1c8e3e70e
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:22:06 +00:00
Jim Grosbach
a33b31be45
Clean up predicates on ARM target instruction aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:04:24 +00:00
Owen Anderson
b113ec55e8
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 17:56:58 +00:00
Chad Rosier
fea95c6bad
Remove the VMOVQQ pseudo instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-20 00:52:40 +00:00
Chad Rosier
bdc18572be
Remove VMOVQQQQ pseudo instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138174 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-20 00:40:14 +00:00
Jakob Stoklund Olesen
ac3656ed7a
Add <imp-def> operands to QQ and QQQQ stack loads.
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This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138164 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-20 00:17:45 +00:00
Chad Rosier
e5038e191d
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
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Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-20 00:17:25 +00:00
Jim Grosbach
0780b6303b
Thumb parsing and encoding support for NOP.
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The irony is not lost that this is not a completely trivial patchset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 23:24:36 +00:00
Jim Grosbach
2c3f70e5d4
Thumb assembly parsing and encoding for NEG.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:51:03 +00:00
Jim Grosbach
3a244bd8b3
Fix NEG alias
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:30:58 +00:00
Jim Grosbach
7a01069420
Be more lenient on tied operand matching for MUL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:30:46 +00:00
Jim Grosbach
7a32fa1c78
Update tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:19:48 +00:00
Jim Grosbach
88ae2bc6d5
Thumb assembly parsing and encoding for MUL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 22:07:46 +00:00