Commit Graph

2618 Commits

Author SHA1 Message Date
Mihai Popa
4f7092176c This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 16:07:46 +00:00
Mihai Popa
4a378b95aa Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc instead of apsr_nzcv)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187803 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 15:52:36 +00:00
Richard Sandiford
ccdf5cc7bc [SystemZ] Add definitions for BRCT and BRCTG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187721 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 11:07:38 +00:00
Richard Sandiford
0e4044c233 [SystemZ] Add LOAD AND TEST instructions
Just the definitions and MC support.  The next patch uses them for codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187719 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-05 11:00:53 +00:00
Joey Gouly
787fdb86a7 [ARMv8] Add an assembler warning for the deprecated 'setend' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187666 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-02 19:18:12 +00:00
Elena Demikhovsky
0780179d53 EVEX and compressed displacement encoding for AVX512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187576 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 13:34:06 +00:00
Vladimir Medic
a701de8d24 Add tests for Mips DSP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187570 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:35:25 +00:00
Tim Northover
87773c318f AArch64: add initial NEON support
Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:20:35 +00:00
Kevin Enderby
e38070fc32 Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match.  Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.

rdar://14214063


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187530 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 21:05:30 +00:00
Richard Sandiford
f3068d02e5 [SystemZ] Add RISBLG and RISBHG instruction definitions
The next patch will make use of RISBLG for codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187490 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 11:17:35 +00:00
Craig Topper
418eb3df74 Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
Patch by Richard Mitton.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 02:47:52 +00:00
Vladimir Medic
b67775df0c This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 10:12:14 +00:00
Nico Rieck
fdbea5107b Use proper section suffix for COFF weak symbols
32-bit symbols have "_" as global prefix, but when forming the name of
COMDAT sections this prefix is ignored. The current behavior assumes that
this prefix is always present which is not the case for 64-bit and names
are truncated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-29 13:58:39 +00:00
Nico Rieck
c63dce3c59 MC: Support larger COFF string tables
Single-slash encoded entries do not require a terminating null. This bumps
the maximum table size from ~1MB to ~9.5MB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187352 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-29 12:30:12 +00:00
Akira Hatanaka
407883b69b [mips] Fix FP conditional move instructions to have explicit FP condition code
register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 20:51:20 +00:00
Akira Hatanaka
83d8ef133b [mips] Fix FP branch instructions to have explicit FP condition code register
operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 20:13:47 +00:00
Akira Hatanaka
9b06dd6ca2 [mips] Print instructions "beq", "bne" and "or" using assembler pseudo
instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 18:34:25 +00:00
Craig Topper
6ee1464ba5 Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187188 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 05:39:33 +00:00
Rafael Espindola
6fccaafd8b Remove the mblaze backend from llvm.
Approval in here http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/064169.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 18:55:05 +00:00
Richard Sandiford
bf99364f81 [SystemZ] Add LOCR and LOCGR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187113 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 09:11:15 +00:00
Richard Sandiford
cf20e45cc4 [SystemZ] Add LOC and LOCG
As with the stores, these instructions can trap when the condition is false,
so they are only used for things like (cond ? x : *ptr).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 09:04:52 +00:00
Richard Sandiford
b284e1bf08 [SystemZ] Add STOC and STOCG
These instructions are allowed to trap even if the condition is false,
so for now they are only used for "*ptr = (cond ? x : *ptr)"-style
constructs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 08:57:02 +00:00
Rafael Espindola
113034596c Add not so that these tests pass with pipefail enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186939 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 13:18:20 +00:00
Craig Topper
9b8b830f3f Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186924 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:50:47 +00:00
Kevin Enderby
877d123bdb Fix the move to/from accumulator register instructions that use a full 64-bit
absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 21:25:31 +00:00
Craig Topper
4e3170b63a Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186869 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 20:46:37 +00:00
Akira Hatanaka
9a05b98ef9 [mips] Fix MipsAsmParser::parseCCRRegs.
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186861 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 19:30:38 +00:00
Akira Hatanaka
0b92642767 [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 18:52:22 +00:00
Mihai Popa
0226538292 This adds range checking for "ldr Rn, [pc, #imm]" Thumb
instructions. With this patch:

1. ldr.n is recognized as mnemonic for the short encoding
2. ldr.w is recognized as menmonic for the long encoding
3. ldr will map to either short or long encodings depending on the size of the offset

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186831 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 15:49:36 +00:00
Richard Sandiford
6dae7ae765 [SystemZ] Add tests for ALHSIK and ALGHSIK
The insn definitions themselves crept into r186689, sorry.
This should be the last of the distinct-ops instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186690 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:44:32 +00:00
Richard Sandiford
c7c7e1502a [SystemZ] Add ALRK, AGLRK, SLRK and SGLRK
Follows the same lines as r186686, but much more limited, since we only
use ADD LOGICAL for multi-i64 additions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186689 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:37:00 +00:00
Joey Gouly
6fec715a1a [ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186688 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:34:16 +00:00
Richard Sandiford
70d3e71f2e [SystemZ] Add AHIK and AGHIK
I did these as a separate patch because it uses a slightly different
form of RIE layout.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:32:12 +00:00
Richard Sandiford
dc05e0bff6 [SystemZ] Add ARK, AGRK, SRK and SGRK
The testsuite changes follow the same lines as for r186683.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186686 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:26:39 +00:00
Richard Sandiford
52b2774577 [SystemZ] Add NGRK, OGRK and XGRK
Like r186683, but for 64 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186685 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:24:22 +00:00
Richard Sandiford
db92fb0716 [SystemZ] Add NRK, ORK and XRK
The atomic tests assume the two-operand forms, so I've restricted them to z10.

Running and-01.ll, or-01.ll and xor-01.ll for z196 as well as z10 shows why
using convertToThreeAddress() is better than exposing the three-operand forms
first and then converting back to two operands where possible (which is what
I'd originally tried).  Using the three-operand form first stops us from
taking advantage of NG, OG and XG for spills.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186683 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:21:55 +00:00
Tilmann Scheller
cae5d5ea65 ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form.
See A8.8.127 in ARM DDI 0406C.b.

Related to <rdar://problem/14403733>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:18:56 +00:00
Richard Sandiford
eddfaad1ef [SystemZ] Start adding z196 and zEC12 support
This first step just adds definitions for SLLK, SRLK and SRAK.
The next patch will actually make use of them during codegen.

insn-bad.s tests that some form of error is reported when using these
instructions on z10.  More work is needed to get the "instruction requires:
distinct-ops" that we'd ideally like, so I've stubbed that part out for now.
I'll come back and make it mandatory once the necessary changes are in.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:09:03 +00:00
Tim Northover
914bc14e7b ARM: delete two tests now integrated into the larger files
Somehow forgot to git rm these two files. I believe I left the remaining
invalid* tests intentionally, though whether my reasons were sound is a
different matter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186663 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 10:23:15 +00:00
Tim Northover
29cc13892d ARM: remove invalid invalid tests
The tests were checking for barriers which the ARM ARM says they must execute
as a full system DMB/DSB, rather than that they're UNDEFINED and LLVM does in
fact represent them.

The tests happened to be passing because they were using a non-versioned ARM
triple which didn't have *any* DMB/DSB instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186662 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 10:19:56 +00:00
Tim Northover
38c6ff6c11 Improve llvm-mc disassembler mode and refactor ARM tests to use it
This allows "llvm-mc -disassemble" to accept two new features:
  + Using comma as a byte separator
  + Grouping bytes with '[' and ']' pairs.

The behaviour outside a [...] group is unchanged. But within the group once
llvm-mc encounters a true error, it stops rather than trying to resynchronise
the stream at the next byte. This is more useful for disassembly tests, where
we have an almost-instruction in mind and don't care what the misaligned
interpretation would be. Particularly if it means llvm-mc won't actually see
the next intended almost-instruction.

As a side effect, this means llvm-mc can disassemble its own -show-encoding
output if copy-pasted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186661 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 10:05:04 +00:00
NAKAMURA Takumi
f8087419df llvm/test/MC/AsmParser/secure_log_unique.s: Use env(1) here. Then r186611 can be reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186643 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 01:26:08 +00:00
Hans Wennborg
9903a2513d test/MC/AsmParser/secure_log_unique.s requires shell
This should fix the chapuni bots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-18 21:34:13 +00:00
Rafael Espindola
13c9cf1d51 Add a test for .secure_log_unique.
It also doubles a test that F_Append works.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186606 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-18 20:34:26 +00:00
Joey Gouly
59b3300664 [ARMv8] Add NEON instructions VCVT{A, N, P, M}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186574 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-18 11:53:22 +00:00
Joey Gouly
6a3d933e16 Add Thumb tests for the ARMv8 FP instructions that I recently added.
Also, fix the namespace for two instructions that I missed previously.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186572 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-18 10:20:25 +00:00
Vladimir Medic
764f6f5125 This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-18 09:28:35 +00:00
Vladimir Medic
16f385f90f Implement eret and deret(return from exception) instructions for Mips. Test examples are given.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-17 14:05:19 +00:00
Joey Gouly
c88ac4a344 Add the tests that I forgot to 'svn add' with my previous commit (r186504).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186506 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-17 14:03:49 +00:00
Tilmann Scheller
898788c6bc ARM: Add support for the Thumb2 PLI alternate literal form.
This adds an instruction alias to make the assembler recognize the alternate literal form: pli [PC, #+/-<imm>]

See A8.8.129 in the ARM ARM (DDI 0406C.b).

Fixes <rdar://problem/14403733>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-16 21:52:34 +00:00