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5267651057
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880 Commits

Author SHA1 Message Date
Chris Lattner
5267651057 print arbitrary constant pool entries 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26545 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 09:38:03 +00:00
Evan Cheng
9176b0169c Back out fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) for now. 
It's causing an infinite loop compiling ldecod on x86 / Darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26544 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 07:30:16 +00:00
Chris Lattner
12d830346b Add some simple copysign folds 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26543 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 05:30:57 +00:00
Chris Lattner
a09f848c11 Codegen copysign[f] into a FCOPYSIGN node 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26542 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 05:09:38 +00:00
Chris Lattner
a1deca3cd6 fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 
fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)

This allows us to compile CodeGen/PowerPC/addi-reassoc.ll into:

_test1:
        slwi r2, r4, 4
        add r2, r2, r3
        lwz r3, 36(r2)
        blr
_test2:
        mulli r2, r4, 5
        add r2, r2, r3
        lbz r2, 11(r2)
        extsb r3, r2
        blr

instead of:

_test1:
        addi r2, r4, 2
        slwi r2, r2, 4
        add r2, r3, r2
        lwz r3, 4(r2)
        blr
_test2:
        addi r2, r4, 2
        mulli r2, r2, 5
        add r2, r3, r2
        lbz r2, 1(r2)
        extsb r3, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26535 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-04 23:33:26 +00:00
Evan Cheng
3e1ce5a44d Add more vector NodeTypes: VSDIV, VUDIV, VAND, VOR, and VXOR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26504 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 07:01:07 +00:00
Evan Cheng
33143dce15 Number of NodeTypes now exceeds 128. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26503 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 06:58:59 +00:00
Evan Cheng
bfa284f697 SDOperand::isOperand should not be a forwarding. It must check *this against N's operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26502 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 06:42:32 +00:00
Evan Cheng
80d8eaae05 Added isOperand(N): true if this is an operand of N 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26501 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 06:24:54 +00:00
Evan Cheng
fb43331226 A bit more tweaking 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26500 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 06:23:43 +00:00
Jeff Cohen
d84525480a Fix VC++ compilation errors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26498 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 03:25:07 +00:00
Chris Lattner
41edaa0529 remove the read/write port/io intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26479 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 00:19:58 +00:00
Chris Lattner
03dd465215 Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving 
PR709, and paving the way for future progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26476 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 00:00:25 +00:00
Evan Cheng
86ec7d1d07 - Fixed some priority calculation bugs that were causing bug 478. Among them: 
a predecessor appearing more than once in the operand list was counted as
  multiple predecessor; priority1 should be updated during scheduling;
  CycleBound was updated after the node is inserted into priority queue; one
  of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
  operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
  predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
        .text
        .align  4
        .globl  _f
_f:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        movl %eax, %edx
        imull %ecx, %edx
        imull %eax, %eax
        imull %ecx, %ecx
        addl %eax, %ecx
        leal (%ecx,%edx,2), %eax
        ret

  It is also a slight performance win (1% - 3%) for most tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26470 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-02 21:38:29 +00:00
Chris Lattner
1ec05d1bb4 Fix CodeGen/Generic/2006-03-01-dagcombineinfloop.ll, an infinite loop 
in the dag combiner on 176.gcc on x86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26459 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 21:47:21 +00:00
Chris Lattner
b2742f4a26 Fix a typo evan noticed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26454 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 19:55:35 +00:00
Chris Lattner
2466472a2b Add support for target-specific dag combines 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26443 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 04:53:38 +00:00
Chris Lattner
00ffed0468 Add interfaces for targets to provide target-specific dag combiner optimizations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26442 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 04:52:55 +00:00
Chris Lattner
5750df9d69 Add a new AddToWorkList method, start using it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26441 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 04:03:14 +00:00
Chris Lattner
0b1a85f110 Pull shifts by a constant through multiplies (a form of reassociation), 
implementing Regression/CodeGen/X86/mul-shift-reassoc.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26440 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 03:44:24 +00:00
Evan Cheng
860771d2d8 Vector ops lowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26436 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 01:09:54 +00:00
Evan Cheng
1ab7d859cf - Added VConstant as an abstract version of ConstantVec. 
- All abstrct vector nodes must have # of elements and element type as their
first two operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26432 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 00:51:13 +00:00
Chris Lattner
35a9f5a241 Compile: 
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }

to:

_foo4:
        lbz r3,1(r3)
        blr
_foo5:
        lbz r3,1(r3)
        blr

not:

_foo4:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr
_foo5:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26419 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-28 06:49:37 +00:00
Chris Lattner
15045b6973 Fold "and (LOAD P), 255" -> zextload. This allows us to compile: 
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
        lbz r3, 3(r3)
        blr

instead of:

_foo3:
        lwz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr

and:

unsigned short foo2(float a) { return a; }

as:
_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lhz r3, -2(r1)
        blr

instead of:

_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26417 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-28 06:35:35 +00:00
Chris Lattner
71d9ebcbc1 fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26416 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-28 06:23:04 +00:00
Chris Lattner
22873462c9 Add support for output memory constraints. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26410 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-27 23:45:39 +00:00
Chris Lattner
a6bc5a4d21 Implement bit propagation through sub nodes, this (re)implements 
PowerPC/div-2.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26392 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-27 01:00:42 +00:00
Chris Lattner
2d2536c9d7 remove some completed notes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26390 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-27 00:39:31 +00:00
Chris Lattner
81cd35586f Check RHS simplification before LHS simplification to avoid infinitely looping 
on PowerPC/small-arguments.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26389 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-27 00:36:27 +00:00
Chris Lattner
5f0c658aa4 Just like we use the RHS of an AND to simplify the LHS, use the LHS to 
simplify the RHS.  This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:

_test2:
        srwi r2, r3, 1
        xori r3, r2, 40961
        blr

instead of this:

_test2:
        rlwinm r2, r3, 31, 17, 31
        xori r2, r2, 40961
        rlwinm r3, r2, 0, 16, 31
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26388 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-27 00:22:28 +00:00
Chris Lattner
ec665151b8 Add a bunch of missed cases. Perhaps the most significant of which is that 
assertzext produces zero bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26386 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-26 23:36:02 +00:00
Evan Cheng
38b7327ec0 Print ConstantPoolSDNode offset field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26381 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-26 08:36:57 +00:00
Evan Cheng
404cb4f9fa Added an offset field to ConstantPoolSDNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26371 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-25 09:54:52 +00:00
Chris Lattner
daf6bc6347 Pass all the flags to the asm printer, not just the # operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26362 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 19:50:58 +00:00
Chris Lattner
fd6d282a71 rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope. 
Add support for addressing modes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26361 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 19:18:20 +00:00
Chris Lattner
ed18b6896e Refactor operand adding out to a new AddOperand method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26358 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 18:54:03 +00:00
Jeff Cohen
7e88103cde Get VC++ building again. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26351 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 02:52:40 +00:00
Chris Lattner
0e43f2ba11 Implement (most of) selection of inline asm memory operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26350 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 02:13:54 +00:00
Chris Lattner
87bc3bd121 Lower C_Memory operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26346 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 01:11:24 +00:00
Chris Lattner
2b7401e28e Recognize memory operand codes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26345 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 01:10:46 +00:00
Chris Lattner
9f6637db10 Fix an endianness problem on big-endian targets with expanded operands 
to inline asms.  Mark some methods const.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26334 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 20:06:57 +00:00
Chris Lattner
c3a9f8d31c Record all of the expanded registers in the DAG and machine instr, fixing 
several bugs in inline asm expanded operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26332 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 19:21:04 +00:00
Chris Lattner
9b6fb5de49 This fixes a couple of problems with expansion 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26318 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 23:09:03 +00:00
Chris Lattner
b3befd41b4 Don't return registers from register classes that aren't legal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26317 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 23:00:51 +00:00
Chris Lattner
864635ad7b Change a whole bunch of code to be built around RegsForValue instead of 
a single register number.  This fully implements promotion for inline asms,
expand is close but not quite right yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26316 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 22:37:12 +00:00
Chris Lattner
1efa40f6a4 split register class handling from explicit physreg handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 00:56:39 +00:00
Chris Lattner
0f0b7d4927 Adjust to changes in getRegForInlineAsmConstraint prototype 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26306 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 23:12:12 +00:00
Chris Lattner
4217ca8dc1 Updates to match change of getRegForInlineAsmConstraint prototype 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 23:11:00 +00:00
Chris Lattner
7d20d39009 Fix a problem Nate and Duraid reported where simplifying nodes can cause 
them to get ressurected, in which case, deleting the undead nodes is
unfriendly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26291 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-20 06:51:04 +00:00
Chris Lattner
dca7abed91 Fix a problem on itanium with memset. The value to set has been promoted to 
i64 before this code, so zero_ext doesn't work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26290 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-20 06:38:35 +00:00