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132 Commits

Author SHA1 Message Date
Chad Rosier
410ca67ab2 [AArch64] Removed unnecessary copy patterns with v1fx types. 
- Copy patterns with float/double types are enough.
- Fix typos in test case names that were using v1fx.
- There is no ACLE intrinsic that uses v1f32 type.  And there is no conflict of
  neon and non-neon ovelapped operations with this type, so there is no need to
  support operations with this type.
- Remove v1f32 from FPR32 register and disallow v1f32 as a legal type for
  operations.

Patch by Ana Pazos!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197159 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-12 15:46:29 +00:00
Hao Liu
60a21f2238 [AArch64]Fix the problem that AArch64 backend fails to select scalar_to_vector of vector types having more than one element. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197135 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-12 07:36:26 +00:00
Kevin Qin
24802f3f82 Fix Incorrect CHECK message [0-31]+ in test case. 
In regular expression, [0-31]+ equals to [0-3]+, not the number from
0 to 31. So change it to [0-9]+.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197113 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-12 02:19:13 +00:00
Quentin Colombet
b0f8afd43c Fix an over-constrained assertion in MachineFunction::addLiveIn. 
The assertion was checking that the virtual register VReg used to represent the
physical register PReg uses the same register class as the one passed to
MachineFunction::addLiveIn.
This is over-constraining because it is sufficient to check that the register
class of VReg (VRegRC) is a subclass of the register class of PReg (PRegRC) and
that VRegRC contains PReg.
Indeed, if VReg gets constrained because of some operation constraints
between two calls of MachineFunction::addLiveIn, the original assertion
cannot match.

This fixes <rdar://problem/15633429>. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197097 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-12 00:15:47 +00:00
Chad Rosier
eb1bac0afa [AArch64] Refactor NEON floating-point Max/Min/Maxnm/Minnm across vector AArch64 
intrinsics to use f32 types, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 23:21:25 +00:00
Chad Rosier
87b627d88e [AArch64] Add NEON scalar floating-point compare LLVM AArch64 intrinsics that 
use f32/f64 types, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197068 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 21:03:46 +00:00
Chad Rosier
73f468218f [AArch64] Refactor the NEON scalar floating-point reciprocal step and 
floating-point reciprocal square root step LLVM AArch64 intrinsics to
use f32/f64 types, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197067 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 21:03:43 +00:00
Chad Rosier
c3e5d72ba8 [AArch64] Refactor the NEON scalar floating-point reciprocal estimate, floating- 
point reciprocal exponent, and floating-point reciprocal square root estimate
LLVM AArch64 intrinsics to use f32/f64 types, rather than their vector
equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197066 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-11 21:03:40 +00:00
Chad Rosier
b2282508d3 [AArch64] Refactor the NEON floating-point absolute difference LLVM AArch64 
intrinsic to use f32/f64 types, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196965 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 21:33:59 +00:00
Chad Rosier
2456ea5c92 [AArch64] Refactor the NEON signed/unsigned floating-point convert to fixed-point 
LLVM AArch64 intrinsics to use f32/f64, rather than their vector equivalents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196964 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 21:33:56 +00:00
Chad Rosier
c000d11d5d [AArch64] Overload NEON signed/unsigned floating-point convert to fixed-point 
and fixed-point convert to floating-point LLVM AArch64 intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196963 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 21:33:53 +00:00
Chad Rosier
d096a5c237 [AArch64] Overload NEON signed/unsigned integer convert to floating-point 
LLVM AArch64 intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196962 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 21:33:50 +00:00
Chad Rosier
fafd264de4 [AArch64] Refactor the Neon vector/scalar floating-point convert intrinsics so 
that they use float/double rather than the vector equivalents when appropriate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196930 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 16:11:39 +00:00
Chad Rosier
72800f3a06 [AArch64] Refactor the Neon vector/scalar floating-point convert implementation. 
Specifically, reuse the ARM intrinsics when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196926 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 15:35:33 +00:00
Kevin Qin
3171b8df48 [AArch64 NEON] Support poly128_t and implement relevant intrinsic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196887 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 06:48:35 +00:00
Chad Rosier
e02fa056d9 [AArch64] Refactor the NEON scalar reduce pairwise intrinsics, so that they use 
float/double rather than the vector equivalents when appropriate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196833 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 22:47:38 +00:00
Chad Rosier
97eda18693 [AArch64] Refactor NEON scalar reduce pairwise front-end codegen to remove 
unnecessary patterns in tablegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196832 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 22:47:34 +00:00
Chad Rosier
6c6344e6a9 [AArch64] Remove q and non-q intrinsic definitions in the NEON scalar reduce 
pairwise implementation, using an overloaded definition instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196831 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 22:47:31 +00:00
Ana Pazos
ddf4eb3d03 Fix pattern match for movi with 0D result 
Patch by Jiangning Liu.

With some test case changes:
- intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll.
- New test cases to cover movi 1D scenario without using the intrinsic in
test/CodeGen/AArch64/neon-mov.ll.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196806 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 19:29:14 +00:00
Hao Liu
a339740cb8 [AArch64]Add missing pair intrinsics such as: 
int32_t vminv_s32(int32x2_t a)
which should be compiled into SMINP Vd.2S,Vn.2S,Vm.2S


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196749 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 03:51:42 +00:00
Hao Liu
2f3f02f6f5 [AArch64]Pattern match failures for truncate store and extend load 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196748 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-09 03:34:08 +00:00
Jiangning Liu
4fd58529ab For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196456 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-05 02:12:01 +00:00
Kevin Qin
dd302615b1 [AArch64 Neon] Add ACLE intrinsic vceqz_f64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196362 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-04 08:02:34 +00:00
Kevin Qin
c7f14e3d8c [AArch64 NEON] Add missing compare intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196360 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-04 07:53:28 +00:00
Hao Liu
1296bb3ba6 [AArch64]Add missing floating point convert, round and misc intrinsics. 
E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196210 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-03 06:06:55 +00:00
Hao Liu
5025a48f68 AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions. 
E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196208 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-03 05:58:30 +00:00
Hao Liu
3d69ff4d07 AArch64: Add missing scalar pair intrinsics. 
E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196198 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-03 03:39:47 +00:00
Jiangning Liu
bbc450c5cf Add some missing pattern matches for AArch64 Neon intrinsics like vuqadd_s64 and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196192 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-03 01:33:52 +00:00
Jiangning Liu
7f1f8d4146 Add some missing pattern matches for AArch64 Neon intrinsics like vmull_high_n_s16 and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196190 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-03 01:29:32 +00:00
Chad Rosier
d4809bb0e3 [AArch64] Implemented vcopy_lane patterns using scalar DUP instruction. 
Patch by Ana Pazos!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196151 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-02 21:05:16 +00:00
Hao Liu
7fd70e7b0c AArch64: The pattern match should check the range of the immediate value. 
Or we can generate some illegal instructions.
E.g. shrn2 v0.4s, v1.2d, #35. The legal range should be in [1, 16].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195941 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-29 02:11:22 +00:00
Jiangning Liu
d4685468fd Add missing test case for bsl_f64 support of AArch64 NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195939 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-29 01:38:08 +00:00
Jiangning Liu
35df2e8c7f Fix the AArch64 NEON bug exposed by checking constant integer argument range of ACLE intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195843 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-27 14:02:25 +00:00
Chad Rosier
9fef0370c5 [AArch64] Add support for NEON scalar floating-point absolute difference. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195803 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-27 01:45:58 +00:00
Chad Rosier
48f115aabf [AArch64] Add support for NEON scalar floating-point to integer convert 
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195788 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-26 22:17:37 +00:00
Kevin Qin
cf7ed12a1d Refactored the implementation of AArch64 NEON instruction ZIP, UZP 
and TRN.
Fix a bug when mixed use of vget_high_u8() and vuzp_u8().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195716 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-26 03:26:47 +00:00
Kevin Qin
57f6b2778b [AArch64]Implement 128 bit register copy with NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195713 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-26 02:33:42 +00:00
Hao Liu
e74a644b38 Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types. 
e.g. "%tmp = load <2 x i64>* %ptr" can't be selected. 
     "%tmp = bitcast i64 %in to <2 x i32>" can't be selected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195424 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-22 08:47:22 +00:00
Jiangning Liu
0282fe6d91 For AArch64 back-end instruction selection, lower Neon_Lowxxx with EXTRCT_SUBREG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195408 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-22 02:45:13 +00:00
Ana Pazos
6345249972 Implemented Neon scalar vdup_lane intrinsics. 
Fixed scalar dup alias and added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195330 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-21 08:16:15 +00:00
Ana Pazos
1c93766aa5 Implemented Neon scalar by element intrinsics. 
Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane,
vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195327 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-21 07:37:04 +00:00
Hao Liu
36c7806f4e Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 02:17:05 +00:00
Jiangning Liu
f11b55c5cc Implement AArch64 SISD intrinsics for vget_high and vget_low. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195074 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 01:46:48 +00:00
Jiangning Liu
01dd5728cc Add predicate for AArch64 crypto instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 01:38:31 +00:00
Hao Liu
97577757c6 Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors. 
The functions are like: vst1_s8_x2 ...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194990 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-18 06:31:53 +00:00
Ana Pazos
a53bf06f7a Implemented aarch64 Neon scalar vmulx_lane intrinsics 
Implemented aarch64 Neon scalar vfma_lane intrinsics
Implemented aarch64 Neon scalar vfms_lane intrinsics

Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64
intrinsics (v1f64 parameter type) using Neon scalar instructions.

Implemented legacy vfma_lane_f64, vfms_lane_f64,
vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type)
using Neon scalar instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194888 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-15 23:32:10 +00:00
Chad Rosier
5758c3c832 [AArch64] Fix the scalar NEON ACLE functions so that they return float/double 
rather than the vector equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194853 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-15 21:28:10 +00:00
Kevin Qin
27df434c5e Add test case for AArch64 NEON instruction set misc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194673 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 06:45:17 +00:00
Kevin Qin
a08063a000 Implement aarch64 neon instruction class SIMD misc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 02:44:13 +00:00
Jiangning Liu
082ac99cc8 Implement AArch64 NEON instruction set AdvSIMD (table). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 01:57:32 +00:00