tblgen has been renamed to llvm-tblgen so this command has been failing,
and it's no longer needed because llvm-tblgen is already installed by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147187 91177308-0d34-0410-b5e6-96231b3b80d8
Diagnostics are now emitted via the SourceMgr and we use MemoryBuffer
for buffer management. Switched the code to make use of the trailing
'0' that MemoryBuffer guarantees where it makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147063 91177308-0d34-0410-b5e6-96231b3b80d8
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results. The function is
still not auto-generated, so it still returns inexact results.
This produces these new register classes:
ARM:
QQPR_with_dsub_0_in_DPR_8
QQQQPR_with_dsub_0_in_DPR_8
X86:
GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
GR64_with_sub_16bit_in_GR16_NOREX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_with_sub_32bit_in_GR32_TC
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
GR64_with_sub_32bit_in_GR32_AD
GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX
The other targets in the tree are not weird enough to be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146872 91177308-0d34-0410-b5e6-96231b3b80d8
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B. This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.
In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).
This introduces these synthetic register classes:
ARM:
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
tGPR_and_tcGPR
hGPR_and_tcGPR
X86:
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR64_NOSP_and_GR64_TC
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_TC
GR32_NOAX_and_GR32_NOSP
GR64_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_ABCD_and_GR32_NOAX
GR64_ABCD_and_GR64_TC
GR32_NOAX_and_GR32_TC
GR32_AD_and_GR32_NOAX
Other targets are unaffected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146657 91177308-0d34-0410-b5e6-96231b3b80d8
subdirectories to traverse into.
- Originally I wanted to avoid this and just autoscan, but this has one key
flaw in that new subdirectories can not automatically trigger a rerun of the
llvm-build tool. This is particularly a pain when switching back and forth
between trees where one has added a subdirectory, as the dependencies will
tend to be wrong. This will also eliminates FIXME implicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146436 91177308-0d34-0410-b5e6-96231b3b80d8
For example, ARM allows:
vmov.u32 s4, #0 -> vmov.i32, #0
'u32' is a more specific designator for the 32-bit integer type specifier
and is legal for any instruction which accepts 'i32' as a datatype suffix.
We want to say,
def : TokenAlias<".u32", ".i32">;
This works by marking the match class of 'From' as a subclass of the
match class of 'To'.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145992 91177308-0d34-0410-b5e6-96231b3b80d8
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
When wait() has finished, opened handles (especially writing stdout to file) might not be released immediately.
To wait for released, poll to attempt renaming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145222 91177308-0d34-0410-b5e6-96231b3b80d8
properly quote strings when writing the CMakeFiles/Makefile.cmake output file
(which lists the dependencies). This shows up when using CMake + MSYS Makefile
generator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144873 91177308-0d34-0410-b5e6-96231b3b80d8
- Can be used to generate the substitution values we currently use for the various target related .def files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144345 91177308-0d34-0410-b5e6-96231b3b80d8
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144253 91177308-0d34-0410-b5e6-96231b3b80d8
- Currently we require that all references between components (except the parent relation) fit into a DAG -- this could be relaxed later if it ever proves to be useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143623 91177308-0d34-0410-b5e6-96231b3b80d8
one aspect of them by having them use the (annoying, if not broken)
proper library dependency model for adding the LLVMTableGen library as
a dependency. This could manifest as a link order issue in the presence
of separate LLVM / Clang source builds with CMake and a linker that
really cares about such things.
Also, add the Support dependency to llvm-tblgen itself so that it
doesn't rely on TableGen's transitive Support dependency. A parallel
change for clang-tblgen will be forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143531 91177308-0d34-0410-b5e6-96231b3b80d8
For example,
On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a
matcher pattern that handles the bitwise negation when mapping to t2MVNi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143233 91177308-0d34-0410-b5e6-96231b3b80d8
If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143200 91177308-0d34-0410-b5e6-96231b3b80d8
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
the last compiler built for the previous flavour is used for the next,
for example the Debug clang compiler was being used for the initial build
of the Release LLVM. Flavors should be independent of each other. This
especially matters if the compiler built for the previous flavour doesn't
actually work!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142607 91177308-0d34-0410-b5e6-96231b3b80d8
In fact this commit is not intended to change anything unless you
use one of the new command line flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142577 91177308-0d34-0410-b5e6-96231b3b80d8
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
This removes support for building llvm-gcc. It will eventually add support for
building other projects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142165 91177308-0d34-0410-b5e6-96231b3b80d8
the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8
Pass the correct jobs and threads information to the builder.
We were underutilizing the number of jobs and threads specified
by the user.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141977 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen infers unmodeled side effects on instructions without a
pattern. Fix some instruction definitions where that was overlooked.
Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.
Add a test case for xorps which has a very high opcode that exposes this
problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
Multidefs are a bit unwieldy and incomplete. Remove them in favor of
another mechanism, probably for loops.
Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141378 91177308-0d34-0410-b5e6-96231b3b80d8
This restores my karma after I added TRI::getSubClassWithSubReg().
Register constraints are applied 'backwards'. Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.
We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in? The
getSubRegisterRegClass() hook did that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.
For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.
The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.
The version provided by TableGen is usually adequate, but targets can
override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.
This patch implements the easiest form of register class inference: For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.
This does create some new register classes for the targets in the tree:
ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td
file on purpose because it only has two registers. InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.
PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8. I think that might be an omission?
X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:
GR64_with_sub_8bit
GR64_TC_with_sub_8bit
GR64_NOREX_with_sub_8bit
GR64_TC_with_sub_8bit_hi
The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference. All register classes must have a
name, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.
This will be used to simplify some sub-class operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140826 91177308-0d34-0410-b5e6-96231b3b80d8
Many targets use pseudo instructions to help register allocation. Like
the COPY instruction, these pseudos can be expanded after register
allocation. The early expansion can make life easier for PEI and the
post-ra scheduler.
This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
Report missing template arguments more helpfully by supplying the name
of the missing argument in the error message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140034 91177308-0d34-0410-b5e6-96231b3b80d8
