Commit Graph

90622 Commits

Author SHA1 Message Date
Ulrich Weigand
5b390e4cd8 Use direct types in PowerPC instruction patterns.
This commit updates the PowerPC back-end (PPCInstrInfo.td and
PPCInstr64Bit.td) to use types instead of register classes in
instruction patterns, along the lines of Jakob Stoklund Olesen's
changes in r177835 for Sparc.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177890 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 19:05:30 +00:00
Ulrich Weigand
1492a4e518 Use direct types in PowerPC Pat patterns.
This commit updates the PowerPC back-end (PPCInstrInfo.td and
PPCInstr64Bit.td) to use types instead of register classes in
Pat patterns, along the lines of Jakob Stoklund Olesen's
changes in r177829 for Sparc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177889 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 19:04:58 +00:00
Dave Zarzycki
9b3939983f x86 -- add the XTEST instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 18:59:43 +00:00
Dave Zarzycki
97a80092d3 x86 -- disassemble the REP/REPNE prefix when needed
This fixes Apple bug: 13493622

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177887 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 18:59:38 +00:00
Chad Rosier
301a9c0db7 Remove unnecessary attributes from test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 18:36:19 +00:00
Bill Wendling
66d11e9aa7 Remove assert. There may be target-dependent attributes left.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177878 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 17:42:20 +00:00
Dmitri Gribenko
9409a64eb0 Documentation: Replace dead link for binfmt_misc
Patch by Thomas Schwinge.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177876 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 17:08:25 +00:00
Chad Rosier
c82fba27fe [arm load/store optimizer] When trying to merge a base update load/store, make
sure the base register and would-be writeback register don't conflict for
stores.  This was already being done for loads.

Unfortunately, it is rather difficult to create a test case for this issue.  It
was exposed in 450.soplex at LTO and requires unlucky register allocation.
<rdar://13394908>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177874 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 16:29:20 +00:00
Shankar Easwaran
bd1737c846 [tools][llvm-readobj] print the name of the section when iterating the symbol table / dynamic symbol table
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 16:06:51 +00:00
Shankar Easwaran
11987c4719 [ELF] add elf_hash function to compute the hash value of a symbol in the dynamic symbol table
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177872 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 16:02:10 +00:00
Duncan Sands
6a19f7b9de Teach cmake about the new Erlang GC files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177869 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 14:12:21 +00:00
Yiannis Tsiouris
477de3a785 Add a GC plugin for Erlang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177867 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 13:47:46 +00:00
Duncan Sands
2269c56a3c Don't use add_llvm_definitions for adding warning flags. It makes it too hard
to have them appear in the right order.  Instead append all warnings explicitly
to the language flags.  This was already the case for many warnings.  Fixes the
issue of -Wno-maybe-uninitialized not being effective because -Wall was being
placed after it rather than before.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177866 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 13:25:34 +00:00
Joerg Sonnenberger
f9a7132df8 Refine fenv.h handling: check if the desired macros exist, before using
it. NetBSD/ARM and TILE-Gx are examples for platforms that have an
unusable fenv.h and this avoids the need for a blacklist.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 13:13:33 +00:00
Arnaud A. de Grandmaison
1bb93a9121 Address issues found by Duncan during post-commit review of r177856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177863 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 11:47:38 +00:00
Arnaud A. de Grandmaison
35763b1ee7 InstCombine: simplify comparisons to zero of (shl %x, Cst) or (mul %x, Cst)
This simplification happens at 2 places :
 - using the nsw attribute when the shl / mul is used by a sign test
 - when the shl / mul is compared for (in)equality to zero

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177856 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 09:48:49 +00:00
Michael Gottesman
f0a15d88af Changed isNullOrUndef => IsNullOrUndef and isNoopInstruction => IsNoopInstruction so that all helper functions are named similarly in ObjCARC.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177855 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 09:27:43 +00:00
Jakob Stoklund Olesen
a231033e70 Mention the new TableGen pattern format in the release notes.
Make threats about removing the old syntax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25 00:36:53 +00:00
Justin Holewinski
1ce53cb526 [NVPTX] Fix handling of vector arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 21:17:47 +00:00
Jakob Stoklund Olesen
d28e30fcf4 Clean up Sparc patterns.
The types of register variables no longer need to be specified in output
patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177845 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 19:37:04 +00:00
Jakob Stoklund Olesen
8e3cb3ee0c Allow types to be omitted in output patterns.
This syntax is now preferred:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;

There is no reason to repeat the types in the output pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177844 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 19:37:00 +00:00
Jakob Stoklund Olesen
4717fd4c0f Allow TableGen DAG arguments to be just a name.
DAG arguments can optionally be named:

  (dag node, node:$name)

With this change, the node is also optional:

  (dag node, node:$name, $name)

The missing node is treated as an UnsetInit, so the above is equivalent
to:

  (dag node, node:$name, ?:$name)

This syntax is useful in output patterns where we currently require the
types of variables to be repeated:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>;

This is preferable:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177843 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 19:36:51 +00:00
Tobias Grosser
9c22886a01 GettingStarted: Add Git clone instructions for compiler-rt and test-suite
Contributed-by:  Thomas Schwinge  <thomas@codesourcery.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177841 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 15:15:19 +00:00
Jakub Staszak
6f7becfe23 Minor cleanups. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177837 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 09:56:28 +00:00
Jakub Staszak
65a47ff554 Use dyn_cast instead of isa && cast.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177836 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 09:25:47 +00:00
Jakob Stoklund Olesen
15a3c18623 Give Sparc instruction patterns direct types instead of register classes.
Also update the documentation since Sparc is the nicest backend, and
used as an example in WritingAnLLVMBackend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177835 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 00:56:20 +00:00
Jakob Stoklund Olesen
19209960b6 Allow direct value types to be used in instruction 'set' patterns.
This makes it possible to define instruction patterns like this:

def LDri : F3_2<3, 0b000000,
                (outs IntRegs:$dst), (ins MEMri:$addr),
                "ld [$addr], $dst",
                [(set i32:$dst, (load ADDRri:$addr))]>;
                      ~~~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-24 00:56:16 +00:00
Hal Finkel
526d6c451b PPC ZERO register needs a register number of 0.
In order for the new ZERO register to be used with MC, etc. we need to specify
its register number (0).

Thanks to Kai for reporting the problem!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177833 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 22:06:07 +00:00
Hal Finkel
3f2c047f32 Note in PPCFunctionInfo VRSAVE spills
In preparation for using the new register scavenger capability for providing
more than one register simultaneously, specifically note functions that have
spilled VRSAVE (currently, this can happen only in functions that use the
setjmp intrinsic). As with CR spilling, such functions will need to provide two
emergency spill slots to the scavenger.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177832 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 22:06:03 +00:00
Hal Finkel
7d35f74a5d MCize the bcl instruction in PPCAsmPrinter
I recently added a BCL instruction definition as part of implementing SjLj
support. This can also be used to MCize bcl emission in the asm printer.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 20:53:15 +00:00
Jakob Stoklund Olesen
edf03820f1 Use direct types in Sparc def : Pat patterns.
The SelectionDAG graph has MVT type labels, not register classes, so
this makes it clearer what is happening.

This notation is also robust against adding more types to the IntRegs
register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 20:35:05 +00:00
Jakob Stoklund Olesen
f0a804df49 Allow direct value types in pattern definitions.
Just like register classes, value types can be used in two ways in
patterns:

  (sext_inreg i32:$src, i16)

In a named leaf node like i32:$src, the value type simply provides the
type of the node directly. This simplifies type inference a lot compared
to the current practice of specifiying types indirectly with register
classes.

As an unnamed leaf node, like i16 above, the value type represents
itself as an MVT::Other immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 20:35:01 +00:00
Hal Finkel
02327fefd8 Cleanup some unused reg. scavenger parameters in PPCRegisterInfo
These spilling functions will eventually make use of the register scavenger,
however, they'll do so by taking advantage of PEI's virtual-register-based
delayed scavenging mechanism. As a result, these function parameters will not
be used, and can be removed.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177827 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 19:36:47 +00:00
Jakob Stoklund Olesen
7a42fb3b6e Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.
A register class can appear as a leaf TreePatternNode with and without a
name:

  (COPY_TO_REGCLASS GPR:$src, F8RC)

In a named leaf node like GPR:$src, the register class provides type
information for the named variable represented by the node. The TypeSet
for such a node is the set of value types that the register class can
represent.

In an unnamed leaf node like F8RC above, the register class represents
itself as a kind of immediate. Such a node has the type MVT::i32,
we'll never create a virtual register representing it.

This change makes it possible to remove the special handling of
COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177825 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 18:08:44 +00:00
Hal Finkel
7257fda1b3 Remove dead PPC LR spilling code
The LR register is unconditionally reserved, and its spilling and restoration
is handled by the prologue/epilogue code. As a result, it is never explicitly
spilled by the register allocator.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177823 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 17:14:27 +00:00
Benjamin Kramer
7cdba152bb Plug a memory leak in FileCheck when the input file is empty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177822 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 13:56:23 +00:00
Benjamin Kramer
1f1058fb1a Move X86-dependent test into the right subdirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177821 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 09:35:44 +00:00
Owen Anderson
7834c71433 Remove the type legality check from the SelectionDAGBuilder when it lowers @llvm.fmuladd to ISD::FMA nodes.
Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA.
For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's.

NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook.  They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 08:26:53 +00:00
Michael Gottesman
31881c235f Change method name ClearRefCount => ClearKnownPositiveRefCount to match the name of the member that it is modifying.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177818 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 05:46:19 +00:00
Michael Gottesman
4df66f74d9 Changed the method name PtrState.IsKnownIncremented() to PtrState.HasKnownPositiveRefCount().
Now said method matches namewise every other method which refers to
the member KnownPositiveRefCount of the class PtrState.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 05:31:01 +00:00
Hal Finkel
0e8fc6f87a Fix comparison of mixed signedness
177774 broke the lld-x86_64-darwin11 builder; error:
error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long')
  for (SI = 0; SI < Scavenged.size(); ++SI)
               ~~ ^ ~~~~~~~~~~~~~~~~

Fix this by making SI also unsigned.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-23 00:07:29 +00:00
Sean Silva
928ef439a5 [docs] Slight reword for precision.
The new wording cannot be construed as suggesting the use of
SmallVectorImpl<T> as e.g. a class member (just because the class
happens to be in an interface).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 23:52:38 +00:00
Sean Silva
0059eb1e2e [docs] Document usage of SmallVectorImpl in interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177775 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 23:41:29 +00:00
Hal Finkel
dc3beb9017 Allow the register scavenger to spill multiple registers
This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.

To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.

In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 23:32:27 +00:00
Manman Ren
a2e3834d16 Support in AAEvaluator to print alias queries of loads/stores with TBAA tags.
Add "evaluate-tbaa" to print alias queries of loads/stores. Alias queries
between pointers do not include TBAA tags.

Add testing case for "placement new". TBAA currently says NoAlias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177772 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 22:34:41 +00:00
John McCall
1f9c4407c0 Kill every call to @clang.arc.use in the ARC contract phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177769 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 21:38:36 +00:00
Bill Wendling
46125e1a8b Update test. There may be multiple catches, but those will be cleaned up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177758 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 20:36:39 +00:00
Bill Wendling
4c62502470 Add all clauses when merging the landing pads. Duplicates will be handled later on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177757 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 20:31:05 +00:00
David Blaikie
8faed2745c Swap the DIFile in DILexicalBlockFile out for the raw name/directory pair
This is the last change in transitioning all DIScopes to have a common prefix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177756 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 20:18:46 +00:00
David Blaikie
7b246860bd reorder the fields in DILexicalBlockFile to match the common prefix for DIScopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177754 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 19:13:22 +00:00