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5efabcf01d
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7612 Commits

Author SHA1 Message Date
Benjamin Kramer
5efabcf01d Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing. 
<stdin>:1:12: error: register %rax is only available in 64-bit mode
   incl    %rax
           ^~~~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142137 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 12:10:27 +00:00
Benjamin Kramer
f82edaffb1 X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands. 
<stdin>:1:4: error: invalid instruction mnemonic 'abc'
   abc incl    %edi
   ^~~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142135 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 11:28:29 +00:00
Craig Topper
b53fa8bf19 Add X86 BZHI instruction as well as BMI2 feature detection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 07:55:05 +00:00
Craig Topper
dc479c4a89 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 07:05:40 +00:00
Chris Lattner
d8b7aa2613 Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance 
the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 04:47:35 +00:00
Craig Topper
17730847d5 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 03:51:13 +00:00
Craig Topper
4145c49aa0 Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142089 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 00:21:51 +00:00
Craig Topper
566f233ba6 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-15 20:46:47 +00:00
Benjamin Kramer
003fad98cc SmallVector -> array 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142073 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-15 13:28:31 +00:00
Evan Cheng
b10946a5a9 A few 80-col violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141988 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 20:36:23 +00:00
Craig Topper
54a11176f6 Add X86 ANDN instruction. Including instruction selection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 07:06:56 +00:00
Craig Topper
909652f687 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 03:21:46 +00:00
Jakob Stoklund Olesen
ccbe603869 Ban rematerializable instructions with side effects. 
TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 01:00:49 +00:00
Jakob Stoklund Olesen
0a951fba75 V_SET0 has no side effects. 
TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.

This was part of the cause for PR11125, but the real bug was fixed
in r141923.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141924 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 00:39:50 +00:00
Eli Friedman
d83a54fd35 Simplify assertion, and avoid undefined shift. Based on patch by Ahmed Charles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141912 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 23:27:48 +00:00
Bill Wendling
4e68054b20 More closely follow libgcc, which has code after the `ret' instruction to 
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141859 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 08:24:19 +00:00
Bill Wendling
1203fe7fc8 Revert r141854 because it was causing failures: 
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 07:48:07 +00:00
Bill Wendling
82222c20be Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141856 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 07:42:32 +00:00
Craig Topper
8ab1d1e900 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 07:09:14 +00:00
Craig Topper
d501c714cd Add 'implicit EFLAGS' to patterns for popcnt and lzcnt 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-13 06:18:52 +00:00
Nick Lewycky
1f9c6860bf Fix indent in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 00:14:12 +00:00
Craig Topper
c48b301fb0 Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 07:13:09 +00:00
Craig Topper
227358e93c Make Ivy Bridge 16-bit floating point conversion instructions require AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141654 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 07:01:37 +00:00
Craig Topper
37f2167f15 Add X86 LZCNT instruction. Including instruction selection support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 06:44:02 +00:00
Craig Topper
29480fd798 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 04:34:23 +00:00
Lang Hames
4ad06e61c0 Fixed natural stack alignment for Linux x86-32. Thanks Eli. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141616 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 00:51:36 +00:00
Lang Hames
bb5b3f3359 Add a natural stack alignment field to TargetData, and prevent InstCombine from 
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.

The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 23:42:08 +00:00
Eli Friedman
dca62d53b7 Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:28:47 +00:00
Benjamin Kramer
717073c237 X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141571 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 19:35:07 +00:00
Nadav Rotem
a7934dd8e4 Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the 
instruction set has no 64-bit SRA support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 19:31:45 +00:00
Benjamin Kramer
a86a58695d X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:34:56 +00:00
Craig Topper
1f104804bf Put a bunch of calls to ToggleFeature behind proper if statements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141527 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 05:34:02 +00:00
Craig Topper
da394041c4 Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen
b7994fedcb Prevent potential NOREX bug. 
A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:

  %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
  TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2

If such a live range is ever split, its register class must not be
inflated to GR8.  The sub-register copy can only target GR8_NOREX.

I dont have a test case for this theoretical bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141500 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 20:20:03 +00:00
Jakob Stoklund Olesen
ed74482704 Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. 
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141499 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 18:28:28 +00:00
Jakob Stoklund Olesen
b66f18486a Constrain both operands on MOVZX32_NOREXrr8. 
This instruction is explicitly encoded without an REX prefix, so both
operands but be *_NOREX.

Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX
constraints are not satisfied.

This fixes a miscompilation in 20040709-2 in the gcc test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141410 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 20:15:54 +00:00
Evan Cheng
7c1780c5fe High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141371 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 17:21:44 +00:00
Craig Topper
75fe5f3bab Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 07:02:24 +00:00
Craig Topper
1b526a98e3 Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 05:53:50 +00:00
Craig Topper
25f6dfd108 Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 05:35:38 +00:00
Craig Topper
7ea16b01fa Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 06:44:41 +00:00
Peter Collingbourne
de8f33c199 Build system infrastructure for multiple tblgens. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 01:51:51 +00:00
Jakob Stoklund Olesen
9bb272c900 Override TRI::getSubClassWithSubReg for X86. 
There are fewer registers with sub_8bit sub-registers in 32-bit mode
than in 64-bit mode.  In 32-bit mode, sub_8bit behaves the same as
sub_8bit_hi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141206 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 20:26:33 +00:00
Craig Topper
41e59c7c34 Change C++ style comments to C style comments in X86 disassembler. Patch from Joe Abbey. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141162 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 03:29:32 +00:00
Owen Anderson
2fec6c5ff1 Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 23:26:17 +00:00
Craig Topper
6744a17dcf Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 06:30:42 +00:00
Craig Topper
581fe82c84 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 17:28:23 +00:00
Craig Topper
04c5be9f12 Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 08:14:29 +00:00
Craig Topper
7b22976de3 Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140993 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 07:51:09 +00:00
Craig Topper
82f131a017 Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 21:08:12 +00:00