Jakob Stoklund Olesen
708d06f7fb
Add an interface for SplitKit complement spill modes.
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SplitKit always computes a complement live range to cover the places
where the original live range was live, but no explicit region has been
allocated.
Currently, the complement live range is created to be as small as
possible - it never overlaps any of the regions. This minimizes
register pressure, but if the complement is going to be spilled anyway,
that is not very important. The spiller will eliminate redundant
spills, and hoist others by making the spill slot live range overlap
some of the regions created by splitting. Stack slots are cheap.
This patch adds the interface to enable spill modes in SplitKit. In
spill mode, SplitKit will assume that the complement is going to spill,
so it will allow it to overlap regions in order to avoid back-copies.
By doing some of the spiller's work early, the complement live range
becomes simpler. In some cases, it can become much simpler because no
extra PHI-defs are required. This will speed up both splitting and
spilling.
This is only the interface to enable spill modes, no implementation yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 16:49:21 +00:00
Jakob Stoklund Olesen
3d4ec14ffc
Update comments to reflect some (not so) recent changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 16:03:26 +00:00
Richard Osborne
a1d16b53e8
Associate a MemOperand with LDWCP nodes introduced during ISel.
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This information is required if we want LDWCP to be hoisted out of loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 14:43:23 +00:00
Richard Osborne
2cb6c1bd20
Mark LDWCP as having no side effects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 14:41:31 +00:00
Nadav Rotem
5ed0983200
Format patterns, remove unused X86blend patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139491 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 08:41:50 +00:00
Craig Topper
136046c9a2
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 23:19:54 +00:00
Craig Topper
038197988b
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 21:41:45 +00:00
Craig Topper
842f58f9be
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139484 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 20:23:20 +00:00
Nick Lewycky
e4481d8ce5
s/SequeuentiallyConsistent/SequentiallyConsistent/g
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139481 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 15:50:05 +00:00
Nick Lewycky
5366ca4e06
Fix verb tense agreement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 15:30:08 +00:00
Nadav Rotem
fbad25e120
CR fixes per Bruno's request.
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Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11 15:02:23 +00:00
Eli Friedman
cfeb55cdbc
Really un-XFAIL the testcase, like I said I would in r139458.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 02:02:27 +00:00
Eli Friedman
106f6e7a27
r139454 activates an assert in a case where we were doing the right thing anyway. Make that explicit, and un-XFAIL the testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 02:01:42 +00:00
Richard Trieu
81cbb0ad60
Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp and
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lib/ExecutionEngine/MCJIT/MCJIT.cpp from:
assert("error");
to:
assert(0 && "error");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:42:07 +00:00
Richard Trieu
2db8628085
Fixed an assert from:
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assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:26:21 +00:00
Andrew Trick
20151da8c3
[disable-iv-rewrite] Allow WidenIV to handle NSW/NUW operations
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better.
Don't immediately give up when an add operation can't be trivially
sign/zero-extended within a loop. If it has NSW/NUW flags, generate a
new expression with sign extended (non-recurrent) operand. As before,
if SCEV says that all sign extends are loop invariant, then we can
widen the operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139453 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:24:17 +00:00
Andrew Trick
543376743c
Set NSW/NUW flags on SCEVAddExpr when the operation is flagged as
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such.
I'm doing this now for completeness because I can't think of/remember
any reason that it was left out. I'm not sure it will help anything,
but if we don't do it we need to explain why in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:09:50 +00:00
Richard Trieu
2e3734e2d9
Fix asserts in CodeGen from:
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assert("error");
to:
assert(0 && "error");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139449 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 01:07:54 +00:00
Jim Grosbach
1ad60c2adc
Thumb2 parsing and encoding for MOV(immediate).
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Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10 00:15:36 +00:00
Akira Hatanaka
33ff5aeaa8
Fix test cases.
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Generate code for Mips32r1 unless a Mips32r2 feature is tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:14:58 +00:00
Owen Anderson
921d01ae1f
LDM writeback is not allowed if Rn is in the target register list.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:13:33 +00:00
Owen Anderson
112fb73502
Fix an ambiguously nested if.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:13:02 +00:00
Owen Anderson
cd4338fff5
Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139429 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:05:14 +00:00
Owen Anderson
08fef885eb
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:24:36 +00:00
Akira Hatanaka
46ac94ba8b
O64 will not be supported.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139421 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:22:48 +00:00
Akira Hatanaka
5881586745
Make F31 and D15 non-reserved registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:11:26 +00:00
Chris Lattner
c3ab388ba9
tidy up a bit
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:06:59 +00:00
Owen Anderson
51f6a7abf2
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:48:23 +00:00
Douglas Gregor
13d8baa3fc
Update Clang AST attribute reader tblgen generation to match with ASTReader change
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139414 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:37:29 +00:00
Akira Hatanaka
9a439affd7
Mips32 does not reserve even-numbered floating point registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:31:46 +00:00
Eli Friedman
9db817fd0c
Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:04:06 +00:00
Akira Hatanaka
8ddf6531b8
Drop support for Mips1 and Mips2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:45:50 +00:00
Nadav Rotem
8ffad56f8e
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:29:17 +00:00
Jim Grosbach
468709e43d
Thumb2 assembly parsing and encoding for MLA and MLS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:24:45 +00:00
Duncan Sands
a50c6d95e4
Don't tack "Instruction not interpretable yet!" onto the end of
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the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139398 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:22:48 +00:00
Jim Grosbach
84d043a8b3
Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:19:28 +00:00
Jim Grosbach
1e0fff17f3
Tidy up formatting a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139396 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:17:49 +00:00
Jim Grosbach
95102265a9
Thumb2 assembly parsing and encoding for LSL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139395 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:05:38 +00:00
Jim Grosbach
d4b72de3e2
Thumb2 assembly parsing and encoding for LDRT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139393 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:02:15 +00:00
Jim Grosbach
56806c2997
Thumb2 assembly parsing and encoding for LDRSHT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139392 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 20:01:18 +00:00
Jim Grosbach
a315a99093
Thumb2 assembly parsing and encoding for LDRSH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:54:30 +00:00
Jim Grosbach
578edfbfa0
Thumb2 assembly parsing and encoding for LDRSBT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139390 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:49:06 +00:00
Jim Grosbach
0811fe13d6
Thumb2 assembly parsing and encoding for LDRSB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:42:40 +00:00
Jim Grosbach
95d397c3b1
Thumb2 assembly parsing and encoding for LDRH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139386 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:13:53 +00:00
Jim Grosbach
1efd9a0e8b
Shuffle a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139385 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:09:54 +00:00
Akira Hatanaka
d199d0c59c
Drop support for Allegrex. Allegrex implements a variant of Mips2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 19:00:51 +00:00
Jim Grosbach
b6aed508e3
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 18:37:27 +00:00
Jakob Stoklund Olesen
1ab7c8ea03
Reapply r139247: Cache intermediate results during traceSiblingValue.
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In some cases such as interpreters using indirectbr, the CFG can be very
complicated, and live range splitting may be forced to insert a large
number of phi-defs. When that happens, traceSiblingValue can spend a
lot of time zipping around in the CFG looking for defs and reloads.
This patch causes more information to be cached in SibValues, and the
cached values are used to terminate searches early. This speeds up
spilling by 20x in one interpreter test case. For more typical code,
this is just a 10% speedup of spilling.
The previous version had bugs that caused miscompilations. They have
been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 18:11:41 +00:00
Andrew Trick
39d7802224
Comment formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 17:35:10 +00:00
Devang Patel
9b4a2ac196
Update docs to reflect recent addition of new CompileUnit elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139374 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 17:07:15 +00:00