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49643 Commits

Author SHA1 Message Date
Richard Trieu
81cbb0ad60 Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp and 
lib/ExecutionEngine/MCJIT/MCJIT.cpp from:

  assert("error");

to:

  assert(0 && "error");



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139456 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 01:42:07 +00:00
Richard Trieu
2db8628085 Fixed an assert from: 
assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 01:26:21 +00:00
Andrew Trick
20151da8c3 [disable-iv-rewrite] Allow WidenIV to handle NSW/NUW operations 
better.

Don't immediately give up when an add operation can't be trivially
sign/zero-extended within a loop. If it has NSW/NUW flags, generate a
new expression with sign extended (non-recurrent) operand. As before,
if SCEV says that all sign extends are loop invariant, then we can
widen the operation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139453 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 01:24:17 +00:00
Andrew Trick
543376743c Set NSW/NUW flags on SCEVAddExpr when the operation is flagged as 
such.

I'm doing this now for completeness because I can't think of/remember
any reason that it was left out. I'm not sure it will help anything,
but if we don't do it we need to explain why in comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 01:09:50 +00:00
Richard Trieu
2e3734e2d9 Fix asserts in CodeGen from: 
assert("error");

to:

  assert(0 && "error");



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139449 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 01:07:54 +00:00
Jim Grosbach
1ad60c2adc Thumb2 parsing and encoding for MOV(immediate). 
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-10 00:15:36 +00:00
Owen Anderson
921d01ae1f LDM writeback is not allowed if Rn is in the target register list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:13:33 +00:00
Owen Anderson
112fb73502 Fix an ambiguously nested if. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139431 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:13:02 +00:00
Owen Anderson
cd4338fff5 Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139429 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:05:14 +00:00
Owen Anderson
08fef885eb Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:24:36 +00:00
Akira Hatanaka
46ac94ba8b O64 will not be supported. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139421 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:22:48 +00:00
Akira Hatanaka
5881586745 Make F31 and D15 non-reserved registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:11:26 +00:00
Chris Lattner
c3ab388ba9 tidy up a bit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139419 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 22:06:59 +00:00
Owen Anderson
51f6a7abf2 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:48:23 +00:00
Akira Hatanaka
9a439affd7 Mips32 does not reserve even-numbered floating point registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139412 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:31:46 +00:00
Eli Friedman
9db817fd0c Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:04:06 +00:00
Akira Hatanaka
8ddf6531b8 Drop support for Mips1 and Mips2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:45:50 +00:00
Nadav Rotem
8ffad56f8e Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:29:17 +00:00
Jim Grosbach
468709e43d Thumb2 assembly parsing and encoding for MLA and MLS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:24:45 +00:00
Duncan Sands
a50c6d95e4 Don't tack "Instruction not interpretable yet!" onto the end of 
the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139398 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 20:22:48 +00:00
Jim Grosbach
0811fe13d6 Thumb2 assembly parsing and encoding for LDRSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:42:40 +00:00
Akira Hatanaka
d199d0c59c Drop support for Allegrex. Allegrex implements a variant of Mips2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 19:00:51 +00:00
Jim Grosbach
b6aed508e3 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 18:37:27 +00:00
Jakob Stoklund Olesen
1ab7c8ea03 Reapply r139247: Cache intermediate results during traceSiblingValue. 
In some cases such as interpreters using indirectbr, the CFG can be very
complicated, and live range splitting may be forced to insert a large
number of phi-defs.  When that happens, traceSiblingValue can spend a
lot of time zipping around in the CFG looking for defs and reloads.

This patch causes more information to be cached in SibValues, and the
cached values are used to terminate searches early.  This speeds up
spilling by 20x in one interpreter test case.  For more typical code,
this is just a 10% speedup of spilling.

The previous version had bugs that caused miscompilations. They have
been fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 18:11:41 +00:00
Andrew Trick
39d7802224 Comment formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139375 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 17:35:10 +00:00
Craig Topper
ccfa4ed4e0 Fix handling of Intel syntax disassembling of movs and stos to stop being blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 05:40:53 +00:00
Akira Hatanaka
ad5f0c9e73 Change default target architecture from Mips1 to Mips32r1 in preparation for 
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 01:13:27 +00:00
Benjamin Kramer
d40b0b0a06 Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139343 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 00:22:05 +00:00
Nick Lewycky
58856eae16 Fix release build: 
MachOObjectFile.cpp:524: error: unused variable 'NumLoadCommands' [-Wunused-variable]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139341 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 00:16:50 +00:00
Akira Hatanaka
404507e7d8 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 00:13:35 +00:00
Devang Patel
9aee335c23 Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139330 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:59:09 +00:00
Owen Anderson
441462f932 All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:48:37 +00:00
Owen Anderson
d2fc31b3f7 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:42:49 +00:00
Eric Christopher
d1e002a0a3 Formatting and typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:17:40 +00:00
Nadav Rotem
ee64be9c17 Dix the 80-columns and remove unsupported v8i16 type from the list of legal vselect types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:17:35 +00:00
Jim Grosbach
a77295db19 Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 22:07:06 +00:00
Bruno Cardoso Lopes
7ec8fb8830 Add a AVX version of a simple i64 -> f64 bitcast. This could be 
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 21:52:33 +00:00
Kevin Enderby
5afc19002e Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom 
without a base symbol that must not have a relocation entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 20:53:44 +00:00
Benjamin Kramer
0fcab076f0 Add support for relocations to ObjectFile. 
Patch by Danil Malyshev!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139314 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 20:52:17 +00:00
Bruno Cardoso Lopes
cbf479df8a * Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a 
single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.

* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }

* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.

* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.

* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).

Patch by David Meyer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139311 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 18:35:57 +00:00
Bruno Cardoso Lopes
814c6ced85 Add AVX versions of blend vector operations and fix some issues noticed 
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139305 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes
7db2d3a504 Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl. 
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139304 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 18:05:02 +00:00
Nadav Rotem
ffe3e7da84 Add X86-SSE4 codegen support for vector-select. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 08:11:19 +00:00
Eli Friedman
184166da61 A couple minor corrections to r139276. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139277 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 02:37:07 +00:00
Eli Friedman
81ac8ddc67 Fix the logic in BasicAliasAnalysis::aliasGEP for comparing GEP's with variable differences so that it actually does something sane. Fixes PR10881. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139276 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 02:23:31 +00:00
Jim Grosbach
e64fb28da1 Thumb2 assembly parsing and encoding for LDR post-indexed. 
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 01:01:32 +00:00
Jim Grosbach
eeec025cf5 Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 00:39:19 +00:00
Owen Anderson
170580e8f4 Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 00:11:18 +00:00
Jim Grosbach
f0eee6eca8 Thumb2 assembly parsing and encoding for LDRBT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:39:14 +00:00
Jim Grosbach
ab899c1bcc Thumb2 assembly parsing and encoding for LDR(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:10:15 +00:00