Commit Graph

40690 Commits

Author SHA1 Message Date
Johnny Chen
270159fcc2 The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 01:40:54 +00:00
Daniel Dunbar
09062b1672 MC/X86/AsmParser: Give an explicit error message when we reject an instruction
because it could have an ambiguous suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 00:55:42 +00:00
Daniel Dunbar
f1e29d4c21 MC/AsmParser: Push the burdon of emitting diagnostics about unmatched
instructions onto the target specific parser, which can do a better job.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 00:55:38 +00:00
Daniel Dunbar
4f98f83459 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl',
target specific parsers can adapt the TargetAsmParser to this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 00:55:32 +00:00
Johnny Chen
7def14f40f Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
Added two test cases to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:35:12 +00:00
Devang Patel
ebd53742c6 Even if a variable has constant value all the time, it is still a variable in gdb's eyes.
Tested by scope.exp in gdb testsuite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:17:54 +00:00
Bob Wilson
eaf1c98a7c Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode.  This also fixes part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:10:46 +00:00
Jakob Stoklund Olesen
d29583bd32 Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk.
When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110874 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 23:08:22 +00:00
Owen Anderson
cf6abd2486 Fix a subtle use-after-free issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110863 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 22:36:04 +00:00
Nick Lewycky
7f9ef4bb51 Clean up ConstantRange a bit:
- remove ashr which never worked.
 - fix lshr and shl and add tests.
 - remove dead function "intersect1Wrapped".
 - add a new sub method to subtract ranges, with test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 22:04:36 +00:00
Dan Gohman
bd4d66d56a Make LoopPass::getContainedPass return a LoopPass* instead of a Pass*
and remove casts from all its callers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 20:34:43 +00:00
Dan Gohman
fa5c2a67c3 Remove BasicBlockPass::runOnFunction, which was unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110847 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 20:28:16 +00:00
Dan Gohman
1f9a1608a6 Delete FunctionPass::run, which is unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 19:11:05 +00:00
Dan Gohman
73e8800229 Delete FunctionPass::runOnModule, which is unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 19:05:53 +00:00
Dan Gohman
b68f274b6d Don't use unsigned char for alignments in TargetData. There aren't
that many of these things, so the memory savings isn't significant,
and there are now situations where there can be alignments greater
than 128.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 18:15:01 +00:00
Dan Gohman
d881627d33 Use ISD::ADD instead of ISD::SUB with a negated constant. This
avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.

Also, use getCopyFromReg instead of getRegister to read a
physical register's value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 18:14:00 +00:00
Jakob Stoklund Olesen
dfa28b157d Fix a FIXME. The SlotIndex::Slot enum should be private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110826 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 16:50:17 +00:00
Jim Grosbach
fcba5e6b64 cortex m4 has floating point support, but only single precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 15:44:15 +00:00
Bill Wendling
de2b151dbf Consider this code snippet:
float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 08:43:16 +00:00
Evan Cheng
7b4d31176e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 07:17:46 +00:00
Evan Cheng
8d62e713ea ArchV7M implies HW division instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 07:00:16 +00:00
Evan Cheng
cb5ce6e62b ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:57:53 +00:00
Evan Cheng
d6b4632256 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:51:54 +00:00
Daniel Dunbar
345a9a6269 MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:20 +00:00
Daniel Dunbar
5747b13af8 MC/ARM: Split mnemonic on '.' characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110793 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:16 +00:00
Daniel Dunbar
fa315de8f4 MC/ARM: Fill in ARMOperand::dump a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110792 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:12 +00:00
Daniel Dunbar
3c14ca47fc llvm-mc: Add -show-inst-operands, for dumping the parsed instruction representation before matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:09 +00:00
Daniel Dunbar
b3cb696794 MCAsmParser: Add dump() hook to MCParsedAsmOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:04 +00:00
Daniel Dunbar
8462b30548 MC/ARM: Add an ARMOperand class for condition codes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:36:53 +00:00
Evan Cheng
ee34987fd5 Really control isel of barrier instructions with cpu feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:36:31 +00:00
Evan Cheng
c7569ed4e4 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit
instructions: dmb, dsb, isb, msr, and mrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:30:38 +00:00
Evan Cheng
11db068721 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:22:01 +00:00
Daniel Dunbar
3483acabf0 MC/ARM: Switch to using the generated match functions instead of stub implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110783 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 05:24:50 +00:00
Daniel Dunbar
a7ac688d55 MC/ARM: Enable generation of the ARM asm matcher, not that it can do much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 05:09:20 +00:00
Daniel Dunbar
3bcd9f7902 ARM: Mark some disassembler only instructions as not available for matching --
for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 04:46:13 +00:00
Daniel Dunbar
9db683b06c ARM: Quote $p in an asm string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 04:46:10 +00:00
Owen Anderson
2d0f2470ff Improve indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110778 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 04:24:25 +00:00
Bill Wendling
38ae997e63 Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 00:23:00 +00:00
Bill Wendling
0cce3dd326 Mark ARM compare instructions as isCompare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 00:22:27 +00:00
Dan Gohman
4ee87398e8 When analyzing loop exit conditions combined with and and or, don't
make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 00:12:36 +00:00
Bob Wilson
9a1c189d9e Add a separate ARM instruction format for Saturate instructions.
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 00:01:18 +00:00
Dan Gohman
af08a36bd6 Rename and reorder the arguments to isImpliedCond, for consistency and clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 23:46:30 +00:00
Evan Cheng
3611d9e25d CBZ and CBNZ are implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 23:27:11 +00:00
Bruno Cardoso Lopes
045573ce21 Add AVX matching patterns to Packed Bit Test intrinsics.
Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 23:25:42 +00:00
Owen Anderson
625051be7e Now that we're using ConstantRange to represent potential values, make use of that represenation to
create constraints from comparisons other than eq/neq.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 23:20:01 +00:00
Nate Begeman
95743d8748 Add the minimal amount of smarts necessary to instcombine of shufflevectors to recognize
patterns generated by clang for transpose of a matrix in generic vectors.  This is made
of two parts:

1) Propagating vector extracts of hi/lo half into their users
2) Recognizing an insertion of even elements followed by the odd elements as an unpack.

Testcase to come, but this shrinks the # of shuffle instructions generated on x86 from ~40 to the minimal 8.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110734 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 21:38:12 +00:00
Bill Wendling
75486dbf4e Turn optimize compares back on with fix. We needed to test that a machine op was
a register before checking if it was defined.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110733 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 21:38:11 +00:00
Jakob Stoklund Olesen
a516e94cf1 Give up on register class recalculation when the register is used with subreg
operands. We don't currently have a hook to provide "the largest super class of
A where all registers' getSubReg(subidx) is valid and in B".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 21:16:16 +00:00
Dan Gohman
a8c58a6f59 Revert r110718; it broke clang-i386-darwin9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 20:49:33 +00:00
Jakob Stoklund Olesen
b67b12ea64 Avoid editing the current live interval during remat.
The live interval may be used for a spill slot as well, and that spill slot
could be shared by split registers. We cannot shrink it, even if we know the
current register won't need the spill slot in that range.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 20:45:07 +00:00
Jakob Stoklund Olesen
987eeccb61 More debug spew
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 20:45:01 +00:00
Bill Wendling
a54e3cddce Turn optimize cmps on by default so that we can get some testing by the nightly
ARM testers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 20:23:02 +00:00
Devang Patel
6bf058c9aa Add missing argument. CreateCompositeTypeEx() users, please verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 20:22:49 +00:00
Owen Anderson
9f01406179 Switch over to using ConstantRange to track integral values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 20:03:09 +00:00
Devang Patel
e7e5a0f6fb Do not forget debug info for enums. Use named mdnode to keep track of these types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 20:01:20 +00:00
Evan Cheng
5818032521 Delete some unused instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 19:36:22 +00:00
Evan Cheng
ac096808a3 Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 19:30:19 +00:00
Jakob Stoklund Olesen
9db3ea46cb Implement register class inflation.
When splitting a live range, the new registers have fewer uses and the
permissible register class may be less constrained. Recompute the register class
constraint from the uses of new registers created for a split. This may let them
be allocated from a larger set, possibly avoiding a spill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 18:37:40 +00:00
Daniel Dunbar
4bd828f781 Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP
register is", it breaks a couple test-suite tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 18:32:02 +00:00
Daniel Dunbar
e25c6b95ce MC/AsmParser: Fix a bug in macro argument parsing, which was dropping
parentheses from argument lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 17:38:52 +00:00
Jakob Stoklund Olesen
08e93b14c3 Recalculate the spill weight and allocation hint for virtual registers created
during live range splitting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110686 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 17:07:22 +00:00
Michael J. Spencer
b0f3b3e7de Revert "MC/MachO: Fix possible null pointer dereference."
This reverts commit 110575.

Target.isAbsolute() is true if SD would be null.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 16:00:49 +00:00
Chandler Carruth
0db86fe097 Mark this variable as used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 10:39:25 +00:00
Tobias Grosser
73362c820b RegionInfo: Do not assert if a BB is not part of the dominance tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110665 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 09:54:35 +00:00
Devang Patel
2936807564 Handle TAG_constant for integers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110656 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 07:11:13 +00:00
Evan Cheng
c9aed19747 Fix ARM hasFP() semantics. It should return true whenever FP register is
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.

This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 06:26:49 +00:00
Bill Wendling
94f7950e4d Update CMake...sorry for the breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 05:16:06 +00:00
Devang Patel
ecbd8e866b Simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 04:12:17 +00:00
Devang Patel
85e9580e25 Drop "const". It does not add value here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 04:09:06 +00:00
Bruno Cardoso Lopes
9f798e9a9e Add AVX movnt{pd,ps,dq} 256-bit intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110650 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 02:49:24 +00:00
Evan Cheng
c120af4567 Add missing null check reported by Amaury Pouly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110649 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 02:39:45 +00:00
Bruno Cardoso Lopes
fcfcca1d9b Add AVX movmsk 256-bit intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 02:34:56 +00:00
Bruno Cardoso Lopes
405f11b300 Support AVX 256-bit load and store intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 01:43:16 +00:00
Devang Patel
9fa539ce33 Do not include file static variable in pubnames list.
Refactor and simplify code to avoid redundant checks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 01:37:23 +00:00
Chris Lattner
60e72d9ebc remove code setting rw locks to PTHREAD_PROCESS_PRIVATE, which
is the default.  Patch by NAKAMURA Takumi!


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2010-08-10 00:34:06 +00:00
Bruno Cardoso Lopes
6719784148 Patterns to match AVX cmp instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 00:13:20 +00:00
Jakob Stoklund Olesen
df30cf9e61 Transpose the calculation of spill weights such that we are calculating one
register at a time. This turns out to be slightly faster than iterating over
instructions, but more importantly, it allows us to compute spill weights for
new registers created after the spill weight pass has run.

Also compute the allocation hint at the same time as the spill weight. This
allows us to use the spill weight as a cost metric for copies, and choose the
most profitable hint if there is more than one possibility.

The new hints provide a very small (< 0.1%) but universal code size improvement.

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2010-08-10 00:02:26 +00:00
Bruno Cardoso Lopes
533a7df02d Add matching patterns for vblend AVX intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110630 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 00:02:05 +00:00
Bill Wendling
6cdb1abe4e Merge the OptimizeExts and OptimizeCmps passes into one PeepholeOptimizer
pass. This pass should expand with all of the small, fine-grained optimization
passes to reduce compile time and increase happiment.


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2010-08-09 23:59:04 +00:00
Devang Patel
02ecdefbe4 Undo accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110623 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 23:28:52 +00:00
Devang Patel
450b793a04 Simplify. Avoid redundant checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 23:26:06 +00:00
Eric Christopher
5cb33a384f Wording.
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2010-08-09 22:52:47 +00:00
Kevin Enderby
b07ce60981 Next bit of support for the dwarf .file directive. This patch takes the
previously collected info from the .file directives and outputs the encoded
bytes for it.  For now this is only in the Mach-O streamer but at some point
will move to a more generic place.


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2010-08-09 22:52:14 +00:00
Evan Cheng
b000d683c8 ARMBaseRegisterInfo::hasFP() has been broken for a while now. :-(
This will always be false before PEI:
(DisableFramePointerElim(MF) && MFI->adjustsStack())
Which means it's going to make r11 available as a general purpose register even
if -disable-fp-elim is specified. It's working on Darwin only because r7 is
always reserved. But it's obviously broken for other targets.


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2010-08-09 22:32:45 +00:00
Bruno Cardoso Lopes
93f6c1ec6e Add VCVTPD2PS, VCVTPS2DQ, VCVTPS2PDY, VCVTTPD2DQY, VCVTTPS2DQ and VCVTPD2DQ 256-bit conversion intrinsics
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2010-08-09 21:51:56 +00:00
Devang Patel
2739896cdd Refactor.
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2010-08-09 21:39:24 +00:00
Bruno Cardoso Lopes
8468157278 Add patterns to AVX conversions instructions. Do that instead of declaring more intructions whenever is possible, more coming
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2010-08-09 21:24:59 +00:00
Nick Lewycky
3221834f8a Fix a use after free error caught by the valgrind builders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 21:03:28 +00:00
Devang Patel
8bd11de33e Refactoring. Update DbgVarible to handle queries itself.
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2010-08-09 21:01:39 +00:00
Owen Anderson
2f3ffb80fa Add ConstantRange information to the debugging output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110598 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 20:50:46 +00:00
Eli Friedman
4fffb345ed PR7853: fix a silly mistake introduced in r101899, and add a test to make sure
it doesn't regress again.



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2010-08-09 20:49:43 +00:00
Oscar Fuentes
4951870e04 CMake: eliminated unnecessary target_link_libraries.
Next time the build is broken due to wrong library dependencies, just
try building again (if you are on some Unix and are building all LLVM
targets) or ask someone to commit the regenerated LLVMLibDeps.cmake.

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2010-08-09 20:33:08 +00:00
Devang Patel
8162574aaa It is ok, and convenient, to pass descriptors by value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110590 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 20:20:05 +00:00
Jakob Stoklund Olesen
e4b9c4f187 A REG_SEQUENCE instruction may use the same register twice.
If we are emitting COPY instructions for the REG_SEQUENCE, make sure the kill
flag goes on the last COPY. Otherwise we may be using a killed register.

<rdar://problem/8287792>

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2010-08-09 20:19:16 +00:00
Evan Cheng
9de1ac267e Explicitly initialize SlowFPBrcc and Pref32BitThumb to false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 19:19:36 +00:00
Devang Patel
e03161c28e Rename a method.
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2010-08-09 18:51:29 +00:00
Evan Cheng
e44be63816 Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations.
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2010-08-09 18:35:19 +00:00
Bruno Cardoso Lopes
ad4910429c Memory version of vcvtdq2pd intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 18:20:14 +00:00
Bruno Cardoso Lopes
251871ca66 Patterns to match vinsert, vbroadcast, vmovmask and vcvtdq2pd AVX intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 18:03:43 +00:00
Evan Cheng
e8846feaa1 Add an option to disable 32 -> 16-bit Thumb2 size reduction pass for experimentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110579 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 17:16:10 +00:00