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266 Commits

Author SHA1 Message Date
Renato Golin
719927a68f Emitting ARM build attributes and values as ULEB, rather than char. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137115 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 09:50:10 +00:00
Owen Anderson
793e79601f Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 20:54:26 +00:00
Evan Cheng
4b64e8a9e1 Separate MCInstPrinter registration from AsmPrinter registration. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 21:20:24 +00:00
Evan Cheng
ee04a6d3a4 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 23:34:39 +00:00
Jim Grosbach
0b44aea7b5 Use tPseudoExpand for tTAILJMPrND and tTAILJMPr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134734 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 20:39:19 +00:00
Jim Grosbach
af7f2d6b67 Use tPseudoExpand for tTAILJMPd and tTAILJMPdND. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134732 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 20:32:21 +00:00
Jim Grosbach
245f5e8e2a Use ARMPseudoExpand for ARM tail calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134719 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 18:50:22 +00:00
Jim Grosbach
4559a7bcfd Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred. 
TableGen'erated MC lowering pseudo-expansion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 18:15:12 +00:00
Jim Grosbach
53e3fc463e Use TableGen'erated pseudo lowering for ARM. 
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134705 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 17:40:42 +00:00
Cameron Zwarich
375db7f39a The VMLA instruction and its friends are not actually fused; they're plain old 
multiply-accumulate instructions with separate rounding steps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134609 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 08:28:52 +00:00
Evan Cheng
b262799d49 createMCInstPrinter doesn't need TargetMachine anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134525 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-06 19:45:42 +00:00
Jim Grosbach
2a7b41ba4d Refact ARM Thumb1 tMOVr instruction family. 
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 23:38:17 +00:00
Jim Grosbach
63b46faeb8 Thumb1 register to register MOV instruction is predicable. 
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 22:10:46 +00:00
Jim Grosbach
16f9924000 Pseudo-ize the t2LDMIA_RET instruction. 
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134173 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 18:25:42 +00:00
Jim Grosbach
4629d50501 Pseudo-ize the Thumb tPOP_RET instruction. 
It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 17:34:04 +00:00
Jim Grosbach
f6fd90910a Remove redundant Thumb2 ADD/SUB SP instruction definitions. 
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-29 23:25:04 +00:00
Eric Christopher
3c14f24c9d Implement the 'M' output modifier for arm inline asm. This is fairly 
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.

rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 01:40:44 +00:00
Rafael Espindola
5b23b7fe31 Make size computation less brittle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132222 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 22:05:41 +00:00
Eric Christopher
32bfb2c513 Reorganize these slightly according to operand type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132128 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 18:22:26 +00:00
Cameron Zwarich
421b106872 Mark tBX as an indirect branch rather than a return. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 03:41:12 +00:00
Cameron Zwarich
ad70f6d2b1 Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132086 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 21:53:50 +00:00
Eric Christopher
8f89463894 Implement the 'm' modifier. Note that it only works for memory operands. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 20:51:58 +00:00
Cameron Zwarich
106acd4158 Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This 
fixes <rdar://problem/9495913>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:45:27 +00:00
Cameron Zwarich
b36c1ae6d5 Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better 
reflect their actual meaning and match the ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132039 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:45:14 +00:00
Eric Christopher
4db7dec70b Implement the arm 'L' asm modifier. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 23:27:13 +00:00
Eric Christopher
e1739d598d Implement the immediate part of the 'B' modifier. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132023 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 23:15:43 +00:00
Eric Christopher
fef50062ea Add more unimplemented asm modifiers and some documentation of what they 
do.

Part of rdar://9119939.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 22:27:43 +00:00
Eric Christopher
0628d38085 Add support for the arm 'y' asm modifier. 
Fixes part of rdar://9444657


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132011 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 22:10:34 +00:00
Cameron Zwarich
d34d429401 Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches 
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131894 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-23 01:57:17 +00:00
Rafael Espindola
b8adb8af0f adds some attributes to attribute section when cpu is "xscale" 
(this is what used in Android NDK, when architecture is ARMv5)

patch by Koan-Sin Tan

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 20:10:34 +00:00
Rafael Espindola
6469540adf sets bit 0 of the function address of thumb function in .symtab 
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)

Patch by Koan-Sin Tan!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 16:17:21 +00:00
Devang Patel
64915dec28 Do not emit location expression size twice. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130854 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 19:00:57 +00:00
Devang Patel
c26f5447e3 Teach dwarf writer to handle complex address expression for .debug_loc entries. 
This fixes clang generated blocks' variables' debug info.
Radar 9279956.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130373 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-28 02:22:40 +00:00
Devang Patel
0be77dff11 Revert r130178. It turned out to be not the optimal path to emit complex location expressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130326 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-27 20:29:27 +00:00
Devang Patel
0c99861836 Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130178 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-26 00:12:46 +00:00
Devang Patel
0a6ea83f39 Add asserts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-22 16:44:29 +00:00
Devang Patel
71f3f1146f Fix DWARF description of Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129952 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 23:22:35 +00:00
Devang Patel
27f5acb7d4 Fix DWARF description of S registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-21 22:48:26 +00:00
Chris Lattner
7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 05:18:47 +00:00
Bill Wendling
a5c177e70a We need to pass the TargetMachine object to the InstPrinter if we are printing 
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.

This is part of a work-in-progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-21 04:13:46 +00:00
Jim Grosbach
5edf24efac Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches. 
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127637 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-15 00:30:40 +00:00
Jim Grosbach
f859a545de Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same 
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127515 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-12 00:45:26 +00:00
Jim Grosbach
72422d38ba Pseudo-ize the ARM 'B' instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127510 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 23:24:15 +00:00
Jim Grosbach
dd11988c99 Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side- 
effect that we get proper instruction printing using the "pop" mnemonic for it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-11 22:51:41 +00:00
Anton Korobeynikov
e516379d2a ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 18:44:00 +00:00
Anton Korobeynikov
b3fcc06d21 In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 18:43:55 +00:00
Anton Korobeynikov
3daccd82d3 Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 18:43:50 +00:00
Anton Korobeynikov
7a764168b9 Add unwind information emission for thumb stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 18:43:43 +00:00
Anton Korobeynikov
57caad7a33 Preliminary support for ARM frame save directives emission via MI flags. 
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 18:43:32 +00:00
Renato Golin
e89a05337a Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126882 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 21:20:09 +00:00