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13143 Commits

Author SHA1 Message Date
Evan Cheng
400073d546 On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 07:40:29 +00:00
Eric Christopher
5e63990271 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91657 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 02:12:53 +00:00
Evan Cheng
c7928f8f4e Re-apply 91623 now that I actually know what I was trying to do. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91655 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 01:59:21 +00:00
Bob Wilson
5afffaed5c Handle ARM inline asm "w" constraints with 64-bit ("d") registers. 
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 01:03:29 +00:00
John McCall
c226fe3c3e Pass the error string directly to llvm_unreachable instead of the residual 
(0 && "error").  Rough consensus seems to be that g++ *should* be diagnosing
this because the pointer makes it not an ICE in c++03.  Everyone agrees that
the current standard is silly and null-pointer-ness should not be based on
ICE-ness.  Excellent fight scene in Act II, denouement weak, two stars.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91644 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 00:27:18 +00:00
Sean Callanan
108934c65d Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 00:01:26 +00:00
Jeffrey Yasskin
08ce53996e Revert r91623 to unbreak the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-17 22:44:34 +00:00
Evan Cheng
73ebbd8aac Remove an unused option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91623 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-17 21:23:58 +00:00
Chris Lattner
551dec592f finish cleaning up StructLayoutMap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91612 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-17 20:00:21 +00:00
Ken Dyck
70d0ef1459 In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of 
incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91602 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-17 15:31:52 +00:00
Johnny Chen
caedfbc6ae Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91571 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 23:36:52 +00:00
John McCall
6eeccd4aa4 Silence a clang warning about the deprecated (but perfectly reasonable in 
context) increment-of-bool idiom.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91564 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 20:31:50 +00:00
Jim Grosbach
587b072f23 Mark STREX* as earlyclobber for the success result register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91555 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 19:44:06 +00:00
Johnny Chen
bbc71b2904 Add encoding bits for some Thumb instructions. Plus explicitly set the top two 
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91496 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 02:32:54 +00:00
Evan Cheng
2e489c4f9d Re-enable 91381 with fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91489 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 00:53:11 +00:00
John McCall
bd13cb911c Every anonymous namespace is different. Caught by clang++. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91481 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 00:15:28 +00:00
Jeffrey Yasskin
32d7e6ebde Change indirect-globals to use a dedicated allocIndirectGV. This lets us 
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface.  It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91464 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 22:42:46 +00:00
Johnny Chen
d68e119c0f Added encoding bits for the Thumb ISA. Initial checkin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91434 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 17:24:14 +00:00
Evan Cheng
dba6cac0d4 Fix an encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91417 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 06:49:02 +00:00
Kenneth Uildriks
76df3f398c For fastcc on x86, let ECX be used as a return register after EAX and EDX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91410 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 03:27:52 +00:00
Evan Cheng
d7760a4905 Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91405 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 03:07:11 +00:00
Evan Cheng
ad9c0a3d8b Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 00:53:42 +00:00
Jim Grosbach
c67b556b5b nand atomic requires opposite operand ordering 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91371 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 00:12:35 +00:00
Dan Gohman
2e141d744e Fix integer cast code to handle vector types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 23:40:38 +00:00
Johnny Chen
ec689151f2 Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate 
between BR_JTr and STREXD.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91339 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 21:51:34 +00:00
Jim Grosbach
80dd125e17 v6 sync insn copy/paste error 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91333 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 21:33:32 +00:00
Jim Grosbach
7c03dbd8ed Add ARMv6 memory and sync barrier instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91329 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 21:24:16 +00:00
Johnny Chen
c474796438 Fixed encoding bits typo of ldrexd/strexd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91327 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 21:01:46 +00:00
Jim Grosbach
a36c8f2c2e Thumb2 atomic operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91321 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 20:14:59 +00:00
Chris Lattner
cdfb302876 fix an obvious bug found by clang++ and collapse a redundant if. 
Here's the diagnostic from clang:

/Volumes/Data/dgregor/Projects/llvm/lib/Target/CppBackend/CPPBackend.cpp:989:23: warning: 'gv' is always NULL in this context
        printConstant(gv);
                      ^
1 diagnostic generated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91318 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 19:34:32 +00:00
Jim Grosbach
a623f5a58d correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91313 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 19:24:11 +00:00
Jim Grosbach
c219e4dd59 add Thumb2 atomic and memory barrier instruction definitions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91310 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 18:56:47 +00:00
Jim Grosbach
015d3b5704 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91307 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 18:36:32 +00:00
Jim Grosbach
f6b2862e81 ARM memory barrier instructions are not predicable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91305 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 18:31:20 +00:00
Jim Grosbach
d7d72d66b7 add ldrexd/strexd instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91284 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 17:02:55 +00:00
Bill Wendling
85de1e5bad Whitespace changes, comment clarification. No functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91274 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 06:51:19 +00:00
Jim Grosbach
c3c2354ec9 atomic binary operations up to 32-bits wide. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91260 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-14 04:22:04 +00:00
Anton Korobeynikov
cdcad11c94 Do not allow uninitialize access during debug printing 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91232 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-13 01:00:32 +00:00
Eli Friedman
bcae205a4b More info on this transformation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91230 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 23:23:43 +00:00
Eli Friedman
1555473387 Remove some stuff that's already implemented. Also, remove the note about 
merging x >u 5 and x <s 20 because it's impossible to implement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91228 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 21:41:48 +00:00
Evan Cheng
dd99f3a7dc Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91223 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 20:03:14 +00:00
Anton Korobeynikov
2625de35ed Implement variable-width shifts. 
No testcase yet - it seems we're exposing generic codegen bugs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91221 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 18:55:37 +00:00
Evan Cheng
04ab19cb14 Add comment about potential partial register stall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91220 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 18:55:26 +00:00
Evan Cheng
15b0d97068 Fix an obvious bug. No test case since LEA16r is not being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91219 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 18:51:56 +00:00
Jim Grosbach
e801dc4a7b Framework for atomic binary operations. The emitter for the pseudo instructions 
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91200 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 01:40:06 +00:00
Anton Korobeynikov
8d1ffbd1ad Lower setcc branchless, if this is profitable. 
Based on the patch by Brian Lucas!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91175 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 23:01:29 +00:00
Dan Gohman
87862e77bb Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91158 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 21:31:27 +00:00
Jim Grosbach
c8f9e4fdc5 memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91150 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 20:29:53 +00:00
Anton Korobeynikov
817a46454a Honour setHasCalls() set from isel. 
This is used in some weird cases like general dynamic TLS model.
This fixes PR5723

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91144 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 19:39:55 +00:00
Johnny Chen
0291d7ed09 Store Register Exclusive should leave the source register Inst{3-0} unspecified. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91143 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-11 19:37:26 +00:00