Commit Graph

108 Commits

Author SHA1 Message Date
Vladimir Medic
e925f7dbbf This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-16 10:29:42 +00:00
Akira Hatanaka
3e6758541b [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-07 00:52:30 +00:00
Akira Hatanaka
a796d90c0e [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
Also, fix predicates.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 00:55:15 +00:00
Akira Hatanaka
b1f4f120a5 [mips] Add support for mfhc1 and mthc1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 23:47:25 +00:00
Akira Hatanaka
c89cb45ecb [mips] Remove predicates that were incorrectly or unnecessarily added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188845 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 23:21:55 +00:00
Akira Hatanaka
3531db14c6 [mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 22:58:56 +00:00
Akira Hatanaka
a98a486ad1 [mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 21:08:22 +00:00
Akira Hatanaka
491d04969d [mips] Rename accumulator register classes and FP register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:54:26 +00:00
Akira Hatanaka
1858786285 [mips] Rename register classes CPURegs and CPU64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:08:38 +00:00
Vladimir Medic
b67775df0c This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 10:12:14 +00:00
Akira Hatanaka
407883b69b [mips] Fix FP conditional move instructions to have explicit FP condition code
register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 20:51:20 +00:00
Akira Hatanaka
83d8ef133b [mips] Fix FP branch instructions to have explicit FP condition code register
operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 20:13:47 +00:00
Akira Hatanaka
9955cb931b [mips] Fix floating point branch, comparison, and conditional move instructions
to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 19:01:56 +00:00
Akira Hatanaka
da218210f7 [mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186642 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 01:19:52 +00:00
Vladimir Medic
0884836277 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-16 10:07:14 +00:00
Akira Hatanaka
a66aacf6d7 [mips] Add new InstrItinClasses for move from/to coprocessor instructions and
floating point loads and stores.

No changes in functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 00:00:02 +00:00
Vladimir Medic
90b1086b93 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184716 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 10:05:34 +00:00
Akira Hatanaka
ae7e7cb3d3 [mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).
Previously, three instructions were needed:

trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)

Now we need only two:

trunc.w.s $f0, $f2
swc1 $f0, 0($2)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 21:17:15 +00:00
Akira Hatanaka
ec4db6ab5f [mips] Fix instruction selection pattern for sint_to_fp node to avoid emitting an
invalid instruction sequence.

Rather than emitting an int-to-FP move instruction and an int-to-FP conversion
instruction during instruction selection, we emit a pseudo instruction which gets
expanded post-RA. Without this change, register allocation can possibly insert a
floating point register move instruction between the two instructions, which is not
valid according to the ISA manual.

mtc1 $f4, $4         # int-to-fp move instruction.
mov.s $f2, $f4       # move contents of $f4 to $f2.
cvt.s.w $f0, $f2     # int-to-fp conversion.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182042 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 19:48:37 +00:00
Akira Hatanaka
afcca55ff9 [mips] Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182036 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 18:42:42 +00:00
Akira Hatanaka
42f562a169 [mips] Add option -mno-ldc1-sdc1.
This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 18:23:35 +00:00
Akira Hatanaka
175f0fd99a [mips] Define reg+imm load/store pattern templates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 02:01:48 +00:00
Akira Hatanaka
dc2f792740 [mips] Split SelectAddr, which was used to match address patterns, into two
functions. Set AddedComplexity to determine the order in which patterns are
matched.

This simplifies selection of floating point loads/stores.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175300 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 21:20:45 +00:00
Akira Hatanaka
d2047c6001 [mips] Set flag neverHasSideEffects flag on some of the floating point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173401 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 00:20:39 +00:00
Jack Carter
ec3199f675 This patch tackles the problem of parsing Mips
register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12 01:03:14 +00:00
Akira Hatanaka
1e7739f614 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
parameter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:20:09 +00:00
Akira Hatanaka
c567b1cd0d [mips] Delete all floating point instruction classes that are no longer used.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170084 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 02:05:02 +00:00
Akira Hatanaka
b573539c6b [mips] Modify definitions of floating point comparison instructions.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170077 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:34:09 +00:00
Akira Hatanaka
89828a6a56 [mips] Modify definitions of floating point branch instructions.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:32:36 +00:00
Akira Hatanaka
2b1a50cfdb [mips] Modify definitions of floating point indexed load and store instructions.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:30:49 +00:00
Akira Hatanaka
b2c68ddaab [mips] Modify definitions of floating point multiply-add/sub instructions.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170073 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:27:48 +00:00
Akira Hatanaka
6f94eb3512 [mips] Modify definitions of floating point load and store instructions.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:24:00 +00:00
Akira Hatanaka
be9f72d2d8 [mips] Modify definitions of move from/to coprocessor instructions.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:16:49 +00:00
Akira Hatanaka
4b921416b4 [mips] Modify definitions of two register operand floating point instructions.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:14:07 +00:00
Akira Hatanaka
82fdad75f7 [mips] Modify definitions of three register operand floating point instructions
and separate encoding information from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:07:37 +00:00
Akira Hatanaka
10bd726459 [mips] Move classes that do not belong in MipsInstrFormats.td into
MipsInstrFPU.td.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 00:49:23 +00:00
Akira Hatanaka
2f3e06399a [mips] Set isCommutable flag in a more explicit way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 00:46:23 +00:00
Akira Hatanaka
1c88a8d978 [mips] Remove fmt from the parameter list of classes FMADDSUB and FNMADDSUB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 00:38:59 +00:00
Akira Hatanaka
625cb5ac72 [mips] Remove single-precision floating point instruction from multiclass
FFR2P_M.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 00:35:54 +00:00
Akira Hatanaka
6085780a91 [mips] Remove single-precision floating point instructions from multiclasses
FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170053 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 00:29:29 +00:00
Akira Hatanaka
249330eadb [mips] Shorten predicate name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169579 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07 03:06:09 +00:00
Akira Hatanaka
0301bc54ad [mips] Add predicate HasFPIdx for floating-point indexed load instruction
support and use it in place of HasMips32r2Or64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15 21:17:13 +00:00
Akira Hatanaka
3c77033a90 [mips] Set flag neverHasSideEffects flag on floating point conversion
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167348 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-03 00:53:12 +00:00
Akira Hatanaka
5a7dd43f04 Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.

No changes in functionality.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 01:52:08 +00:00
Akira Hatanaka
72e9b6aeb4 Add stub methods for mips assembly matcher.
Patch by Vladimir Medic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 20:16:42 +00:00
Akira Hatanaka
603f69dc2c Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31 19:13:07 +00:00
Akira Hatanaka
36bcc11236 Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
single-precision load and store.

Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31 18:16:49 +00:00
Akira Hatanaka
1418045472 1. introduce MipsPat in place of Pat in order to exclude those from
being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered

Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14 21:03:23 +00:00
Akira Hatanaka
18f3c78092 This patch adds a predicate to existing mips32 and mips64 so that those
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-22 03:10:09 +00:00
Akira Hatanaka
ecdc9d5bb2 Add disassembler to MIPS.
Patch by Vladimir Medic. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 18:03:21 +00:00