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16417 Commits

Author SHA1 Message Date
Jim Grosbach
5c57639c28 For Thumb2, try to use frame pointer references for stack slots even when a 
base register is available. rdar://8525298

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116729 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 18:39:46 +00:00
Rafael Espindola
aa85c21633 Produce ELF::R_386_GOTPC relocations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116728 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 18:36:12 +00:00
Kevin Enderby
7aef62ff8c Added a handful of x86-32 instructions that were missing so that llvm-mc would 
be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 17:04:36 +00:00
Jim Grosbach
0f0127f4a6 ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate 
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116714 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 16:48:59 +00:00
Jim Grosbach
e038a206df Grammar tweak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116712 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 16:38:50 +00:00
Kalle Raiskila
940e7965f1 Improve lowering of sext to i128 on SPU. 
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116701 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 09:34:19 +00:00
Eric Christopher
4cf34c6c04 Remove the check for invalid calling conventions. Testing shows that they're 
working just fine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116698 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 06:49:12 +00:00
Eric Christopher
fa87d66752 Lift arg promotion from the X86 backend. This should be unified at some point. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116694 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 02:17:53 +00:00
Eric Christopher
404be0c04f Now that we handle all allocas via a non-SP reg offset remove all of the 
special case handling for ARM::SP.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116688 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-17 11:08:44 +00:00
Eric Christopher
ec8bf972f5 Allow more load types to be materialized through the allocas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-17 06:07:26 +00:00
Eric Christopher
d56d61af01 Optimize GEP off of intermediate allocas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116681 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-17 01:51:42 +00:00
Eric Christopher
7208dbf2d5 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116680 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-17 01:42:53 +00:00
Eric Christopher
dc0b0ef6cd Turn on AddOperator folding in GEP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116679 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-17 01:41:46 +00:00
Eric Christopher
45c607134b Use the i12 immediate versions of the load instructions - they're handled 
more in the post-passes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116678 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-17 01:40:27 +00:00
Rafael Espindola
f230df9af4 Add a MCObjectFormat class so that code common to all targets that use a 
single object format can be shared.

This also adds support for

mov zed+(bar-foo), %eax

on ELF and COFF targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116675 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-16 18:23:53 +00:00
Michael J. Spencer
84ac4d5a2a X86-Windows: Emit an undefined global __fltused symbol when targeting Windows 
if any floating point arguments are passed to an external function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116665 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-16 08:25:41 +00:00
Eric Christopher
47650ece37 Fix some funky formatting that got through. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-16 01:10:35 +00:00
Bill Wendling
07fda9f9b6 ARMCodeEmitter::emitMiscInstruction is dead. Long live 
ARMCodeEmitter::emitMiscInstruction!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116644 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 23:35:12 +00:00
Eric Christopher
c9a91fdaf9 Make sure offset is 0 for load/store register to the stack call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116640 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 23:07:10 +00:00
Eric Christopher
00ed59a968 Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116635 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 22:49:28 +00:00
Eric Christopher
315030ca74 Fix else if -> if in store machinery. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116628 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 22:32:37 +00:00
Bill Wendling
2695d8edd1 Reformatting. No functionalogicality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116625 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 21:50:45 +00:00
Eric Christopher
a322425642 Refactor ARM fast-isel reg + offset to be a base + offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116622 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 21:32:12 +00:00
Jim Grosbach
5ad01c7728 Encoding information for the various ARM saturating add/sub instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116612 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 19:49:46 +00:00
Jim Grosbach
84760885e1 ARM binary encoding information for RSB and RSC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 18:42:41 +00:00
Jim Grosbach
fd52906478 Don't mark argument value stores as immutable, as otherwise the post-RA 
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116602 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 18:34:47 +00:00
Bob Wilson
01b35c25de Use simple RegState::Define flag instead of getDefRegState(true). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116601 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 18:25:59 +00:00
Eric Christopher
2896df897c Expand GEP handling for constant offsets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 18:02:07 +00:00
Jim Grosbach
6bdc8ae291 When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes 
an explicit def. Make sure to capture that properly. rdar://8556556

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116591 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 17:35:17 +00:00
Jim Grosbach
8abe32af38 ARM mode encoding information for UBFX and SBFX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 17:15:16 +00:00
Bob Wilson
1dd5a2f4e1 Remove unused ARMISD::AND selection DAG node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 04:34:40 +00:00
Bob Wilson
cfbece50f6 ARM instructions that are both predicated and set the condition codes 
have been printed with the "S" modifier after the predicate.  With ARM's
unified syntax, they are supposed to go in the other order.  We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM.  Apparently we don't generate these instructions often because no one
noticed until now.  Thanks to Bill Wendling for the testcase!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 03:23:44 +00:00
Jim Grosbach
197a8df640 Encoding info for extension instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 02:29:58 +00:00
Jim Grosbach
58456c0b04 Add missing Rd encoding for MOVs instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116537 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 23:28:31 +00:00
Jim Grosbach
7032f922b1 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos 
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 22:57:13 +00:00
Jim Grosbach
792e9796b3 Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx' 
pseudonym.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 20:43:44 +00:00
Jim Grosbach
1de588df69 MOVi16 and MOVT ARM mode encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 18:54:27 +00:00
Jim Grosbach
2d294f564b Simplify encoding information and add 'dst' operand info for TAILJMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 17:24:28 +00:00
Oscar Fuentes
7bd698153d Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It 
creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116480 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 15:54:46 +00:00
Eric Christopher
eae8439771 Handle more complex GEP based loads and add a few TODOs to deal with 
GEP + alloca.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116474 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 09:29:41 +00:00
Bill Wendling
bbbdcd453d Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on 
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 02:33:26 +00:00
Bill Wendling
946a2740a5 Add encoding for 'fmstat'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 01:19:34 +00:00
Bill Wendling
88cf038436 - Add encodings for multiply add/subtract instructions in all their glory. 
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 01:02:08 +00:00
Jim Grosbach
bd38acfa6f Regenerate. No functional change, just cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 00:15:18 +00:00
Jim Grosbach
55561d1882 Detabify and clean up 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 23:47:11 +00:00
Jim Grosbach
95369599c6 A few 80 column fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 23:34:31 +00:00
Jim Grosbach
3a37866e53 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116450 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 23:12:26 +00:00
Jim Grosbach
b4b07b93ea Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116449 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:55:33 +00:00
Jim Grosbach
06ef444e5c Add operand encoding bits for SMC and SVC in ARM mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:38:23 +00:00
Jim Grosbach
832859d062 More encoding cleanup. Also add register Rd operands for indirect branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:09:34 +00:00