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16417 Commits

Author SHA1 Message Date
Jim Grosbach
a7dbc1ead7 Simplify some ARM encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:48:54 +00:00
Eric Christopher
a9c575110f Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116438 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:41:51 +00:00
Jim Grosbach
6c354fd3f5 Add a FIXME. The ADR instruction is a bit odd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:32:30 +00:00
Jim Grosbach
b3af5de2d9 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:00:04 +00:00
Bill Wendling
67a704de03 Add MC encodings for VCVT* instrunctions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:58:46 +00:00
Jim Grosbach
596307e133 Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:38:04 +00:00
Jim Grosbach
fa7d2cb680 Make a few more bits of some simple instructions explicit. nop, yield, wfe, 
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:30:55 +00:00
Jim Grosbach
b35ad41fef Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 19:56:10 +00:00
Jim Grosbach
e822f94509 Fix encoding for compares. No Rd register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 18:05:25 +00:00
Jim Grosbach
24989ecc70 Add ARM mode operand encoding information for ADDE/SUBE instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 18:00:52 +00:00
Rafael Espindola
6d8628061b Fix another case where we were preferring instructions with large 
immediates instead of 8 bits ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 17:14:25 +00:00
Rafael Espindola
dba81cf40e Fix PR8365 by adding a more specialized Pat that checks if an 'and' with 
8 bit constants can be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116403 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 13:31:20 +00:00
Eric Christopher
ede42b0a22 Start handling more global variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116401 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 09:11:46 +00:00
Evan Cheng
14ce175216 Limit load / store issues (at least until we have a true multi-issue aware scheduler). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 01:54:21 +00:00
Bill Wendling
6932643a37 Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test 
just yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 01:17:33 +00:00
Bill Wendling
54908dd72b Add encodings for VCVT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:56:35 +00:00
Jim Grosbach
89c898f8af Add ARM encoding information for comparisons, forced-cc-out arithmetics, and 
arithmetic-with-carry-in instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:50:27 +00:00
Bill Wendling
1fc6d8837f Add VCMPZ and VABS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:38:07 +00:00
Bill Wendling
cd77686254 Refactor VCMP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:04:29 +00:00
Jim Grosbach
ef324d7044 Add the rest of the ARM so_reg encoding options (register shifted register) 
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:53:58 +00:00
Bill Wendling
5a1fd8cf68 Add encodings for VNMUL[SD]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:47:37 +00:00
Bill Wendling
caa3d467ab Add encodings for VDIV and VMUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:22:27 +00:00
Evan Cheng
3f490f3469 Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116368 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:19:28 +00:00
Jim Grosbach
2a6a93d542 Move the ARM so_imm encoding into a custom operand encoder and remove the 
explicit handling of the instructions referencing it from the MC code
emitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:18:08 +00:00
Bill Wendling
52061f83e7 Refactor some of the encoding logic into a base class. This keeps us from having 
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116362 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:06:54 +00:00
Jim Grosbach
08bd54987f Add custom encoder for the 's' bit denoting whether an ARM arithmetic 
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:00:24 +00:00
Bill Wendling
dd3bc112e6 Add encoding for VSUB and VCMP. 
Fear not! I'm going to try a refactoring right now. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:55:35 +00:00
Bill Wendling
174777bb2b Encoding for VADDD. Plus a test for the VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:08:41 +00:00
Bill Wendling
a0c14ef8f6 Split out the "size" field from the encoding. The newer documentation has it as 
a separate bit in the coding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:03:19 +00:00
Eric Christopher
558cf007b5 Fix thinko in arm fast isel alloca rewrite. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 21:23:43 +00:00
Jim Grosbach
499e886fe6 Encoding for ARM-mode VADD.F32 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 21:22:40 +00:00
Eric Christopher
52b45056b2 Combine these together - should probably have some text associated 
that says what why what we just asserted is wrong.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116333 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 19:44:17 +00:00
Nick Lewycky
65b65d6ca4 Mark variable 'NoImplicitFloatOps' used only in an assert as used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:18:03 +00:00
Jim Grosbach
f59818b81a Add MOVi ARM encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:09:12 +00:00
Dan Gohman
320afb8c81 Initial va_arg support for x86-64. Patch by David Meyer! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116319 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:00:49 +00:00
Jim Grosbach
8e157302f4 Nuke unused wrapper function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:53:25 +00:00
Jakob Stoklund Olesen
d0eeeeb558 Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions. 
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116314 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:15:00 +00:00
Jim Grosbach
0de6ab3c43 Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:11:26 +00:00
Bob Wilson
77f42b5278 PR8359: The ARM backend may end up allocating registers D16 to D31 when 
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 16:22:47 +00:00
Eric Christopher
1541877941 Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 05:39:06 +00:00
Eric Christopher
5532433a57 Handle a wider arrangement of loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:43:21 +00:00
Evan Cheng
08cec1ef27 More ARM scheduling itinerary fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:41:41 +00:00
Jim Grosbach
42fac8ee3b MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:16:21 +00:00
Jason W Kim
17b443df43 Second set of ARM/MC/ELF changes. 
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116257 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:01:44 +00:00
Evan Cheng
60ff87914f Proper VST scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 22:03:18 +00:00
Eric Christopher
5f9e8b971b Use a sane mechanism for that assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116249 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 22:01:22 +00:00
Eric Christopher
050d16c2a9 We're not going to handle dynamic allocas anywhere else. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116240 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 21:37:35 +00:00
Eric Christopher
fb0b892f7e Make sure that the call stack adjustments have default operands. Also 
leave custom lowerings for later.

Fixes some nightly tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 21:20:02 +00:00
Jakob Stoklund Olesen
4f9af2ef65 PowerPC varargs functions store live-in registers on the stack. Make sure we use 
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.

This fixes PR8357.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116222 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:43:09 +00:00
Eric Christopher
8ff9a9da0a Found a bug turning this on by default. Disable again for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:26:21 +00:00
Eric Christopher
fa6b29dacd Fix help text. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:15:02 +00:00
Eric Christopher
feadddd6b6 Change flag from Enable to Disable since we're enabled by default. 
Also don't use fast-isel on non-darwin since it's untested.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116217 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:05:22 +00:00
Andrew Trick
1a2cf3b4d9 Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116214 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 19:02:04 +00:00
Jim Grosbach
62547267f0 More binary encoding stuff, taking advantage of the new "by name" operand 
matching in tblgen to do the predicate operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 18:51:51 +00:00
Eric Christopher
a2efc5ff6e Turn on arm fast isel by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116212 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 18:48:18 +00:00
Francois Pichet
1265776243 MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 11:36:19 +00:00
Eric Christopher
a1640d9ed9 Copy and pasteo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116198 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:40:05 +00:00
Eric Christopher
dccd2c3c43 Whitespace cleanup in ARM fast isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116197 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:38:55 +00:00
Eric Christopher
6a880d6ba8 Add srem libcall support to ARM fast isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116196 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:37:26 +00:00
Eric Christopher
7bdc4de4e7 Add i8 sdiv support for ARM fast isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116195 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:31:54 +00:00
Eric Christopher
3bbd396853 Implement select handling for ARM fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 08:27:59 +00:00
Chris Lattner
60cb528246 Per discussion with Sanjiv, remove the PIC16 target from mainline. When/if 
it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116190 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 05:44:40 +00:00
Michael J. Spencer
335b806c62 X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116188 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 05:29:15 +00:00
Michael J. Spencer
92bf38c956 X86: MinGW should always use libgcc on Windows. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116177 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-10 23:11:06 +00:00
Michael J. Spencer
1802a9f8fe X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116174 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-10 22:04:34 +00:00
Michael J. Spencer
ec38de2ca8 Fix Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116173 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-10 22:04:20 +00:00
Chris Lattner
749dc72bdc fix the expansion of va_arg instruction on PPC to know the arg 
alignment for PPC32/64, avoiding some masking operations.

llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-10 18:34:00 +00:00
Michael J. Spencer
c0c8df3cea Fix Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116149 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 11:00:50 +00:00
Evan Cheng
10dc63feeb Add VLD4 scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116143 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 04:07:58 +00:00
Evan Cheng
84f69e8436 Finish vld3 and vld4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116140 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:45:34 +00:00
Evan Cheng
40bb6836f6 Complete vld2 instruction itineries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116136 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:26:12 +00:00
Evan Cheng
8ae6ffacdd Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116135 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:15:04 +00:00
Evan Cheng
d2ca813549 Correct some load / store instruction itinerary mistakes: 
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:03:04 +00:00
Bill Wendling
0aa38b9381 Check to make sure that the iterator isn't at the beginning of the basic block 
before decrementing. <rdar://problem/8529919>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116126 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 00:03:48 +00:00
Chris Lattner
0d9a0865c6 add jit support for the new psuedo instructions I added for 
the add/or xform.  The JIT isn't mcized yet, boo.

This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116125 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 23:59:27 +00:00
Chris Lattner
8dae787db4 machine a mutable machineinstr down into emitInstruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116124 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 23:54:01 +00:00
Eric Christopher
e93417bcc8 Fix the store part of this as well. Fixes smg2000. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116123 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 23:52:16 +00:00
Jim Grosbach
56ac907c57 Implement a few more binary encoding bits. Still very early stage proof-of- 
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 21:45:55 +00:00
Cameron Esfahani
ec37b00b17 Recommit 116056, now with the missing file... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116083 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 19:24:18 +00:00
Jim Grosbach
3e09413c2c Reapply 116059, this time without the fatfingered pasto at the top. 
''const'ify getMachineOpValue() and associated helpers.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 17:45:54 +00:00
Jim Grosbach
2cee75a254 Reverting 116059. Bots are unhappy with it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 17:28:40 +00:00
Andrew Trick
5900201aa7 reverting 116056: win64_params.ll may need to be conditionalized? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116063 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 17:22:42 +00:00
Jim Grosbach
461caba214 'const'ify getMachineOpValue() and associated helpers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116059 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 16:52:44 +00:00
Cameron Esfahani
d7b8d91d4a Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116056 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 10:31:30 +00:00
Bob Wilson
7d24705f65 Change register allocation order for ARM VFP and NEON registers to put the 
callee-saved registers at the end of the lists.  Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases.  Thanks to
Jakob for helping me realize the problem.

Most of this patch is fixing the testsuite.  There are quite a few places
where we're checking for specific registers.  I changed those to wildcards
in places where that doesn't weaken the tests.  The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 06:15:13 +00:00
Chris Lattner
d043529b34 fix a subtle bug I introduced in my refactoring, where we stopped preferring 
the i8 versions of instructions in some cases.  In test6, we started 
generating:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
                                        ## <MCInst #478 CMP64mi32
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

instead of:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
                                        ## <MCInst #479 CMP64mi8
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

Fix this and add some comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116053 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 05:12:14 +00:00
Chris Lattner
15df55d8c2 reapply: Use the new TB_NOT_REVERSABLE flag instead of special 
reapply: reimplement the second half of the or/add optimization.  We should now

with no changes.  Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116040 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 03:57:25 +00:00
Chris Lattner
99ae6659da reapply the patch reverted in r116033: 
"Reimplement (part of) the or -> add optimization.  Matching 'or' into 'add'"

With a critical fix: the add pseudos clobber EFLAGS.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 03:54:52 +00:00
Daniel Dunbar
b88b00ba2b Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into 
'add'", which seems to have broken just about everything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116033 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 02:07:32 +00:00
Daniel Dunbar
b38109fc2d Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends 
on r116007, which I am about to revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116032 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 02:07:29 +00:00
Daniel Dunbar
32f0cdba30 Revert "reimplement the second half of the or/add optimization. We should now", 
which depends on r116007, which I am about to revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 02:07:26 +00:00
Eric Christopher
7a56f33583 Move to thumb2 loads, fixes a problem with incoming registers 
as thumb1.

Fixes lencod.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116027 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 01:13:17 +00:00
Chris Lattner
cd3167b281 reimplement the second half of the or/add optimization. We should now 
only end up emitting LEA instead of OR.  If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.

Add some testcases that we emit "or" in cases where we used to produce
an "add".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 01:05:10 +00:00
Jim Grosbach
58f38bfa24 Enable binary encoding of some simple instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116022 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 00:39:21 +00:00
Jim Grosbach
bade37bb8b Make <target>CodeEmitter::getBinaryCodeForInstr() a const method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 00:21:28 +00:00
Chris Lattner
05e27c5786 Use the new TB_NOT_REVERSABLE flag instead of special 
casing FsMOVAPDrr/FsMOVAPSrr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116016 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 00:03:02 +00:00
Chris Lattner
a228376185 simplify some map operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116014 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 23:57:02 +00:00
Chris Lattner
122e2ea043 Reimplement (part of) the or -> add optimization. Matching 'or' into 'add' 
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies.  However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).

While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA.  This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.

This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20

the add r/i cases are coming next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116007 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 23:36:18 +00:00
Evan Cheng
344d9db970 Code refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116002 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 23:12:15 +00:00
Chris Lattner
45a1cb26a3 Reduce casting in various tables by defining the table 
with the right types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116001 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 23:08:41 +00:00