Commit Graph

22154 Commits

Author SHA1 Message Date
Rafael Espindola
a21a8a863d Make the ARM ABI selectable via SubtargetFeature.
This patch makes it possible to select the ABI with -mattr. It will be used to
forward clang's -target-abi option to llvm's CodeGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198304 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 13:40:08 +00:00
Arnold Schwaighofer
1bdb320dae BasicAA: Fix value equality and phi cycles
When there are cycles in the value graph we have to be careful interpreting
"Value*" identity as "value" equivalence. We interpret the value of a phi node
as the value of its operands.
When we check for value equivalence now we make sure that the "Value*" dominates
all cycles (phis).

%0 = phi [%noaliasval, %addr2]
%l = load %ptr
%addr1 = gep @a, 0, %l
%addr2 = gep @a, 0, (%l + 1)
store %ptr ...

Before this patch we would return NoAlias for (%0, %addr1) which is wrong
because the value of the load is from different iterations of the loop.

Tested on x86_64 -mavx at O3 and O3 -flto with no performance or compile time
regressions.

PR18068
radar://15653794

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198290 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 03:31:36 +00:00
Venkatraman Govindaraju
447c3480e5 [Sparc] Handle atomic loads/stores in sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198286 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 22:11:54 +00:00
Venkatraman Govindaraju
924ac6dc0c [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198281 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 20:22:45 +00:00
Venkatraman Govindaraju
ca0ef6fe4f [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198280 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 19:00:10 +00:00
Craig Topper
95a3ccdd80 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 15:29:32 +00:00
Elena Demikhovsky
3062a311ac AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp
Printing rounding control.
Enncoding for EVEX_RC (rounding control).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 15:12:34 +00:00
Craig Topper
8dff260267 Add two fp test cases I missed in my previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 23:15:19 +00:00
Craig Topper
45e6393241 Add more X86 FP stack disassembler test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 22:51:53 +00:00
Nick Lewycky
99cebadb5c Fold vector selects with undef elements in the condition. Fixes PR18319.
Patch by Ilia Filippov!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 19:30:47 +00:00
Craig Topper
5cbbd7e1a5 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 17:21:44 +00:00
Saleem Abdulrasool
4ba4132d62 ARM IAS: account for predicated pre-UAL mnemonics
Checking the trailing letter of the mnemonic is insufficient.  Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 18:38:01 +00:00
Eric Christopher
5be77762a3 Revert r198208 and reapply:
r198196: Use a pointer to keep track of the skeleton unit for each normal unit and construct it up front.
      r198199: Reapply r198196 with a fix to zero initialize the skeleton pointer.
      r198202: Fix aranges and split dwarf by ensuring that the symbol and relocation back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo.

with a fix to use integer 0 for DW_AT_low_pc since the relocation to the text section symbol was causing issues with COFF. Accordingly remove addLocalLabelAddress and machinery since we're not currently using it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 17:22:27 +00:00
NAKAMURA Takumi
b2299f0c80 Revert r198199 (and r198202). It broke 3 DebugInfo tests for targeting i686-cygming.
r198196: Use a pointer to keep track of the skeleton unit for each normal unit and construct it up front.
  r198199: Reapply r198196 with a fix to zero initialize the skeleton pointer.
  r198202: Fix aranges and split dwarf by ensuring that the symbol and relocation back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo.

They could be reproducible with explicit target.

  llvm/lib/MC/WinCOFFObjectWriter.cpp:224: bool {anonymous}::COFFSymbol::should_keep() const: Assertion `Section->Number != -1 && "Sections with relocations must be real!"' failed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198208 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 09:26:10 +00:00
Eric Christopher
782b70f4b3 Fix aranges and split dwarf by ensuring that the symbol and relocation
back to the compile unit from the aranges section is to the skeleton
unit and not the one in the dwo.

Do this by adding a method to grab a forwarded on local sym and local
section by querying the skeleton if one exists and using that. Add
a few tests to verify the relocations are back to the correct section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198202 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 05:25:49 +00:00
Eric Christopher
bba2331876 Reapply r198196 with a fix to zero initialize the skeleton pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 03:40:32 +00:00
Eric Christopher
0661cbefb3 Temporarily revert "Use a pointer to keep track of the skeleton unit for
each normal unit" as it seems to be causing problems in the asan tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198197 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 03:12:31 +00:00
Eric Christopher
1dd211d88d Use a pointer to keep track of the skeleton unit for each normal unit
and construct it up front. Add address ranges at the end and a helper
routine so that we're not needlessly using an indirction in the case
of split dwarf.

Update testcases according to the new ordering of attributes on
the compile unit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198196 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 03:02:12 +00:00
Jiangning Liu
90128bee68 For AArch64 Neon, simplify scalar dup by lane0 for fp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198194 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 02:44:35 +00:00
Hao Liu
afcdbf7400 [AArch64]Add code to spill/fill Q register tuples such as QPair/QTriple/QQuad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198193 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 02:38:12 +00:00
Hao Liu
43ffcc571c [AArch64]Can't select shift left 0 of type v1i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198192 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 02:12:46 +00:00
Kevin Qin
3f8f3c9feb Fix a bug in DAGcombiner about zero-extend after setcc.
For AArch64 backend, if DAGCombiner see "sext(setcc)", it will
combine them together to a single setcc with extended value type.
Then if it see "zext(setcc)", it assumes setcc is Vxi1, and try to
create "(and (vsetcc), (1, 1, ...)". While setcc isn't Vxi1,
DAGcombiner will create wrong node and get wrong code emitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 02:05:13 +00:00
Hao Liu
3796015b5b [AArch64]Fix the problem that can't select mul of v1i64/v2i64 types.
E.g. Can't select such IR:
     %tmp = mul <2 x i64> %a, %b


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198188 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 01:38:41 +00:00
Bill Wendling
14eb675218 Un-XFAILify some tests which are now passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198184 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-29 23:09:14 +00:00
Saleem Abdulrasool
dd2836776f ARM: provide VFP aliases for pre-V6 mnemonics
In order to provide compatibility with the GNU assembler, provide aliases for
pre-UAL mnemonics for floating point operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198172 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-29 17:58:35 +00:00
Venkatraman Govindaraju
a71d72a059 [SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.
This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198157 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-29 07:15:09 +00:00
Venkatraman Govindaraju
0c67825459 [SparcV9] For codegen generated library calls that return float, set inreg flag manually in LowerCall().
This makes the sparc backend to generate Sparc64 ABI compliant code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198149 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-29 04:27:21 +00:00
Venkatraman Govindaraju
5b9918957a [SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.
Also, pass fp128 arguments to varargs through integer registers if necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-29 01:20:36 +00:00
Andrew Trick
6c9712fecb New machine model for cortex-a9. Schedule for resources and latency.
Schedule more conservatively to account for stalls on floating point
resources and latency. Use the AGU resource to model latency stalls
since it's shared between FP and LD/ST instructions. This might not be
completely accurate but should work well in practice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-28 21:57:05 +00:00
NAKAMURA Takumi
d8e67feaf2 llvm/test/CodeGen/X86/vselect.ll: Unbreak Windows x64 targets to add -mtriple=x86_64-unknown-unknown.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198114 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-28 13:04:29 +00:00
Andrea Di Biagio
6ec3395335 [X86] Teach the backend how to fold target specific dag node for packed
vector shift by immedate count (VSHLI/VSRLI/VSRAI) into a build_vector when
the vector in input to the shift is a build_vector of all constants or UNDEFs.

Target specific nodes for packed shifts by immediate count are in
general introduced by function 'getTargetVShiftByConstNode' (in
X86ISelLowering.cpp) when lowering shift operations, SSE/AVX immediate
shift intrinsics and (only in very few cases) SIGN_EXTEND_INREG dag
nodes.

This patch adds extra rules for simplifying vector shifts inside
function 'getTargetVShiftByConstNode'.

Added file test/CodeGen/X86/vec_shift5.ll to verify that packed
shifts by immediate are correctly folded into a build_vector when the
input vector to the shift dag node is a vector of constants or undefs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198113 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-28 11:11:52 +00:00
Saleem Abdulrasool
14b42a1c92 AsmParser: cleanup diagnostics for .rep/.rept
Avoid double diagnostics for invalid expressions for count.  Improve caret
location for negative count.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198099 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-28 06:39:29 +00:00
Saleem Abdulrasool
b5191e98e8 IAS: support .rep as an alias for .rept
The GNU assembler supports .rep as an alias for .rept.  This simply creates the
alias for it and introduces a test for both .rept and .rep.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198097 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-28 05:54:33 +00:00
Chandler Carruth
92ffb676af Disable transforms that introduce calls to exp10*() on Linux due to
widespread glibc bugs.

The glibc implementation of exp10 has a very serious precision bug in
version 2.15 (and older versions). This is still very widely used (the
current Ubuntu LTS for example uses it) and so it isn't reasonable to
make transforms that produce these functions. This fixes many
miscompiles introduced when we started transforming pow(10.0, ...) into
exp10, and it may have fixed other latent miscompiles where exp10
provided sufficient precision but exp10f did not.

This is all really horrible. The primary bug has been fixed for over
a year and glibc 2.18 works correctly for the test cases I have, but it
will be 2017 before the LTS using 2.15 is no longer supported by Ubuntu
(and thus reasonable for folks to be relying on). =[ We're either going
to need to live without these optimizations, or find a way to switch
behavior more dynamically than using simply the fact that the OS is
"Linux".

To make matters worse, there appears to be significant testing and
fixing of numerous other bugs in the exp10 family of functions right now
in glibc. While those haven't been causing problems I've seen in the
wild, it gives me concerns that we may need to wait until an even later
release of glibc before we can reliably transform code into exp10.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198093 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-28 02:40:19 +00:00
Andrea Di Biagio
b2f47c6a34 Teach DAGCombiner how to fold a SIGN_EXTEND_INREG of a BUILD_VECTOR of
ConstantSDNodes (or UNDEFs) into a simple BUILD_VECTOR.

For example, given the following sequence of dag nodes:

  i32 C = Constant<1>
  v4i32 V = BUILD_VECTOR C, C, C, C
  v4i32 Result = SIGN_EXTEND_INREG V, ValueType:v4i1

The SIGN_EXTEND_INREG node can be folded into a build_vector since
the vector in input is a BUILD_VECTOR of constants.

The optimized sequence is:

  i32 C = Constant<-1>
  v4i32 Result = BUILD_VECTOR C, C, C, C



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-27 20:20:28 +00:00
Joerg Sonnenberger
c01b59658f Recognize armv7a and friends as aliases for armv7-a etc. for the purpose
of architecture naming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-26 11:50:28 +00:00
Saleem Abdulrasool
6841860532 ARM IAS: support .even directive
The .even directive aligns content to an evan-numbered address.  This is an ARM
specific directive applicable to any section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198031 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-26 01:52:28 +00:00
Venkatraman Govindaraju
76a1dca38d [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198030 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-26 01:49:59 +00:00
Alexander Potapenko
ca523f4f3d [ASan] Fix the tests broken by r198018 to check for private linkage of ASan-generated globals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 17:06:04 +00:00
Simon Atanasyan
f84792ad48 [Mips] Does not take in account 'use-soft-float' attribute's value when
consider to generate stubs for mips16 hard-float mode.

The patch reviewed by Reed Kotler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198019 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 17:00:27 +00:00
Elena Demikhovsky
09a63715ce AVX-512: decoder for AVX-512, made by Alexey Bader.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198013 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 11:40:51 +00:00
Zoran Jovanovic
7dc193619e Support for microMIPS load effective address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 10:14:07 +00:00
Zoran Jovanovic
ae3597c141 Support for microMIPS FPU instructions 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 10:09:27 +00:00
Hao Liu
0f6ebf1aa3 [AArch64]Fix a problem that the register order of fmls/fmla by element is incorrect.
E.g. the codegen result is 
     fmls v1.2s, v0.2s, v2.s[3]
which is expected to be
     fmls v0.2s, v1.2s, v2.s[3]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198001 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 07:12:34 +00:00
Jiangning Liu
eeabc572b9 Add missing pattern matches to support ACLE intrinsics of AArch64 NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197993 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 01:22:51 +00:00
Alexey Samsonov
42c9ecb7a4 llvm-symbolizer: add --obj flag to specify a single object file that should be symbolized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197988 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-24 19:33:22 +00:00
Richard Sandiford
4c925c60eb [SystemZ] Use interlocked-access 1 instructions for CodeGen
...namely LOAD AND ADD, LOAD AND AND, LOAD AND OR and LOAD AND EXCLUSIVE OR.
LOAD AND ADD LOGICAL isn't really separately useful for LLVM.

I'll look at adding reusing the CC results in new year.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-24 15:18:04 +00:00
Richard Sandiford
f7e24324ba [SystemZ] Add MC support for interlocked-access 1 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-24 15:14:05 +00:00
Elena Demikhovsky
097935cc40 AVX-512: fixed some patterns for MVT::i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197981 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-24 14:24:07 +00:00
Hao Liu
dfe4fd9ceb [AArch64]Add patterns to match normal shift nodes: shl, sra and srl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197969 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-24 09:00:21 +00:00