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ae4be981b1
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Author SHA1 Message Date
Chris Lattner
ae4be981b1 Add some pattern fragments to simplify the repetitive parts of the patterns 
for some common ops and use them for a few examples.  Andrew, if you like
this, feel free to convert the rest over, if you hate it, feel free to
revert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23837 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 04:21:06 +00:00
Chris Lattner
d7cc4c407d simplify this a bit by using immediates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23836 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 03:57:03 +00:00
Nate Begeman
6957523b9d Move the target constant divide optimization up into the dag combiner, so 
that the nodes can be folded with other nodes, and we can not duplicate
code in every backend.  Alpha will probably want this too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23835 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 02:15:44 +00:00
Andrew Lenharth
d97591a961 forgot this one 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23833 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 00:29:02 +00:00
Andrew Lenharth
4907d22a90 ret 0; works, not much else 
still lots of uglyness.
Maybe calls will come soon.
Fixing the return value of things will be necessary to make alpha work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23832 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 00:28:31 +00:00
John Criswell
9811ea4567 This fixes PR638: 
Regression/CodeGen/Generic/2004-02-08-UnwindSupport.llx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23831 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 20:07:15 +00:00
Jim Laskey
538421411a Added InstrSchedClass to each of the PowerPC Instructions. 
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 19:51:16 +00:00
Nate Begeman
2d5aff761d Write patterns for the various shl and srl patterns that don't involve 
doing something clever.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23824 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 18:42:01 +00:00
Jim Laskey
0de8796e68 Push processor descriptions to the top of target and add command line info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23820 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 13:34:52 +00:00
Chris Lattner
f6cd147471 now that tblgen is smarter, use integers directly. This should help Andrew too 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23818 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 04:32:04 +00:00
Chris Lattner
14c09b81ea teach ppc backend these are copies 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23813 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 01:50:36 +00:00
Chris Lattner
8be1fa5dc5 Convert these cases to patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23811 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 01:38:02 +00:00
Nate Begeman
8d94832394 Woo, it kinda works. We now generate this atrociously bad, but correct, 
code for long long foo(long long a, long long b) { return a + b; }

_foo:
        or r2, r3, r3
        or r3, r4, r4
        or r4, r5, r5
        or r5, r6, r6
        rldicr r2, r2, 32, 31
        rldicl r3, r3, 0, 32
        rldicr r4, r4, 32, 31
        rldicl r5, r5, 0, 32
        or r2, r3, r2
        or r3, r5, r4
        add r4, r3, r2
        rldicl r2, r4, 32, 32
        or r4, r4, r4
        or r3, r2, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23809 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 01:12:32 +00:00
Chris Lattner
e5468305a0 apply some tblgen majik to simplify the X register definitions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23805 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 00:17:55 +00:00
Nate Begeman
da32c9eed6 Make a new reg class for 64 bit regs that aliases the 32 bit regs. This 
will have to tide us over until we get real subreg support, but it prevents
the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor.

Add some initial support for TRUNCATE and ANY_EXTEND, but they don't
currently work due to issues with ScheduleDAG.  Something wll have to be
figured out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23803 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 00:05:37 +00:00
Nate Begeman
4a95945fa5 Add the ability to lower return instructions to TargetLowering. This 
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23802 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-18 23:23:37 +00:00
Jim Laskey
21f587ca24 Simple edits; remove unimplimented cases and clarify long haul SLU cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23788 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-18 16:59:23 +00:00
Chris Lattner
841d12d9ac Fix the JIT encoding of LWA, LD, STD, and STDU. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23787 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-18 16:51:22 +00:00
Jim Laskey
076866c50f Checking in first round of scheduling tablegen files. Not tied in as yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23786 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-18 16:23:40 +00:00
Chris Lattner
3d8df55fed add a case 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23785 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-18 06:30:51 +00:00
Nate Begeman
9d2b817fcb Do the right thing and enable 64 bit regs under the control of a subtarget 
option.  Currently the only way to enable this is to specify the
64bitregs mattr flag.  It is never enabled by default on any config yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23779 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-18 00:56:42 +00:00
Nate Begeman
1d9d7427c4 First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is 
purely mechanical.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-18 00:28:58 +00:00
Nate Begeman
21e463b2bf More PPC32 -> PPC changes, as well as merging some classes that were 
redundant after the change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-16 05:39:50 +00:00
Nate Begeman
34f342e36f Remove some dead code now that the dag combiner exists. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23754 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-15 22:08:02 +00:00
Chris Lattner
4cb5a1b896 Remove some dead code: the ORI/ORIS cases are autogen'd. This makes 
SelectIntImmediateExpr dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23753 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-15 22:06:18 +00:00
Chris Lattner
de123822e5 prune #includes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23752 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-15 21:58:54 +00:00
Chris Lattner
75c9f67370 These instructions are now autogenerated 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23751 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-15 21:44:56 +00:00
Chris Lattner
e0b2e6372f Add a pattern for FSQRTS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23750 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-15 21:44:15 +00:00
Chris Lattner
651dea74f6 remove dead code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23749 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-15 21:40:12 +00:00
Chris Lattner
d242419e17 remove broken SRA/rlwimi case 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23746 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-15 19:04:48 +00:00
Chris Lattner
16e71f2f70 Rename PPC32*.h to PPC*.h 
This completes the grand PPC file renaming


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:59:06 +00:00
Chris Lattner
b9459b731a Merge PPCJITInfo.h and PPC32JITInfo.h. Note that the PowerPCJITInfo 
and PPC32JITInfo classes should be merged.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23744 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:53:41 +00:00
Chris Lattner
2668959b88 Rename PowerPC*.h to PPC*.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:51:18 +00:00
Chris Lattner
26bd0d48a1 Rename PowerPCInstrBuilder.h -> PPC* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23742 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:45:43 +00:00
Chris Lattner
ec4b73cb09 Nuke the PowerPCTargetMachine.h header. Note that the PowerPCTargetMachine 
still should be merged into the PPC32TargetMachine class


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23741 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:44:05 +00:00
Chris Lattner
f379997adc Rename PowerPC*.td -> PPC*.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23740 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:40:39 +00:00
Chris Lattner
f1ed100bc4 These are dead 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23739 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:38:51 +00:00
Chris Lattner
4c7b43b43f Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 23:37:35 +00:00
Chris Lattner
e87bc1f3a8 Like the comment says... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23737 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 22:48:24 +00:00
Chris Lattner
617742b1b8 Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitions 
from the .td file that correspond to it


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23736 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 22:44:13 +00:00
Nate Begeman
14e2cf62f4 Properly split f32 and f64 into separate register classes for scalar sse fp 
fixing a bunch of nasty hackery


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23735 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 22:06:00 +00:00
Nate Begeman
e0de44adba Remove an unnecsesary file. PPC32 and PPC64 share architected registers. 
We will decide with subtarget support whether we ever use an i64 register
class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23734 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 18:58:46 +00:00
Chris Lattner
444215dddc add the integer truncate/extension operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23733 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 06:40:20 +00:00
Chris Lattner
3f31d4304c These are now autogenerated 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23731 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 06:26:29 +00:00
Chris Lattner
7cb6491a0d Add patterns for FP round/extend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23727 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 04:55:50 +00:00
Chris Lattner
13664a6194 add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23726 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 04:55:10 +00:00
Chris Lattner
7b1fe15de0 These definitions have been moved to common code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23681 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-10 06:01:00 +00:00
Chris Lattner
17f2cf05b3 Pull DAG ISel generation nodes out of the PowerPC backend to where they 
can be used by other targets.  For those targets that want to use it,
have at.  :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23680 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-10 06:00:30 +00:00
Andrew Lenharth
fa08fb2c78 This seems useful from the original patch that added the function. If there is a reason it is not useful on a RISC type target, let me know and I will pull it out 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23676 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-09 20:11:35 +00:00
Chris Lattner
65a419a104 Disable formation of rlwinm instructions from SRA bases. This fixes 
the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23670 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-09 05:36:17 +00:00