Evan Cheng
35b35c5c32
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 05:52:20 +00:00
Evan Cheng
0ff94f7fcc
Initial JIT support for ARM by Raul Fernandes Herbster.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-07 01:37:15 +00:00
Dan Gohman
61e729e2e9
More explicit keywords.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 21:21:54 +00:00
Evan Cheng
7fc77611ef
Indexed loads each has 2 outputs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40658 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-01 00:12:08 +00:00
Dan Gohman
f452207d20
More explicit keywords.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40589 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-30 14:51:59 +00:00
Duncan Sands
36397f5034
Support for trampolines, except for X86 codegen which is
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still under discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-27 12:58:54 +00:00
Dan Gohman
b8275a3f6f
Don't ignore the return value of AsmPrinter::doInitialization and
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AsmPrinter::doFinalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40487 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-25 19:33:14 +00:00
Evan Cheng
ffbaccae02
No more noResults.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-21 00:34:19 +00:00
Evan Cheng
8bd6035750
Added -print-emitted-asm to print out JIT generated asm to cerr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40123 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-20 21:56:13 +00:00
Evan Cheng
64d80e3387
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
Evan Cheng
4558b807a2
Only adjust esp around calls in presence of alloca.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40030 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 00:42:58 +00:00
Chris Lattner
c3dbe70ce7
no email addrs in file headers
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39962 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-17 05:56:43 +00:00
Anton Korobeynikov
2365f51ed0
Long live the exception handling!
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This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-14 14:06:15 +00:00
Dale Johannesen
66a2a8f878
ARM: make branch folder remove unconditional branches
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following jump tables that it earlier inserted. This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39782 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-12 16:45:35 +00:00
Dale Johannesen
5d9c4b6020
Fix hang compiling TimberWolf (allow for islands
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of size other than 4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39743 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-11 18:32:38 +00:00
Evan Cheng
8202010364
Didn't mean the last commit. Revert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38515 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 22:00:16 +00:00
Evan Cheng
c608ff22e7
Update.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38513 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 21:49:47 +00:00
Evan Cheng
13ab020ea0
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 18:08:01 +00:00
Chris Lattner
87bdba6d6a
The various "getModuleMatchQuality" implementations should return
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zero if they see a target triple they don't understand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38463 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-09 17:25:29 +00:00
Evan Cheng
9ad6f03166
No need for ccop anymore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 23:34:09 +00:00
Evan Cheng
4b9cb7d135
Incorrect check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37962 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 23:23:19 +00:00
Evan Cheng
06aae67b83
Do away with ImmutablePredicateOperand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37961 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 23:22:46 +00:00
Evan Cheng
dfb2ebac29
Print the s bit if the instruction is toggled to its CPSR setting form.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37932 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 01:01:34 +00:00
Evan Cheng
04c813d00c
PredicateDefOperand -> OptionalDefOperand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37931 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 01:00:49 +00:00
Evan Cheng
148b6a419f
Initial ARM JIT support by Raul Fernandes Herbster.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37926 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 21:15:40 +00:00
Evan Cheng
d54874a06d
Unbreak the build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37914 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 17:13:19 +00:00
Gabor Greif
a99be51bf5
Here is the bulk of the sanitizing.
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Almost all occurrences of "bytecode" in the sources have been eliminated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 17:07:56 +00:00
Evan Cheng
0e1d37904a
Reflects the chanegs made to PredicateOperand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37898 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:18:20 +00:00
Evan Cheng
16b6598325
Added ARM::CPSR to represent ARM CPSR status register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37897 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:17:13 +00:00
Evan Cheng
ee568cf794
Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37896 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:15:27 +00:00
Evan Cheng
c85e832eb7
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37895 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:13:32 +00:00
Evan Cheng
3b5b8368f3
Added ARM::CPSR to represent ARM CPSR status register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37894 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:11:03 +00:00
John Criswell
e644ef7b09
Convert .cvsignore files
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37801 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-29 16:35:07 +00:00
Evan Cheng
e2446c6076
Silence a warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37737 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-26 18:31:22 +00:00
Dan Gohman
d45eddd214
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-26 00:48:07 +00:00
Owen Anderson
0819a9d386
Fix the build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37705 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 16:59:54 +00:00
Dan Gohman
ea859be53c
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 14:59:07 +00:00
Dale Johannesen
5411835165
Quote complex names for Darwin X86 and ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37700 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 00:54:56 +00:00
Evan Cheng
97e604e7d8
Be more conservative of duplicating blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37669 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 23:55:02 +00:00
Evan Cheng
277f0741c5
Allow predicated immediate ARM to ARM calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37659 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 21:05:09 +00:00
Dan Gohman
82a87a0172
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 01:48:05 +00:00
Evan Cheng
eaa91b0a1f
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 01:26:51 +00:00
Evan Cheng
d42e56e166
Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37606 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-15 21:15:00 +00:00
Dale Johannesen
13e8b51e3e
Handle blocks with 2 unconditional branches in AnalyzeBranch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-13 17:59:52 +00:00
Evan Cheng
bfd2ec4a8e
Add a utility routine to check for unpredicated terminator instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-08 21:59:56 +00:00
Lauro Ramos Venancio
61718a6285
Define AsmTransCBE for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37527 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-08 21:06:23 +00:00
Evan Cheng
1fc7cb695c
Fix ARM condition code subsumission check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-08 09:14:47 +00:00
Evan Cheng
f81dea45b5
tBcc is not a barrier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37516 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-08 09:13:23 +00:00
Evan Cheng
9328c1ac66
Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37484 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-07 01:37:54 +00:00
Evan Cheng
2c614c5c69
Mark these instructions clobbersPred. They modify the condition code register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-06 10:17:05 +00:00
Evan Cheng
5e148a37d3
Print predicate of the second instruction of the two-piece constant MI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37437 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-05 18:55:18 +00:00
Evan Cheng
341dcccb4e
PIC label asm printing cosmetic changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37434 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-05 07:36:38 +00:00
Chris Lattner
c621ae7bba
update this entry, now that Anton implemented shift/and lowering for
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switches. There is one really easy isel thing here with tst we are not
getting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37400 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-02 18:45:14 +00:00
Evan Cheng
c354334ac4
Opcode modifier s comes after condition code. e.g. addlts, not addslt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37388 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-01 20:51:29 +00:00
Evan Cheng
144fd1ff0f
Set ARM ifcvt duplication limit to 3 for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37385 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-01 08:28:59 +00:00
Evan Cheng
df4da14948
Make jumptable non-predicable for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37381 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-01 00:56:15 +00:00
Chris Lattner
3a4205367d
Fix the asmprinter so that a globalvalue can specify an explicit alignment
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smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed. This fixes some objc protocol
failures Devang tracked down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37373 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-31 18:57:45 +00:00
Evan Cheng
c6f2f6fbb9
For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37351 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-29 23:34:19 +00:00
Evan Cheng
fd488edb1d
For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37349 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-29 23:32:06 +00:00
Evan Cheng
62ccdbf0b3
Add missing const qualifiers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37342 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-29 18:42:18 +00:00
Evan Cheng
69d555611a
Hooks for predication support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37308 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-23 07:22:05 +00:00
Evan Cheng
94679e66bb
Fix some -march=thumb regressions. tBR_JTr is not predicable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37272 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-21 23:17:32 +00:00
Dale Johannesen
f23b8cf239
Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37271 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-21 22:42:04 +00:00
Dale Johannesen
86d4069666
Add some patterns for PIC PC-relative loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37269 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-21 22:14:33 +00:00
Evan Cheng
5a18ebc70c
BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37268 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-21 18:56:31 +00:00
Evan Cheng
dcc50a4aee
Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37199 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18 01:53:54 +00:00
Evan Cheng
e5e7ce458a
Silence some compilation warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37197 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18 01:19:57 +00:00
Evan Cheng
9f8cbd147c
Set ARM if-conversion block size threshold to 10 instructions for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37194 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18 00:19:34 +00:00
Evan Cheng
6ae3626a4f
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37193 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18 00:18:17 +00:00
Dale Johannesen
8dd86c14d4
More effective breakdown of memcpy into repeated load/store. These are now
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in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm. Ideally you would get cooperation
from the RA as well but this is not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37179 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-17 21:31:21 +00:00
Evan Cheng
3f8602cf20
ARM::tB is also predicable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37125 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 21:53:43 +00:00
Evan Cheng
02c602b333
PredicateInstruction returns true if the operation was successful.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 21:53:07 +00:00
Evan Cheng
75604f81b7
Move if-conversion after all passes that may use register scavenger.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37120 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 20:52:46 +00:00
Evan Cheng
b5f8eff566
Removed isPredicable().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37119 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 20:50:23 +00:00
Evan Cheng
5ada199246
Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37118 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 20:50:01 +00:00
Evan Cheng
aeafca0a25
Conditional branch is not a barrier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37103 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 07:45:54 +00:00
Evan Cheng
2706f9771d
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37098 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 05:14:06 +00:00
Evan Cheng
9307292ae2
Hooks for predication support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37093 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 02:01:49 +00:00
Evan Cheng
44bec52b1b
Add PredicateOperand to all ARM instructions that have the condition field.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-15 01:29:07 +00:00
Lauro Ramos Venancio
5d3d44a848
Fix previous patch. GOTOFF can be used only when the symbol has internal
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linkage or hidden visibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37055 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-14 23:20:21 +00:00
Lauro Ramos Venancio
930d161ba2
Optimize PIC implementation. GOTOFF can be used when the symbol is defined
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and used in the same module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37044 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-14 18:46:23 +00:00
Lauro Ramos Venancio
69642f11ed
Enable aliases on arm-linux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37042 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-14 18:32:56 +00:00
Evan Cheng
42d712b306
Switch BCC, MOVCCr, etc. to PredicateOperand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-08 21:08:43 +00:00
Lauro Ramos Venancio
356e72c4f1
Fix PR1390 in a better way.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36916 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-07 23:15:16 +00:00
Evan Cheng
c4e600362e
This is no longer needed after enabling the DAG combiner xform.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36909 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-07 21:29:41 +00:00
Lauro Ramos Venancio
8f57667a5d
Fix PR1390.
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Don't spill extra register to align the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36814 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-05 23:44:41 +00:00
Lauro Ramos Venancio
a8e9562906
Add a processor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36765 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-04 22:16:30 +00:00
Evan Cheng
97c9bb5cc6
On Mac OS X, GV requires an extra load only when relocation-model is non-static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36718 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-04 00:26:58 +00:00
Evan Cheng
bdc9869dbf
Should never see an indexed load / store with zero offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36714 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 23:30:36 +00:00
Dale Johannesen
4ac075c859
Evan's patch to avoid FPreg->intreg copy for cvt; store to mem
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36693 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 20:54:42 +00:00
Lauro Ramos Venancio
e8e5495474
Debug support for arm-linux.
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Patch by Raul Herbster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36690 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 20:28:35 +00:00
Chris Lattner
388488d604
add support for printing offset from global
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36669 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 16:42:23 +00:00
Evan Cheng
0b0a9a90a4
Typo. It's checking if V is multiple of 4, not multiple of 3. :-)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36663 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 02:00:18 +00:00
Devang Patel
1997473cf7
Drop 'const'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36662 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 01:11:54 +00:00
Chris Lattner
72939126d4
match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36660 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 00:32:00 +00:00
Devang Patel
3e15bf33e0
Use 'static const char' instead of 'static const int'.
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Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-02 21:39:20 +00:00
Dale Johannesen
67cf561b7f
Add some support for (Darwin) code-generating directives in getInlineAsmLength.
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Support is incomplete, but more accurate than gcc's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36634 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-02 01:02:40 +00:00
Devang Patel
794fd75c67
Do not use typeinfo to identify pass in pass manager.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01 21:15:47 +00:00
Evan Cheng
1b20168433
Doh. PC displacement is between the constantpool and the add instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36630 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01 20:27:19 +00:00
Evan Cheng
97de913821
eliminateFrameIndex() change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01 09:13:03 +00:00