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3319 Commits

Author SHA1 Message Date
Jim Grosbach
b4b07b93ea Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116449 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:55:33 +00:00
Jim Grosbach
06ef444e5c Add operand encoding bits for SMC and SVC in ARM mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:38:23 +00:00
Jim Grosbach
832859d062 More encoding cleanup. Also add register Rd operands for indirect branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:09:34 +00:00
Jim Grosbach
a7dbc1ead7 Simplify some ARM encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:48:54 +00:00
Eric Christopher
a9c575110f Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116438 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:41:51 +00:00
Jim Grosbach
6c354fd3f5 Add a FIXME. The ADR instruction is a bit odd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:32:30 +00:00
Jim Grosbach
b3af5de2d9 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:00:04 +00:00
Bill Wendling
67a704de03 Add MC encodings for VCVT* instrunctions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:58:46 +00:00
Jim Grosbach
596307e133 Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:38:04 +00:00
Jim Grosbach
fa7d2cb680 Make a few more bits of some simple instructions explicit. nop, yield, wfe, 
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:30:55 +00:00
Jim Grosbach
b35ad41fef Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 19:56:10 +00:00
Jim Grosbach
e822f94509 Fix encoding for compares. No Rd register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 18:05:25 +00:00
Jim Grosbach
24989ecc70 Add ARM mode operand encoding information for ADDE/SUBE instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 18:00:52 +00:00
Eric Christopher
ede42b0a22 Start handling more global variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116401 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 09:11:46 +00:00
Evan Cheng
14ce175216 Limit load / store issues (at least until we have a true multi-issue aware scheduler). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 01:54:21 +00:00
Bill Wendling
6932643a37 Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test 
just yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 01:17:33 +00:00
Bill Wendling
54908dd72b Add encodings for VCVT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:56:35 +00:00
Jim Grosbach
89c898f8af Add ARM encoding information for comparisons, forced-cc-out arithmetics, and 
arithmetic-with-carry-in instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:50:27 +00:00
Bill Wendling
1fc6d8837f Add VCMPZ and VABS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:38:07 +00:00
Bill Wendling
cd77686254 Refactor VCMP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:04:29 +00:00
Jim Grosbach
ef324d7044 Add the rest of the ARM so_reg encoding options (register shifted register) 
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:53:58 +00:00
Bill Wendling
5a1fd8cf68 Add encodings for VNMUL[SD]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:47:37 +00:00
Bill Wendling
caa3d467ab Add encodings for VDIV and VMUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:22:27 +00:00
Jim Grosbach
2a6a93d542 Move the ARM so_imm encoding into a custom operand encoder and remove the 
explicit handling of the instructions referencing it from the MC code
emitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:18:08 +00:00
Bill Wendling
52061f83e7 Refactor some of the encoding logic into a base class. This keeps us from having 
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116362 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:06:54 +00:00
Jim Grosbach
08bd54987f Add custom encoder for the 's' bit denoting whether an ARM arithmetic 
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:00:24 +00:00
Bill Wendling
dd3bc112e6 Add encoding for VSUB and VCMP. 
Fear not! I'm going to try a refactoring right now. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:55:35 +00:00
Bill Wendling
174777bb2b Encoding for VADDD. Plus a test for the VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:08:41 +00:00
Bill Wendling
a0c14ef8f6 Split out the "size" field from the encoding. The newer documentation has it as 
a separate bit in the coding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:03:19 +00:00
Eric Christopher
558cf007b5 Fix thinko in arm fast isel alloca rewrite. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 21:23:43 +00:00
Jim Grosbach
499e886fe6 Encoding for ARM-mode VADD.F32 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 21:22:40 +00:00
Jim Grosbach
f59818b81a Add MOVi ARM encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:09:12 +00:00
Jim Grosbach
8e157302f4 Nuke unused wrapper function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:53:25 +00:00
Jim Grosbach
0de6ab3c43 Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:11:26 +00:00
Bob Wilson
77f42b5278 PR8359: The ARM backend may end up allocating registers D16 to D31 when 
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 16:22:47 +00:00
Eric Christopher
1541877941 Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 05:39:06 +00:00
Eric Christopher
5532433a57 Handle a wider arrangement of loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 00:43:21 +00:00
Evan Cheng
08cec1ef27 More ARM scheduling itinerary fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:41:41 +00:00
Jim Grosbach
42fac8ee3b MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:16:21 +00:00
Jason W Kim
17b443df43 Second set of ARM/MC/ELF changes. 
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116257 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:01:44 +00:00
Evan Cheng
60ff87914f Proper VST scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 22:03:18 +00:00
Eric Christopher
5f9e8b971b Use a sane mechanism for that assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116249 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 22:01:22 +00:00
Eric Christopher
050d16c2a9 We're not going to handle dynamic allocas anywhere else. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116240 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 21:37:35 +00:00
Eric Christopher
fb0b892f7e Make sure that the call stack adjustments have default operands. Also 
leave custom lowerings for later.

Fixes some nightly tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 21:20:02 +00:00
Eric Christopher
8ff9a9da0a Found a bug turning this on by default. Disable again for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:26:21 +00:00
Eric Christopher
fa6b29dacd Fix help text. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:15:02 +00:00
Eric Christopher
feadddd6b6 Change flag from Enable to Disable since we're enabled by default. 
Also don't use fast-isel on non-darwin since it's untested.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116217 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 20:05:22 +00:00
Jim Grosbach
62547267f0 More binary encoding stuff, taking advantage of the new "by name" operand 
matching in tblgen to do the predicate operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 18:51:51 +00:00
Eric Christopher
a2efc5ff6e Turn on arm fast isel by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116212 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 18:48:18 +00:00
Francois Pichet
1265776243 MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 11:36:19 +00:00