Zoran Jovanovic
7dc193619e
Support for microMIPS load effective address.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 10:14:07 +00:00
Zoran Jovanovic
1ef2ca6994
Support for microMIPS FPU instructions 1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197815 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-20 15:44:08 +00:00
Zoran Jovanovic
bd2926b056
Support for microMIPS control instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197696 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 16:25:00 +00:00
Zoran Jovanovic
4267b16e78
Support for microMIPS LL and SC instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197692 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-19 16:12:56 +00:00
Matheus Almeida
4faa2b38fb
[mips][msa] Fix issue with immediate fields of LD/ST instructions
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not being correctly encoded/decoded.
In more detail, immediate fields of LD/ST instructions should be
divided/multiplied by the size of the data format before encoding and
after decoding, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-05 11:06:22 +00:00
Akira Hatanaka
92b8543819
[mips] Redefine TAILCALL as a pseudo instruction.
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195896 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 23:58:32 +00:00
Zoran Jovanovic
42cb3abadd
Use instr mapping for microMIPS in llvm-mc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 08:07:34 +00:00
Zoran Jovanovic
1206f1968b
Support for microMIPS trap instruction with immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 13:15:03 +00:00
Zoran Jovanovic
9f471750fa
Support for microMIPS trap instructions 1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-07 14:35:24 +00:00
Zoran Jovanovic
5c042162be
Support for microMIPS branch instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 14:53:22 +00:00
Zoran Jovanovic
1aaf43c2a2
Support for microMIPS jump instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 16:38:59 +00:00
Reed Kotler
cb2280e4c7
Make first substantial checkin of my port of ARM constant islands code to Mips.
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Before I just ported the shell of the pass. I've tried to keep everything
nearly identical to the ARM version. I think it will be very easy to eventually
merge these two and create a new more general pass that other targets can
use. I have some improvements I would like to make to allow pools to
be shared across functions and some other things. When I'm all done we
can think about making a more general pass. More to be ported but the
basic mechanism works now almost as good as gcc mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193509 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-27 21:57:36 +00:00
Akira Hatanaka
2ef99c5dff
[mips] Define a pseudo instruction which writes to both the lower and higher
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parts of the accumulators and gets expanded post-RA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 01:48:30 +00:00
Akira Hatanaka
397f6da28c
[mips] Use predicates to guard instructions using accumulator registers instead
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of relying on AddedComplexity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192665 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 01:21:37 +00:00
Akira Hatanaka
adb1297d49
[mips] Rename isel nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192663 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 01:12:50 +00:00
Benjamin Kramer
5af763cb2a
Mips: Disassemble sign-extended 64 bit immediates properly.
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This doesn't change the meaning of the output, but makes look right. PR17539.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192483 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 19:05:08 +00:00
Akira Hatanaka
243702b95a
[mips] Fix definition of mfhi and mflo instructions to read from the whole
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accumulator instead of its sub-registers, $hi and $lo.
We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:
mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2 // read lower 32-bit result from $lo.
mtlo $4 // write to $lo. the content of $hi becomes unpredictable.
mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value.
I don't have a test case for this change that reliably reproduces the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 18:49:46 +00:00
Vladimir Medic
d59ad8a801
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 09:48:56 +00:00
Robert Wilhelm
3f4f420ab7
Even more spelling fixes for "instruction".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-28 13:42:22 +00:00
Akira Hatanaka
6b2448326f
[mips] MUL should clobber HI0 and LO0.
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I cannot think of a test case that reliably triggers this bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191109 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-20 21:22:28 +00:00
Zoran Jovanovic
dcc425c630
Fixed bug when generating Load Upper Immediate microMIPS instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-14 07:35:41 +00:00
Zoran Jovanovic
ab48d10eff
Support for microMIPS DIV instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190745 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-14 07:15:21 +00:00
Zoran Jovanovic
47b33528d1
Support for misc microMIPS instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190744 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-14 06:49:25 +00:00
Akira Hatanaka
69f8e0935a
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
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into a 5-bit or 6-bit field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-07 00:02:02 +00:00
Akira Hatanaka
997c5dead8
[mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 23:52:46 +00:00
Akira Hatanaka
cd3c1b9af9
[mips] Delete unused classes and defs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 23:42:58 +00:00
Akira Hatanaka
1d04ca7987
[mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
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equivalent to "beq $zero, $zero, offset".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 23:40:15 +00:00
Akira Hatanaka
77e1ebd18f
[mips] Set instruction itineraries of loads, stores and conditional moves.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 23:28:24 +00:00
Vladimir Medic
638382e6f1
This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 13:08:00 +00:00
Vladimir Medic
dadd1fba32
This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:53:21 +00:00
Daniel Sanders
2fd3e67dc6
[mips][msa] Added load/store intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 12:04:29 +00:00
Akira Hatanaka
a796d90c0e
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
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Also, fix predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 00:55:15 +00:00
Akira Hatanaka
bf19dba2d4
[mips] Clean up definitions of move word from/to coprocessor instructions.
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189431 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 00:42:50 +00:00
Daniel Sanders
c9617b9a9d
[mips][msa] Added bitconverts for vector types for big and little-endian
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 09:40:30 +00:00
Vladimir Medic
e4bf77a128
This patch implements trap instructions for mips. The test cases are added.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189213 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 10:02:40 +00:00
Akira Hatanaka
a98a486ad1
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
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load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 21:08:22 +00:00
Akira Hatanaka
93877b3cbc
[mips] Guard micromips instructions with predicate InMicroMips. Also, fix
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assembler predicate HasStdEnd so that it is false when the target is micromips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 20:46:51 +00:00
Vladimir Medic
6f297afb7e
This patch implements wait instruction for mips. Examples are added in test files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188537 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 10:17:03 +00:00
Jack Carter
e2a9376b1b
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
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Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 12:24:57 +00:00
Akira Hatanaka
cbaf6d0cc3
[mips] Rename HIRegs and LORegs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 00:47:08 +00:00
Jack Carter
3f70e908c3
[Mips][msa] Added initial MSA support.
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* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions
Does not correctly prohibit use of both 32-bit FPU registers and MSA together.
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188313 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 20:54:07 +00:00
Jack Carter
da0860f78e
[Mips] Support for unaligned load/store microMips instructions
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This includes instructions lwl, lwr, swl and swr.
Patch by Zoran Jovnovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 20:19:16 +00:00
Vladimir Medic
809313970f
This patch implements ei and di instructions for mips. Test cases are added.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 13:07:23 +00:00
Akira Hatanaka
491d04969d
[mips] Rename accumulator register classes and FP register operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:54:26 +00:00
Akira Hatanaka
1858786285
[mips] Rename register classes CPURegs and CPU64Regs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:08:38 +00:00
Akira Hatanaka
014096e4d5
[mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'
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EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 22:35:29 +00:00
Akira Hatanaka
a1fe9ef62e
[mips] Replace usages of register classes with register operands. Also, remove
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unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 22:20:40 +00:00
Akira Hatanaka
ddbdeefa28
[mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,
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remove lines that are setting DecoderNamespace for pseudo atomic instructions.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187632 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 23:14:16 +00:00
Akira Hatanaka
52b7321a48
[mips] Define instruction itineraries IIArith and IILogic.
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 00:55:34 +00:00
Akira Hatanaka
8838da6587
[mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that
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turns "bal" into "bgezal".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187440 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 20:24:24 +00:00