compute it based on what it knows. As part of this, rename getSectionForMergeableConstant
to getSectionForConstant because it works for non-mergable constants also.
The only functionality change from this is that Xcore will start dropping
its jump tables into readonly section instead of data section in -static mode.
This should be fine as the linker resolves the relocations. If this is a
problem, let me know and we'll come up with another solution.
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should have no state that is specific to particular globals in the
section. In this case, it means the removal of the "isWeak" and
"ExplicitSection" bits. MCSection uses the new form of SectionKind.
To handle isWeak, I introduced a new SectionInfo class, which is
SectionKind + isWeak, and it is used by the part of the code generator
that does classification of a specific global.
The ExplicitSection disappears. It is moved onto MCSection as a new
"IsDirective" bit. Since the Name of a section is either a section
or directive, it makes sense to keep this bit in MCSection. Ultimately
the creator of MCSection should canonicalize (e.g.) .text to whatever
the actual section is.
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thing is #if0'd out anyway. Just simplify the code by reducing the interface.
Not deleting this is essential for Bill's continuing happiness.
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indicate that it is a predicate, not an emitter. This eliminates TAI
dependencies on Mangler and GlobalValue.
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and convert code to using it, instead of having lots of things
poke the isLookupPtrRegClass() method directly.
2. Make PointerLikeRegClass contain a 'kind' int, and store it in
the existing regclass field of TargetOperandInfo when the
isLookupPtrRegClass() predicate is set. Make getRegClass pass
this into TargetRegisterInfo::getPointerRegClass(), allowing
targets to have multiple ptr_rc things.
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it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
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'unnamed' bss section, but some impls would want a named one. Since
they don't have consistent behavior, just make each target do their
own thing, instead of doing something "sortof common" then having
targets change immutable objects later.
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group instead of a bunch of random unrelated ideas. Provide predicates
to categorize a SectionKind into a group, and use them instead of
getKind() throughout the code.
This also renames a ton of SectionKinds to be more consistent and
evocative, and adds a huge number of comments on the enums so that
I will hopefully be able to remember how this stuff works long from
now.
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- This is a simplified mechanism which just looks up a target based on the
target triple, with a few additional flags.
- Remove getClosestStaticTargetForModule, the moral equivalent is now:
lookupTarget(Mod->getTargetTriple, true, false, ...);
- This no longer does the fuzzy matching with target data (based on endianness
and pointer width) that getClosestStaticTargetForModule was doing, but this
was deemed unnecessary.
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for now. Make the section switching directives more consistent
by not including \n and including \t for them all.
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1. Spell SectionFlags::Writeable as "Writable".
2. Add predicates for deriving SectionFlags from SectionKinds.
3. Sink ELF-specific getSectionPrefixForUniqueGlobal impl into
ELFTargetAsmInfo.
4. Fix SectionFlagsForGlobal to know that BSS/ThreadBSS has the
BSS bit set (the real fix for PR4619).
5. Fix isSuitableForBSS to not put globals with explicit sections
set in BSS (which was the reason #4 wasn't fixed earlier).
6. Remove my previous hack for PR4619.
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- Instead of requiring targets to define a JIT quality match function, we just
have them specify if they support a JIT.
- Target selection for the JIT just gets the host triple and looks for the best
target which matches the triple and has a JIT.
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It's classifications now include elf-specific discriminators. Targets
that don't have these features (like darwin and pecoff) simply treat
data.rel like data, etc.
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The later doesn't depend on any crazy LLVM IR stuff, and this
pulls the concatenation of prefix with GV name (the root problem behind
PR4584) out one level.
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a new getSectionForMergableConstant hook. This removes one dependence
of TAI on Type, and provides the hook with enough info to make the
right decision based on whether the global has relocations etc.
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This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround.
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their appropriate sections before the code itself. They need to be emitted
before the function because on some targets (x86 but not x86_64) the later
may reference a JT or CP entry address
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be useful, and it's currently unused. (Some issues: it isn't actually
rich enough to capture the semantics on many architectures, and
semantics can vary depending on the type being shifted.)
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are referenced, ignore the relocation entry and patch the relocatable field with
the computed symbol offset directly
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starting in getCurrentFunctionEHName. Among other problems,
we would try to privative a "foo.eh" label, but end up emitting
the label as _Lfoo.eh instead of L_foo.eh on darwin. This is really
bad, and the linker has always tolerated these labels existing.
For now, just emit them as _foo.eh.
This patch also fixes problems with ".eh" labels on unnamed
functions and eliminates two strangely defined TargetAsmInfo
hooks.
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No target uses this currently. This patch only adds the mechanism so
that local installations can choose to enable this.
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Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
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--- Reverse-merging r75799 into '.':
U test/Analysis/PointerTracking
U include/llvm/Target/TargetMachineRegistry.h
U include/llvm/Target/TargetMachine.h
U include/llvm/Target/TargetRegistry.h
U include/llvm/Target/TargetSelect.h
U tools/lto/LTOCodeGenerator.cpp
U tools/lto/LTOModule.cpp
U tools/llc/llc.cpp
U lib/Target/PowerPC/PPCTargetMachine.h
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/PowerPC/PPCTargetMachine.cpp
U lib/Target/PowerPC/PPC.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/ARMTargetMachine.h
U lib/Target/ARM/ARM.h
U lib/Target/XCore/XCoreTargetMachine.cpp
U lib/Target/XCore/XCoreTargetMachine.h
U lib/Target/PIC16/PIC16TargetMachine.cpp
U lib/Target/PIC16/PIC16TargetMachine.h
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/Alpha/AlphaTargetMachine.cpp
U lib/Target/Alpha/AlphaTargetMachine.h
U lib/Target/X86/X86TargetMachine.h
U lib/Target/X86/X86.h
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.h
U lib/Target/CppBackend/CPPTargetMachine.h
U lib/Target/CppBackend/CPPBackend.cpp
U lib/Target/CBackend/CTargetMachine.h
U lib/Target/CBackend/CBackend.cpp
U lib/Target/TargetMachine.cpp
U lib/Target/IA64/IA64TargetMachine.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/IA64/IA64TargetMachine.h
U lib/Target/IA64/IA64.h
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/CellSPU/SPUTargetMachine.h
U lib/Target/CellSPU/SPU.h
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/CellSPU/SPUTargetMachine.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
U lib/Target/Mips/MipsTargetMachine.cpp
U lib/Target/Mips/MipsTargetMachine.h
U lib/Target/Mips/Mips.h
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Sparc/SparcTargetMachine.cpp
U lib/Target/Sparc/SparcTargetMachine.h
U lib/ExecutionEngine/JIT/TargetSelect.cpp
U lib/Support/TargetRegistry.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75820 91177308-0d34-0410-b5e6-96231b3b80d8
from.
- This commit is almost entirely propogating the reference through the
TargetMachine subclasses' constructor calls.
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- They still use the TargetMachineRegistry to populate the contents of the
-march option (via the listener interface). We can't just populate it in the
option parser because we can't expect the TargetRegistry to be populated yet
(we no longer rely on static constructors).
- There are a couple ways to finish killing off TargetMachineRegistry, but I
haven't figured out the cleanest one yet...
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- This is a temporary hack to aid in incremental refactoring, for now we
allocate a new TargetMachineRegistryEntry on every getClosest... call.
- No intended functionality change, other than the leaked memory.
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Targets implement a single global Target structure which will live in a new
<Target>/TargetInfo library; this will be present in any image which the target
is usable in.
- Optional target specific classes can then be registered and attached to the
Target description.
- Registration for normal Targets will be done via the initialization functions
instead of using static constructors.
- This allows clients to use a single interface to obtain target data, without
requiring the code generator be linked in. It also provides a natural
extension point for adding new optional target data (assembler parser,
disassembler, etc.).
- This also provides a new entry point for obtaining a target for a particular
triple (without a module).
- Not yet used, however this should eventually replace the TargetMachineRegistry.
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This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
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We'll eventually use this to print comments in asm files and do other
fun things.
This adds interfaces to the AsmPrinter and changes TableGen to invoke
the postInstructionAction when appropriate. It also add parameters to
TargetAsmInfo to control comment layout.
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Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
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registers based on dynamic conditions. For example, X86 EBP/RBP, when used as
frame register has to be spilled in the first fixed object. It should inform
PEI this so it doesn't get allocated another stack object. Also, it should not
be spilled as other callee-saved registers but rather its spilling and restoring
are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice.
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This stops gcc warning about possible uses of an uninitialized
value when compiling with assertions turned off.
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Implement LowerFORMAL_ARGUMENTS_SVR4().
Implement LowerCALL_SVR4().
Add support for split arguments.
Implement by value parameter passing for aggregates.
Add support for variable argument lists.
Create the spill area for argument registers of variable argument functions no longer at a fixed offset.
Make sure callee saved registers are spilled to the correct stack offsets.
Change allocation order of non-volatile floating-point registers.
Add VRSAVE to the list of callee-saved registers, add CallConvLowering for vararg calls.
Add support for variable argument calls with Vector arguments.
Add support for VR and VRSAVE save area, improve allocation order for non-volatile vector registers.
Stop creating illegal i8 values in LowerVASTART().
Add memory access width hints.
Make sure to reserve space on the stack for the frame pointer.
When using the SVR4 ABI, reserve r13 for the Small Data Area pointer.
Assure that the frame pointer is spilled to the correct location on the stack.
Some FP registers were not marked as volatile.
Make sure the i64 words from a long double are passed either both in registers or both on the stack.
Only put integer arguments in registers which are not marked with the inreg flag.
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With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
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have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
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The OpActions array had a limit of 32 value types, so change it to use
MVT::MAX_ALLOWED_VALUETYPE in its declaration and change the accesses to
this array to work with a VT.getSimpleVT() that is larger than 32.
Also, add a comment to the place where MVT::MAX_ALLOWED_VALUETYPE is
defined indicating that it must be a multiple of 32.
This is part of the work allow MVT::LAST_VALUETYPE be greater than 32.
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This change doubles the allowable value for MVT::LAST_VALUETYPE. It does
this by doing several things.
1. Introduces MVT::MAX_ALLOWED_LAST_VALUETYPE which in this change has a
value of 64. This value contains the current maximum for the
MVT::LAST_VALUETYPE.
2. Instead of checking "MVT::LAST_VALUETYPE <= 32", all of those uses
now become "MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_LAST_VALUETYPE"
3. Changes the dimension of the ValueTypeActions from 2 elements to four
elements and adds comments ahead of the declaration indicating the it is
"(MVT::MAX_ALLOWED_LAST_VALUETYPE/32) * 2". This at least lets us find
what is affected if and when MVT::MAX_ALLOWED_LAST_VALUETYPE gets
changed.
4. Adds initializers for the new elements of ValueTypeActions.
This does NOT add any types in MVT. That would be done separately.
This doubles the size of ValueTypeActions from 64 bits to 128 bits and
gives us the freedom to add more types for AVX.
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C bindings. Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.
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Support for .text relocations, implementing TargetELFWriter overloaded methods for x86/x86_64.
Use a map to track global values to their symbol table indexes
Code cleanup and small fixes
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LEA64_32r, eliminating a bunch of modifier logic stuff on addr modes.
Implement support for printing mbb labels as operands.
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