6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 19:29:31 +00:00
Code Issues Projects Releases Wiki Activity
32,770 Commits 39 Branches 0 Tags 277 MiB
c621ae7bba
Commit Graph

7712 Commits

Author SHA1 Message Date
Chris Lattner
c621ae7bba update this entry, now that Anton implemented shift/and lowering for 
switches.  There is one really easy isel thing here with tst we are not
getting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37400 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-02 18:45:14 +00:00
Evan Cheng
c354334ac4 Opcode modifier s comes after condition code. e.g. addlts, not addslt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37388 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-01 20:51:29 +00:00
Evan Cheng
144fd1ff0f Set ARM ifcvt duplication limit to 3 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37385 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-01 08:28:59 +00:00
Evan Cheng
df4da14948 Make jumptable non-predicable for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37381 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-06-01 00:56:15 +00:00
Chris Lattner
3a4205367d Fix the asmprinter so that a globalvalue can specify an explicit alignment 
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed.  This fixes some objc protocol
failures Devang tracked down.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37373 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-31 18:57:45 +00:00
Evan Cheng
c6f2f6fbb9 For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37351 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 23:34:19 +00:00
Evan Cheng
fd488edb1d For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37349 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 23:32:06 +00:00
Evan Cheng
62ccdbf0b3 Add missing const qualifiers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37342 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 18:42:18 +00:00
Evan Cheng
f277ee4be7 Add missing const qualifiers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37341 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 18:35:22 +00:00
Nicolas Geoffray
2fb813d70b Implementation of compilation callback in PPC ELF32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37340 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-29 16:33:18 +00:00
Dan Gohman
237898ac1f Add explicit qualification for namespace MVT members. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37320 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-24 14:33:05 +00:00
Evan Cheng
69d555611a Hooks for predication support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37308 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-23 07:22:05 +00:00
Evan Cheng
d90733035d Rename a parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37307 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-23 07:21:11 +00:00
Dale Johannesen
e6e435498c name change requested by review of previous patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37289 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-22 18:31:04 +00:00
Dale Johannesen
81da02b553 Make tail merging the default, except on powerPC. There was no prior art 
for a target-dependent default with a command-line override; this way
should be generally usable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37285 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-22 17:14:46 +00:00
Bill Wendling
cd6cea0823 We only need to specify the most-implied feature for an architecture. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37275 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-22 05:15:37 +00:00
Evan Cheng
94679e66bb Fix some -march=thumb regressions. tBR_JTr is not predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37272 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 23:17:32 +00:00
Dale Johannesen
f23b8cf239 Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37271 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 22:42:04 +00:00
Dale Johannesen
86d4069666 Add some patterns for PIC PC-relative loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37269 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 22:14:33 +00:00
Evan Cheng
5a18ebc70c BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37268 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 18:56:31 +00:00
Evan Cheng
126f17a176 BlockHasNoFallThrough() now returns true if block ends with a return instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37266 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-21 18:44:17 +00:00
Dan Gohman
f5135be3fc Apply this patch: 
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37240 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 23:21:46 +00:00
Chris Lattner
60c7a136f3 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37239 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 20:18:14 +00:00
Dan Gohman
fa0f77d9b7 Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37234 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 18:44:07 +00:00
Evan Cheng
dcc50a4aee Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37199 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 01:53:54 +00:00
Evan Cheng
e5e7ce458a Silence some compilation warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37197 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 01:19:57 +00:00
Evan Cheng
9f8cbd147c Set ARM if-conversion block size threshold to 10 instructions for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37194 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 00:19:34 +00:00
Evan Cheng
6ae3626a4f RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37193 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 00:18:17 +00:00
Evan Cheng
b5cdaa257e RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37192 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-18 00:05:48 +00:00
Dale Johannesen
8dd86c14d4 More effective breakdown of memcpy into repeated load/store. These are now 
in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37179 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 21:31:21 +00:00
Evan Cheng
213d2cf94f Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37173 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 18:45:50 +00:00
Evan Cheng
174f803395 Added missing patterns for UNPCKH* and PUNPCKH*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37172 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 18:44:37 +00:00
Chris Lattner
07c70cd866 This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't 
cause other regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37160 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 17:13:13 +00:00
Anton Korobeynikov
f840202953 Revert patch for PR1427. It breaks almost all vector tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37159 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 07:50:14 +00:00
Chris Lattner
ccde4cb8ab add support for 128-bit add/sub on ppc64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37158 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 06:52:46 +00:00
Chris Lattner
a066810681 add support for 128-bit integer add/sub 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37154 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 06:35:11 +00:00
Chris Lattner
da66472ea6 Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37141 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 03:29:42 +00:00
Evan Cheng
d9e9efb253 Remove. Not needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37139 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-17 00:11:35 +00:00
Evan Cheng
e425956b72 Default implementation of TargetInstrInfo::getBlockSize(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37138 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 23:53:44 +00:00
Evan Cheng
3f8602cf20 ARM::tB is also predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37125 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 21:53:43 +00:00
Evan Cheng
02c602b333 PredicateInstruction returns true if the operation was successful. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 21:53:07 +00:00
Evan Cheng
2eb80fa433 Add default implementation of PredicateInstruction(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37123 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 21:20:37 +00:00
Evan Cheng
75604f81b7 Move if-conversion after all passes that may use register scavenger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37120 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:52:46 +00:00
Evan Cheng
b5f8eff566 Removed isPredicable(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37119 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:50:23 +00:00
Evan Cheng
5ada199246 Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37118 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:50:01 +00:00
Evan Cheng
064d7cdd3c Added isPredicable bit to class Instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37117 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 20:47:01 +00:00
Evan Cheng
aeafca0a25 Conditional branch is not a barrier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37103 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 07:45:54 +00:00
Chris Lattner
738a6ec0ae implement the missing maskmovq mmx intrinsic that akor hit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37100 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 06:08:17 +00:00
Evan Cheng
2706f9771d Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37098 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 05:14:06 +00:00
Evan Cheng
9307292ae2 Hooks for predication support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37093 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-05-16 02:01:49 +00:00