Commit Graph

13593 Commits

Author SHA1 Message Date
Jim Grosbach
032434d622 ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 23:40:38 +00:00
Jim Grosbach
6f9f884502 ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:59:38 +00:00
Bruno Cardoso Lopes
53c95880f0 We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:28:55 +00:00
Jim Grosbach
14ab1c3387 ARM parsing and encoding tests for CMN/CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:26:58 +00:00
Jim Grosbach
d986bc66bc Shuffle ARM assembly tests a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:19:10 +00:00
Jim Grosbach
83ab070fc1 Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes
466b022c99 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:36:51 +00:00
Eli Friedman
2a01946de4 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile.
<rdar://problem/9763308>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:29:53 +00:00
Jim Grosbach
9bb098ad3a Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:14:23 +00:00
Jim Grosbach
f333d471d2 Testcases for ARM assembly BX/BXJ instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:25:46 +00:00
Jim Grosbach
37023b05c8 Testcases for ARM assembly BLX/BL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135072 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:11:04 +00:00
Jim Grosbach
fff76ee7ef Range checking for 16-bit immediates in ARM assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:10:10 +00:00
Evan Cheng
3fd6e755d0 Change test case, one that actually failed before my commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:19:44 +00:00
Jim Grosbach
21101d60ce Add tests for ARM parsing of 'BKPT' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:17:36 +00:00
Jim Grosbach
76cbe02cdd Fix copy-pasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:16:30 +00:00
Jim Grosbach
e52240c370 Add tests for ARM parsing of 'BIC' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:12:32 +00:00
Jim Grosbach
7ed6d22e96 Add some FIXMEs.
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:10:23 +00:00
Evan Cheng
93a635c82c It's not safe to fold (fptrunc (sqrt (fpext x))) to (sqrtf x) if there is another use of sqrt. rdar://9763193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:08:16 +00:00
Jim Grosbach
59642c2600 Add tests for ARM parsing of 'AND' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 18:55:14 +00:00
Jim Grosbach
19906729a4 Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 18:49:30 +00:00
Jim Grosbach
da9f278c74 Add tests for ARM parsing of 'ADD' instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135053 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 18:12:46 +00:00
Jim Grosbach
37ee464ea9 Destination register operand is optional for ADC and SBC ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 17:57:17 +00:00
Jim Grosbach
e8606dc7c8 Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 17:50:29 +00:00
Bruno Cardoso Lopes
61905f0139 AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 01:15:33 +00:00
Evan Cheng
e721f5c8d3 Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0

rdar://9758317


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 00:42:17 +00:00
Jim Grosbach
dc89561fec Add check for predicate w/o S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134987 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 16:25:04 +00:00
Jim Grosbach
92bf81ddd0 Improve test cases from r134746.
Use memory barriers to force if-conversion off for these tests instead of
the internal llc command line option ifcvt-limit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 16:06:01 +00:00
Andrew Trick
b9484cafcc Comment correction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134958 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 03:39:22 +00:00
Jim Grosbach
3f00e31706 Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 17:09:57 +00:00
Jim Grosbach
589130fac1 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 16:48:36 +00:00
NAKAMURA Takumi
fecdc98390 test/CodeGen/PowerPC/vector.ll: Tweak redirection >%t >%t to >%t >>%t. See also r134814 (test/CodeGen/X86/vector.ll).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 16:21:52 +00:00
Cameron Zwarich
ce3a9f51ce Add a missing test for r134882.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 08:35:17 +00:00
Evan Cheng
59ee62d241 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 03:57:24 +00:00
Rafael Espindola
b5a12dd12f Don't duplicate the work done by a gep into a "bitcast" if the gep has
more than one use.

Fixes PR10322.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134883 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 03:43:47 +00:00
Rafael Espindola
aecfdd3068 Move the loads after the calls so that the fix for
PR10292 doesn't show that the loads don't alias
the allocas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 23:53:58 +00:00
Rafael Espindola
4fe509431b Use CHECK-NEXT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 22:56:50 +00:00
Nick Lewycky
b4f6095bae Remove tests for APIs that were removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 18:55:51 +00:00
Chris Lattner
1afcace3a3 Land the long talked about "type system rewrite" patch. This
patch brings numerous advantages to LLVM.  One way to look at it
is through diffstat:
 109 files changed, 3005 insertions(+), 5906 deletions(-)

Removing almost 3K lines of code is a good thing.  Other advantages
include:

1. Value::getType() is a simple load that can be CSE'd, not a mutating
   union-find operation.
2. Types a uniqued and never move once created, defining away PATypeHolder.
3. Structs can be "named" now, and their name is part of the identity that
   uniques them.  This means that the compiler doesn't merge them structurally
   which makes the IR much less confusing.
4. Now that there is no way to get a cycle in a type graph without a named
   struct type, "upreferences" go away.
5. Type refinement is completely gone, which should make LTO much MUCH faster
   in some common cases with C++ code.
6. Types are now generally immutable, so we can use "Type *" instead 
   "const Type *" everywhere.

Downsides of this patch are that it removes some functions from the C API,
so people using those will have to upgrade to (not yet added) new API.  
"LLVM 3.0" is the right time to do this.

There are still some cleanups pending after this, this patch is large enough
as-is.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 17:41:24 +00:00
Chris Lattner
5445ecdf69 more tests not making the jump into the brave new world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 16:57:10 +00:00
Chris Lattner
ca5470c99d remove some crufy old tests that aren't adding much value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 16:55:16 +00:00
Chris Lattner
5fe319b3bd remove a test that doesn't make sense in the new world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 16:52:42 +00:00
NAKAMURA Takumi
9eb36758ac test/CodeGen/X86/vector.ll: Tweak temporary output to appease Win32 hosts.
With Lit (not bash) in a test, multiple redirects >%t might open(%t, "w") multiple. It can be avoided if latter redirect is >>%t.

It might work even if ">/dev/null" were used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 10:22:28 +00:00
Lang Hames
f86a547419 Added test cases for GVN signed intrinsics recognition, r134777.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134778 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 00:36:54 +00:00
Jakob Stoklund Olesen
56573cc1ae Hoist spills within a basic block.
Try to move spills as early as possible in their basic block. This can
help eliminate interferences by shortening the live range being
spilled.

This fixes PR10221.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 00:25:03 +00:00
Evan Cheng
3286920505 Add support for ARM / Thumb mode switching with .code 16 and .code 32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134760 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:36:29 +00:00
Evan Cheng
f0b3c12919 Fix broken x86_64 tests which specify non-64-bit cpu's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134756 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:29:33 +00:00
Eli Friedman
f06ff4eae3 Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134753 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:16:47 +00:00
Jim Grosbach
25e6d48220 Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:50:04 +00:00
Julien Lerouge
f29608267b Add _allrem, _aullrem and _allmul to the runtime for MSVC.
http://llvm.org/bugs/show_bug.cgi?id=10305


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:40:25 +00:00
Cameron Zwarich
33390848a7 Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:39:21 +00:00
Jakob Stoklund Olesen
51458ed09e Be more aggressive about following hints.
RAGreedy::tryAssign will now evict interference from the preferred
register even when another register is free.

To support this, add the EvictionCost struct that counts how many hints
are broken by an eviction. We don't want to break one hint just to
satisfy another.

Rename canEvict to shouldEvict, and add the first bit of eviction policy
that doesn't depend on spill weights: Always make room in the preferred
register as long as the evictees can be split and aren't already
assigned to their preferred register.

Also make the CSR avoidance more accurate. When looking for a cheaper
register it is OK to use a new volatile register. Only CSR aliases that
have never been used before should be avoided.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 20:46:18 +00:00
Jim Grosbach
245f5e8e2a Use ARMPseudoExpand for ARM tail calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134719 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 18:50:22 +00:00
Benjamin Kramer
9c64030445 Emit a more efficient magic number multiplication for exact sdivs.
We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.

  struct foo { char x[24]; };
  long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  sarl	$3, %eax
  imull	$-1431655765, %eax, %eax
instead of
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  movl	$715827883, %ecx
  imull	%ecx
  movl	%edx, %eax
  shrl	$31, %eax
  sarl	$2, %edx
  addl	%eax, %edx
  movl	%edx, %eax

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134695 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 10:31:30 +00:00
Lang Hames
1fb0955cab Make GVN look through extractvalues for recognised intrinsics. GVN can then CSE ops that match values produced by the intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 01:50:54 +00:00
Jakob Stoklund Olesen
2aa6b4c142 Fix more register allocation sensitive tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:24:06 +00:00
Jakob Stoklund Olesen
caab27963b Remove a test that no longer makes sense.
It was testing a linear scan feature:

  Test if linearscan is unfavoring registers for allocation to allow
  more reuse of reloads from stack slots.

The greedy register allocator doesn't access any stack slots in this
function, so the linear scan feature was not being tested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:24:03 +00:00
Nick Lewycky
9bf45d0b1a Let the inline asm 'q' constraint match float, and on 64-bit double too.
Fixes PR9602!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:19:27 +00:00
Eric Christopher
77ed1353bf Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine.

Fixes PR9675 and rdar://9740801


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 00:04:56 +00:00
Eric Christopher
31b5f00c4e Add support for the X86 'l' constraint.
Fixes PR10149 and rdar://9738585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134648 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 22:29:07 +00:00
Evan Cheng
18fb1d35db Add Mode64Bit feature and sink it down to MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 21:06:52 +00:00
Evan Cheng
39dfb0ff84 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 03:55:05 +00:00
Lang Hames
d0626aacca Added a testcase for PR10220.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134573 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:36:02 +00:00
Andrew Trick
037d1c0c7e indvars -disable-iv-rewrite: Added SimplifyCongruentIVs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134530 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 20:50:43 +00:00
Tobias Grosser
df7102b7d6 LICM: Do not loose alignment on promotion
The promotion code lost any alignment information, when hoisting loads and
stores out of the loop. This lead to incorrect aligned memory accesses. We now
use the largest alignment we can prove to be correct.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 19:19:55 +00:00
Jakub Staszak
9da9934e27 Introduce "expect" intrinsic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 18:22:43 +00:00
Kevin Enderby
d7c7e2ff7d Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 17:55:20 +00:00
Kevin Enderby
d521f2d2f1 Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
push with a small constant produces a 2-byte push.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134501 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 17:23:46 +00:00
Dan Gohman
211f53aa04 Revert r134366 and add an explicit triple to make this test host-independent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 22:09:19 +00:00
Eli Friedman
af45b3d8cb Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 18:21:20 +00:00
Jakob Stoklund Olesen
9693d4c3f0 Fix PR10277.
Remat during spilling triggers dead code elimination. If a phi-def
becomes unused, that may also cause live ranges to split into separate
connected components.

This type of splitting is different from normal live range splitting. In
particular, there may not be a common original interval.

When the split range is its own original, make sure that the new
siblings are also their own originals. The range being split cannot be
used as an original since it doesn't cover the new siblings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 15:38:41 +00:00
Benjamin Kramer
fc87cdc1f4 PR10267: Don't combine an equality compare with an AND into an inequality compare when the AND has more than one use.
This can pessimize code, inequalities are generally more expensive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134379 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-04 20:16:36 +00:00
NAKAMURA Takumi
7495ea7fe9 test/CodeGen/X86/lsr-nonaffine.ll: Relax expressions for Win64 CC to appease Win32 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134366 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-03 09:26:14 +00:00
Chandler Carruth
78e4fcecef FileCheck-ize another test. Reduces the llc invocations from 8 to 1, and
makes one of the tests actually mean something (as the string 'add' will
always appear in the output of this file).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 21:34:52 +00:00
Chandler Carruth
4ca11dea79 Avoid writing to an arbitrary filename during the test run by writing to
a file descriptor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134355 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:43:18 +00:00
Chandler Carruth
a42e665442 FileCheck-ize another X86 test, making it more precisely verify the
desired result based on the comments in the file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:43:16 +00:00
Chandler Carruth
898402dba4 Quote two greps which contain parentheses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:43:13 +00:00
Chandler Carruth
aea63ff104 FileCheck-ize and simplify RUN lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134352 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:43:11 +00:00
Chandler Carruth
432a8931e4 FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134351 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:43:08 +00:00
Chandler Carruth
327b8f1706 FileCheck-ize and tighten up assertions to only check the relevant sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134350 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:43:04 +00:00
Chandler Carruth
44f52f2d39 FileCheck-ize and cleanup IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134349 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:43:01 +00:00
Chandler Carruth
b3ce947ecf FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:59 +00:00
Chandler Carruth
f2a3b35a7c Remove a grep that is already checked with FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134346 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:56 +00:00
Chandler Carruth
3bd210ea8f FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:53 +00:00
Chandler Carruth
45177cb85c FileCheck-ize and modernize IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:50 +00:00
Chandler Carruth
36da1d9633 FileCheck-ize and simplify RUNs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134343 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:48 +00:00
Chandler Carruth
431d63b560 FileCheck-ize and modernize the RUN line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:44 +00:00
Chandler Carruth
03119ab3d7 FileCheck-ize, tightening checks and avoiding a temporary file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:42 +00:00
Chandler Carruth
5a26013390 FileCheck-ize, tightening checks and avoiding a temporary file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:39 +00:00
Chandler Carruth
2fa43a7315 FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:36 +00:00
Chandler Carruth
19318fe135 FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:33 +00:00
Chandler Carruth
fa9d797d73 FileCheck-ize a test, avoiding a temporary file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:31 +00:00
Chandler Carruth
d26117d7f6 FileCheck-ize and simplify this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134336 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:28 +00:00
Chandler Carruth
8a0a4de71f FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134335 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:25 +00:00
Chandler Carruth
8b89789188 FileCheck-ize another codegen test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134334 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:22 +00:00
Chandler Carruth
d95cb01823 Partially FileCheck-ize a test to remove a weird quoting situation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:20 +00:00
Chandler Carruth
218674ba61 FileCheck-ize another test, and upgrade its syntax a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134332 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:17 +00:00
Chandler Carruth
8f786a5834 FileCheck-ize another codegen test, tightening it up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:14 +00:00
Chandler Carruth
4d28d7365a FileCheck-ize another test, making it much more precise for testing the
individual cases, while hard coding less about registers in use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:11 +00:00
Chandler Carruth
549f123715 FileCheck-ize another test. This one is more clear and runs fewer
commands as a result.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134329 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:08 +00:00
Chandler Carruth
0d390f6366 FileCheck-ize a test, no functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 20:42:06 +00:00
Jakob Stoklund Olesen
9d812a2805 Better diagnostics when inline asm fails to allocate.
asm.c:2:7: error: ran out of registers during register allocation
  asm(""::"r"(0), "r"(1), "r"(2), "r"(3), "r"(4), "r"(5), "r"(6), "r"(7), "r"(8), "r"(9));
        ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134310 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 07:17:37 +00:00
Eric Christopher
839656120b Be less specific about register allocation ordering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134308 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 04:06:41 +00:00
Andrew Trick
4b02915386 indvars -disable-iv-rewrite: bug fix involving weird geps and related cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134306 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 02:34:25 +00:00
Eric Christopher
e3997d40de TargetConstant immediates won't be placed into registers so tighten
up the valid constant check earlier.

rdar://9692967


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 23:04:38 +00:00
Dan Gohman
71997f303e Teach IVUsers to stop at non-affine expressions unless they are both
outside the loop and reducible.

This more completely hides them from LSR, which isn't usually able to
do anything meaningful with non-affine expressions anyway, and this
consequently hides them from SCEVExpander, which is acutely unprepared
for non-affine expressions.

Replace test/CodeGen/X86/lsr-nonaffine.ll with a new test that tests
the new behavior.

This works around the bug in PR10117 / rdar://problem/9633149, and is
generally an improvement besides.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134268 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 22:05:19 +00:00
Jim Grosbach
a7603982db ARMv7M vs. ARMv7E-M support.
The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."

Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.

rdar://9572992



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 21:12:19 +00:00
Dan Gohman
68c0dbc14f Improve constant folding of undef for cmp and select operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134223 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 01:03:43 +00:00
Eric Christopher
5e653c925c Add support for the 'j' immediate constraint. This is conditionalized on
supporting the instruction that the constraint is for 'movw'.

Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 01:00:07 +00:00
Dan Gohman
30cb6dda5a Improve constant folding of undef for binary operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 00:42:17 +00:00
Eric Christopher
d5dc9eca2b Add support for the ARM 't' register constraint. And another testcase
for the 'x' register constraint.

Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 00:30:46 +00:00
Eric Christopher
89bd71fc53 Add support for the 'x' constraint.
Part of rdar://9307836 and rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 00:14:47 +00:00
Jakob Stoklund Olesen
098c7ac7c8 Fix a problem with fast-isel return values introduced in r134018.
We would put the return value from long double functions in the wrong
register.

This fixes gcc.c-torture/execute/conversion.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134205 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 23:42:18 +00:00
Eric Christopher
73744df0c4 Add support for the 'h' constraint.
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 23:23:01 +00:00
Jim Grosbach
63b46faeb8 Thumb1 register to register MOV instruction is predicable.
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 22:10:46 +00:00
Rafael Espindola
77a2c372fa Add r134057 back, but splice the predecessor after the successors phi
nodes.

Original message:
Let simplify cfg simplify bb with only debug and lifetime intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 20:14:24 +00:00
Andrew Trick
6e0ce24e0c indvars -disable-iv-rewrite: handle cloning binary operators that cannot overflow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 19:02:17 +00:00
Jim Grosbach
16f9924000 Pseudo-ize the t2LDMIA_RET instruction.
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134173 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 18:25:42 +00:00
Joerg Sonnenberger
ca0ede7655 Recognize the xstorerng alias for VIA PadLock's xstore instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134126 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 01:38:03 +00:00
Andrew Trick
60ac719c85 indvars -disable-iv-rewrite: handle an edge case involving identity phis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 01:27:23 +00:00
Eric Christopher
5d8aa345dd Fix a small thinko for constant i64 lock/orq optimization where we
we didn't have an opcode for 64-bit constant or expressions.

Fixes rdar://9692967


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 00:48:30 +00:00
Devang Patel
272511f518 Revert r133953 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 23:50:13 +00:00
Andrew Trick
cc359d9fa2 indvars -disable-iv-rewrite: insert new trunc instructions carefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134112 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 23:03:57 +00:00
Cameron Zwarich
faff127319 In the ARM global merging pass, allow extraneous alignment specifiers. This pass
already makes the assumption, which is correct on ARM, that a type's alignment is
less than its alloc size. This improves codegen with Clang (which inserts a lot of
extraneous alignment specifiers) and fixes <rdar://problem/9695089>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 22:24:25 +00:00
Chad Rosier
ce77aa3edc Temporarily revert r134057: "Let simplify cfg simplify bb with only debug and
lifetime intrinsics" due to buildbot failures.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 16:22:11 +00:00
Jim Grosbach
254cf03a45 Asm parser range checking on .<size> <value> directives.
For example, ".byte 256" would previously assert() when emitting an object
file. Now it generates a diagnostic that the literal value is out of range.

rdar://9686950


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 16:05:14 +00:00
Benjamin Kramer
8981bce73f Don't depend on the optimization reverted in r134067.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 14:07:18 +00:00
Benjamin Kramer
bdd1ef2dbe Revert a part of r126557 which could create unschedulable DAGs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 13:47:25 +00:00
Rafael Espindola
0fb7dcd48f Let simplify cfg simplify bb with only debug and lifetime intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 05:25:47 +00:00
Andrew Trick
11745d4c02 indvars -disable-iv-rewrite: just because SCEV ignores casts doesn't
mean they can be removed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134054 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 03:13:40 +00:00
NAKAMURA Takumi
5876298e36 Fix a CMake warning, following up to r134008.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134033 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 21:46:21 +00:00
Jakob Stoklund Olesen
9bbe4d6c00 Clean up the handling of the x87 fp stack to make it more robust.
Drop the FpMov instructions, use plain COPY instead.

Drop the FpSET/GET instruction for accessing fixed stack positions.
Instead use normal COPY to/from ST registers around inline assembly, and
provide a single new FpPOP_RETVAL instruction that can access the return
value(s) from a call. This is still necessary since you cannot tell from
the CALL instruction alone if it returns anything on the FP stack. Teach
fast isel to use this.

This provides a much more robust way of handling fixed stack registers -
we can tolerate arbitrary FP stack instructions inserted around calls
and inline assembly. Live range splitting could sometimes break x87 code
by inserting spill code in unfortunate places.

As a bonus we handle floating point inline assembly correctly now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 18:32:28 +00:00
Andrew Trick
8d4386efb7 cmake: Our MSVC build does not support config-time build mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 16:32:01 +00:00
Roman Divacky
bdb226ec83 Implement ISD::VAARG lowering on PPC32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 15:30:42 +00:00
Andrew Trick
4086bb5ba5 FileCheckify and prepare for -disable-iv-rewrite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133998 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 06:34:10 +00:00
Jakob Stoklund Olesen
c1ce95fc25 FileCheckize a couple of tests.
Also and add a test for popping dead return values and avoid testing the
spill precision.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 06:25:03 +00:00
Chandler Carruth
f3f955b5b9 FileCheck-ize a test that had the strangest TCL quote I've seen yet: an
opening single quote with no closing single quote, and with {} quotes
"inside" of it. This broke some of our tools that scrape test cases.

Also, while here, make the test actually assert what the comment says it
asserts. This was essentially authored by Nick Lewycky, and merely typed
in by myself. Let me know if this is still missing the mark, but the
previous test only succeeded due to the improper quoting preventing
*anything* from matching the grep -- it had a '4(%...)' sequence in the
output!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 02:03:10 +00:00
Jim Grosbach
adf7366771 ARM Thumb2 asm syntax optional destination operand for binary operators.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff

rdar://9672867



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133973 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 00:19:13 +00:00
Jim Grosbach
6b8f1e35ea ARM Assembly support for Thumb mov-immediate.
Correctly parse the forms of the Thumb mov-immediate instruction:
  1. 8-bit immediate 0-255.
  2. 12-bit shifted-immediate.

The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 23:54:06 +00:00
Evan Cheng
f10711fb8c Remove the experimental (and unused) pre-ra splitting pass. Greedy regalloc can split live ranges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 23:40:45 +00:00
Devang Patel
016c5829a5 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 22:32:04 +00:00
Eric Christopher
81ce26a410 Fix this test to actually check something and be able to be compiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 22:30:14 +00:00
Jim Grosbach
fbd01783a6 ARM assembler support for ldmfd/stmfd mnemonics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 20:32:18 +00:00
Eric Christopher
34720e193f Allow lr in the register options here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 20:31:01 +00:00
Jim Grosbach
0d06bb9548 ARM assembler support for vpush/vpop.
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.

rdar://9683231



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133932 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 20:00:07 +00:00
Jim Grosbach
0ff9220ccb ARM Assembly syntax support for arithmetic implied dest operand.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
  sub r2, r2, #6
  sub r2, #6

rdar://9682597



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 19:09:15 +00:00
Jakob Stoklund Olesen
e8431ba8cb Move all inline-asm-fpstack tests to a single file.
Also fix some of the tests that were actually testing wrong behavior -
An input operand in {st} is only popped by the inline asm when {st} is
also in the clobber list.

The original bug reports all had ~{st} clobbers as they should.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 17:27:37 +00:00
Nick Lewycky
9174d5c738 Teach one piece of scalarrepl to handle lifetime markers. When transforming an
alloca that only holds a copy of a global and we're going to replace the users
of the alloca with that global, just nuke the lifetime intrinsics. Part of
PR10121.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 05:40:02 +00:00
Dan Bailey
0b19acbb8f PTX: corrected tests that were failing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 19:41:17 +00:00
Dan Bailey
84149460d5 PTX: Reverting implementation of i8.
The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is
not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support
boolean values.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 18:16:28 +00:00
Chad Rosier
644eb9befc Test case for r133858 (tail call optimize in the presence of byval).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 02:44:56 +00:00