6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-21 00:32:23 +00:00
Code Issues Projects Releases Wiki Activity
19,653 Commits 39 Branches 0 Tags 277 MiB
cbec3b00bd
Commit Graph

4099 Commits

Author SHA1 Message Date
Chris Lattner
cbec3b00bd Put register classes in namespaces 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22924 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 18:50:46 +00:00
Chris Lattner
e7af178ccf Fix code that assumes the register info will be dumped into a target 
namespace instead of the reg class namespace.  Update getRegClassForType()
to use modified names due to tblgen change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22923 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 18:50:11 +00:00
Chris Lattner
28e728d75a put reg classes in namespaces 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22922 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 18:49:22 +00:00
Chris Lattner
1ff9540c17 Require that targets specify a namespace for their register classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22921 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 18:48:48 +00:00
Chris Lattner
6096f0d4c6 The skeleton target has never had an isel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22917 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 18:35:41 +00:00
Chris Lattner
8212203ab9 This code has always been dead on itanium 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22916 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 18:34:37 +00:00
Chris Lattner
5499742c06 This code has always been dead for alpha 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22915 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 18:33:26 +00:00
Chris Lattner
2505d6b727 The simple isel being gone makes this dead! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22914 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 18:32:03 +00:00
Chris Lattner
0b1e641b82 Now that the simple isels are dead, so is this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22913 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 18:30:39 +00:00
Chris Lattner
c19d5621ae Sparcv9 gets no operand info 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22909 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 16:56:56 +00:00
Duraid Madina
a91103430b a bugfix (up top) and a quick repair job: disable generation of dep.z 
(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22904 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 13:25:50 +00:00
Nate Begeman
27d53ba6dd Fix a bug where we were passing the wrong number of arguments to an 
instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22901 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 03:42:28 +00:00
Chris Lattner
80132a4b48 mark variable arity instructions as such. Alpha wins the battle for 
cleanest backend in this metric :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22893 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 00:51:37 +00:00
Chris Lattner
efc58be8ca Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR. 
I'm not convinced this is all of them,  but I can't do much testing, because
IA64 LLC crashes on big programs :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22892 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 00:47:42 +00:00
Chris Lattner
9d9dc816d0 add a few missing cases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22891 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 00:41:29 +00:00
Chris Lattner
b822abade7 Give ADJCALLSTACKDOWN/UP the correct operands. 
Give a whole bunch of other stuff variable operands, particularly FP.  The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable.  This will have to be fixed before we can dag->dag
the X86 backend.  The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22890 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 00:38:22 +00:00
Nate Begeman
02b88a4586 ISD::OR, and it's accompanying SelectBitfieldInsert 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22889 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 00:38:14 +00:00
Chris Lattner
679c408768 The variable SAR's only take one operand too 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22888 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 00:31:37 +00:00
Chris Lattner
fd444b2a69 Stop adding bogus operands to variable shifts on X86. These instructions 
only take one operand.  The other comes implicitly in through CL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22887 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 00:16:17 +00:00
Nate Begeman
73bfa71524 Remove the X86 and PowerPC Simple instruction selectors; their time has 
passed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22886 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 23:53:15 +00:00
Nate Begeman
c15ed447f4 Add shifts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22884 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 23:38:00 +00:00
Chris Lattner
45fcb8f410 Fix operand numbers by marking variable arity nodes as such and by fixing 
the operand lists of a few other nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22883 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 23:25:33 +00:00
Chris Lattner
3f852b45fc MFLR doesn't take an operand, the LR register is implicit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22882 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 23:24:50 +00:00
Chris Lattner
329cdc3801 Add a new flag 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22881 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 23:17:07 +00:00
Chris Lattner
0bc04231c0 Move this to the emitter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22877 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 20:08:53 +00:00
Jim Laskey
5b5f0b7fd5 More optimal solution for loading constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22870 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 18:58:23 +00:00
Chris Lattner
d607c12e8e After selecting the instructions for a basic block, emit the instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22869 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 18:46:06 +00:00
Chris Lattner
f5fac3b4a6 remove some unused stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22866 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 18:34:00 +00:00
Nate Begeman
58dfb08319 Fix int foo() { return 65535; } by using the top 16 bits of the constant 
as the argument to LIS rather than the result of HA16(constant).

The DAG->DAG ISel was already doing the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22865 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 18:14:49 +00:00
Nate Begeman
a694047813 Improve ISD::Constant codegen. 
Now for int foo() { return -1; } we generate:
_foo:
        li r3, -1
        blr

instead of
_foo:
        lis r2, -1
        ori r3, r2, 65535
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22864 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 18:01:39 +00:00
Chris Lattner
0c09a411e0 replace switch stmt with an assert, generate li 0 instead of lis 0 for 0, 
to make the code follow people's expectations better.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22861 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 17:16:52 +00:00
Jim Laskey
3285aadce9 Handle loading of 0x????0000 constants with a single instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22858 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 15:52:30 +00:00
Nate Begeman
cffc32b6e2 Add support for ISD::AND, and its various optimized forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22857 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 07:30:46 +00:00
Nate Begeman
131a880520 Maintain consistency in negating things 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22855 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 05:44:50 +00:00
Nate Begeman
0f3257a330 Implement XOR, remove a broken sign_extend_inreg case 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22854 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 05:00:13 +00:00
Nate Begeman
305a1c75cf Add a bunch more simple nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22851 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 03:04:18 +00:00
Nate Begeman
6a7d61179c Add a couple more nodes that are easy to handle 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22850 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 00:53:47 +00:00
Nate Begeman
b5a0668d43 Be fruitful and multiply! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22849 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 00:21:41 +00:00
Jim Laskey
b454cfd453 Better version of isIntImmediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22848 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 00:15:15 +00:00
Nate Begeman
26653500bb Teach the DAG->DAG ISel about FNEG, and how it can be used to invert 
several of the PowerPC opcodes that come in both negated and non-negated
forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22845 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 23:46:35 +00:00
Jim Laskey
b8df7c2213 Promote dependency for MathExtras.h out of Constants.h. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22839 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 20:04:34 +00:00
Jim Laskey
cb6682fa44 Culling out use of unions for converting FP to bits and vice versa. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22838 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 19:34:49 +00:00
Chris Lattner
8482dd894d add a beta option for turning on dag->dag isel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22837 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 19:33:30 +00:00
Chris Lattner
a5a91b1026 initial hack at a dag->dag instruction selector. This is obviously woefully 
incomplete, but it is a start.  It handles basic argument/retval stuff, immediates,
add and sub.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22836 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 19:33:03 +00:00
Chris Lattner
d1c4626e14 add prototype, remove dead proto 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22835 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 19:32:03 +00:00
Chris Lattner
9d6c45bdd7 Fix some bugs in the alpha backend, some of which I introduced yesterday, 
and some that were preexisting.  All alpha regtests pass now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22829 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 17:08:24 +00:00
Chris Lattner
6d9aed4f8f Fix a few small typos I noticed when converting this over to the DAG->DAG 
selector.  Also, there is no difference between addSImm and addImm, so just
use addImm, folding some branches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22819 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 01:25:14 +00:00
Jim Laskey
a033b4d8eb Removed UINT_TO_FP and SINT_TO_FP from ISel outright. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22818 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 01:14:38 +00:00
Andrew Lenharth
035b8abdab thinko. Should fix s4addl.ll regression 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22817 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 00:47:24 +00:00
Jim Laskey
361ca5c927 Remove ISel code generation for UINT_TO_FP and SINT_TO_FP. Now asserts if 
marked as legal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22816 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 00:41:40 +00:00