Bruno Cardoso Lopes
cada2d0966
Fix uninitialized variables and silence warnings
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132355 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 20:25:26 +00:00
Richard Osborne
a9b08aa25e
Fix 80 column violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 16:30:33 +00:00
Richard Osborne
9497466190
Add XCore intrinsic for crc8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 16:24:49 +00:00
Richard Osborne
7736c37c14
Add XCore intrinsic for crc32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132336 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 14:47:36 +00:00
Bruno Cardoso Lopes
895c1e2dee
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
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must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 03:33:27 +00:00
Bruno Cardoso Lopes
4e694c96f1
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
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nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes
d979686bb4
This patch implements the thread local storage. Implemented are General
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Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 02:53:58 +00:00
Rafael Espindola
6e032942cf
Use the dwarf->llvm mapping to print register names in the cfi
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directives.
Fixes PR9826.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 20:20:15 +00:00
Rafael Espindola
67dc11352d
Split ppc dwarf regnums into ppc64 and ppc32 flavours.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132315 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 18:24:44 +00:00
Rafael Espindola
7a067cc6e0
Introduce the DwarfRegAlias class for declaring that two registers have the
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same dwarf number. This will be used for creating a dwarf number to register
mapping.
The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 17:49:59 +00:00
Rafael Espindola
e99f75a300
Mark the 32 bit registers as invalid in 64 bit mode. In 64 bit mode they are
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subregisters of the 64 bit ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 16:04:54 +00:00
Rafael Espindola
053ba4fed6
Remove the DwarfNumbers from the subregisters. They should use DW_OP_bit_piece
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and for now the generic dwarf emission will automatically use the superregister
numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132312 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30 15:56:04 +00:00
John McCall
5f8fd54f08
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
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This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
Take 2, now with more basic competence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 19:50:32 +00:00
John McCall
7eebab2a82
I didn't mean to commit these residues of a personal project.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 19:41:56 +00:00
John McCall
832a9d1a76
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
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This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 19:39:04 +00:00
Rafael Espindola
03dc1868d1
Fix to match the dwarf register numbers that gdb uses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 03:58:16 +00:00
Rafael Espindola
11fd5c0cd9
Dwarf register 0 is r0, remove incorrect entries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132276 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 03:17:01 +00:00
Rafael Espindola
01eaf907b0
Remove the dwarf numbers from the D registers. They don't have dwarf numbers
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and should probably be encoded as
DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 02:21:01 +00:00
Cameron Zwarich
c152aa6c86
Fix ARM fast isel to correctly flag memory operands to stores. This fixes
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-verify-machineinstrs failures on several tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132268 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 20:34:49 +00:00
Bruno Cardoso Lopes
a0112d0c39
Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
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to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 04:07:29 +00:00
Eric Christopher
fea51fc007
This actually starts at offset 0, not 1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 03:16:22 +00:00
Akira Hatanaka
5e93d1c615
Change the set of callee-saved registers for non-MIPS32 architectures specified
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in MipsRegisterInfo::getCalleeSavedRegs so that both registers paired for a
double precision register get saved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 01:41:05 +00:00
Eric Christopher
3c14f24c9d
Implement the 'M' output modifier for arm inline asm. This is fairly
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register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.
rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 01:40:44 +00:00
Akira Hatanaka
342837d0dc
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
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Need this to prevent emitting illegal conditional move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 01:07:07 +00:00
Rafael Espindola
36ea4f0206
Add 132187 back now that the real problem is fixed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 00:24:37 +00:00
Cameron Zwarich
de64aaf6c8
Fix the remaining atomic intrinsics to use the right register classes on Thumb2,
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and add some basic tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 23:54:00 +00:00
Bruno Cardoso Lopes
be64b39431
ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
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mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 23:46:09 +00:00
Rafael Espindola
157371f376
It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while I check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132230 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 23:36:02 +00:00
Cameron Zwarich
f5e771db37
Add a GR32_NOREX_NOSP register class and fix a bug where getMatchingSuperRegClass()
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was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132225 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 22:26:04 +00:00
Rafael Espindola
5b23b7fe31
Make size computation less brittle.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 22:05:41 +00:00
Evan Cheng
4abce0c90b
Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 20:11:27 +00:00
Jakob Stoklund Olesen
11f6cc96bf
Delete MethodBodies that only filtered reserved registers.
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The register allocators know to filter reserved registers from the allocation
orders, so we don't need all of this boilerplate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132199 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 18:27:13 +00:00
Eli Friedman
a4d487fc1e
Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 18:02:04 +00:00
Rafael Espindola
25b15d8502
Remove DwarfRegNum from the individual bits of the condition register.
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These should be DW_OP_bit_piece of CR (64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 16:15:27 +00:00
Rafael Espindola
81a2745830
Remove DwarfRegNum from CARRY. I should be encoded with DW_OP_bit_piece.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132190 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 16:01:08 +00:00
Rafael Espindola
81e193cc1f
Remove dwarf numbers from subregs. We should use DW_OP_bit_piece to
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refer to them.
I tested this with both check-all and the gdb testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132187 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 15:08:24 +00:00
Eric Christopher
33281b2361
Make the branch encoding for tBcc more obvious that it's a 4-byte opcode
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followed by a conditional and imm8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 03:50:53 +00:00
Eric Christopher
86bbcbf4b0
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132178 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 03:46:51 +00:00
Chad Rosier
62660310d9
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist.
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crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 23:13:19 +00:00
Akira Hatanaka
33458fedb6
Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if
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a function has any function calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 20:30:31 +00:00
Rafael Espindola
a5e62019d7
Fix some dwarf register numbers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132136 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 19:25:47 +00:00
Akira Hatanaka
cf0cd8005c
Add support for C++ exception handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 18:59:03 +00:00
Eric Christopher
32bfb2c513
Reorganize these slightly according to operand type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132128 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 18:22:26 +00:00
Akira Hatanaka
78e72d60ec
Set HasSetDirective to true.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 18:16:18 +00:00
Stuart Hastings
2aa0f23e1c
Reverting 132105: it broke some LLVM-GCC DejaGNU tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 04:09:49 +00:00
Cameron Zwarich
421b106872
Mark tBX as an indirect branch rather than a return.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 03:41:12 +00:00
Stuart Hastings
aa4e6afc9b
Correctly handle a one-word struct passed byval on x86_64.
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rdar://problem/6920088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 02:44:56 +00:00
Eli Friedman
76927d7303
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
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The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 23:49:02 +00:00
Akira Hatanaka
37d22d92df
Define WeakRefDirective.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 23:30:30 +00:00
Cameron Zwarich
ad70f6d2b1
Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 21:53:50 +00:00