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12433 Commits

Author SHA1 Message Date
Bob Wilson
79f56c9618 Fix a compiler crash where a Glue value had multiple uses. Radar 9049552. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127198 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-08 01:17:20 +00:00
Bill Wendling
3116dce338 Rename the narrow shift right immediate operands to "shr_imm*" operands. Also 
expand the testing of the narrowing shift right instructions.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-07 23:38:41 +00:00
Devang Patel
cd77a50e63 Preserve line no. info. 
Radar 9097659


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-07 22:43:45 +00:00
Rafael Espindola
e390b3245f Add test for r127138. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-07 21:28:14 +00:00
Nick Lewycky
bf433e5f46 Tweak this test. We can analyze what happens and show that we still do the 
right thing, instead of merely being unable to analyze and the transform
doesn't occur.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127149 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-07 02:10:18 +00:00
Nick Lewycky
c14bc77315 Add more analysis of the sign bit of an srem instruction. If the LHS is negative 
then the result could go either way. If it's provably positive then so is the
srem. Fixes PR9343 #7!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-07 01:50:10 +00:00
Nick Lewycky
d01f50f42c ConstantInt has some getters which return ConstantInt's or ConstantVector's of 
the value splatted into every element. Extend this to getTrue and getFalse which
by providing new overloads that take Types that are either i1 or <N x i1>. Use
it in InstCombine to add vector support to some code, fixing PR8469!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-06 03:36:19 +00:00
Jakob Stoklund Olesen
7cefa640de Revert r127073: "Introduce $(ECHOPATH) to print DOSish path string on MSYS bash for alternative of $(ECHO)." 
It broke the llvm-gcc-native-mingw32 buildbot, and we need all of them to be green for the 2.9 branch.

Takumi, please reapply after we branch, preferably with a fix ;-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 18:55:06 +00:00
Che-Liang Chiou
0df2c50c2b ptx: add basic intrinsic support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127084 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 14:17:37 +00:00
NAKAMURA Takumi
0c3ed6b046 Introduce $(ECHOPATH) to print DOSish path string on MSYS bash for alternative of $(ECHO). 
On mingw and python/w32, lit would not be expected to understand MSYS-style path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127073 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 09:46:45 +00:00
Nick Lewycky
58bfcdbcf6 Thread comparisons over udiv/sdiv/ashr/lshr exact and lshr nuw/nsw whenever 
possible. This goes into instcombine and instsimplify because instsimplify
doesn't need to check hasOneUse since it returns (almost exclusively) constants.

This fixes PR9343 #4 #5 and #8!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127064 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 05:19:11 +00:00
Nick Lewycky
9feda1730c Try once again to optimize "icmp (srem X, Y), Y" by turning the comparison into 
true/false or "icmp slt/sge Y, 0".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 04:28:48 +00:00
NAKAMURA Takumi
89be0acecf test/CodeGen/X86/vec_cast.ll: [PR8311] Add explicit -mtriple=x86_64-linux and -mtriple=x86_64-win32. Thanks to Nadav, it might be fixed in r126424. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-05 02:38:02 +00:00
Bruno Cardoso Lopes
38b5e86b9c Improve div/rem node handling on mips. Patch by Akira Hatanaka 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127034 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes
650af5d0f8 Add testcase for r127032 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127033 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 20:48:39 +00:00
Dan Gohman
a7a841adb8 When decling to reuse existing expressions that involve casts, ignore 
bitcasts, which are really no-ops here. This fixes slowdowns on
MultiSource/Applications/aha and others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127031 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 20:46:46 +00:00
Joerg Sonnenberger
89e0f386f3 Be nice to Xcore and the XMOS assembler and avoid quoting section names 
that contain only letters, digits and the characters "_" and ".".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 20:03:14 +00:00
Bruno Cardoso Lopes
ca8a2aa921 Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127027 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 20:01:52 +00:00
Devang Patel
c8888c7d80 XFAIL for all. These tests are darwin specific anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 19:38:10 +00:00
Nick Lewycky
e2ee753bc4 Revert broken srem logic from r126991. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 19:26:08 +00:00
Devang Patel
53dc40a45f Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 19:11:05 +00:00
Kalle Raiskila
31cbac1cfe Allow vector shifts (shl,lshr,ashr) on SPU. 
There was a previous implementation with patterns that would 
have matched e.g. 
	shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 13:19:18 +00:00
Kalle Raiskila
7f5de8b4c6 Allow load from constant on SPU. 
A 'load <4 x i32>* null' crashes llc before this fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 12:00:11 +00:00
Nick Lewycky
786792784e Fold "icmp pred (srem X, Y), Y" like we do for urem. Handle signed comparisons 
in the urem case, though not the other way around. This is enough to get #3 from
PR9343!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126991 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 10:06:52 +00:00
Nick Lewycky
3a73e343d0 Teach instruction simplify to use constant ranges to solve problems of the form 
"icmp pred %X, CI" and a number of examples where "%X = binop %Y, CI2".

Some of these cases (div and rem) used to make it through opt -O2, but the
others are probably now making code elsewhere redundant (probably instcombine).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126988 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 07:00:57 +00:00
Eli Friedman
86d822df6d Followup to r126970: add 64-bit encoding tests for str with reg operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126987 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 04:06:47 +00:00
Eli Friedman
ac39bd534b PR9377: Handle x86 str with register operand in a way consistent with gas. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 00:10:17 +00:00
Eli Friedman
81c5ef8649 Revert r123908; the code in question is completely untested and wrong. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126964 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 22:33:23 +00:00
Joerg Sonnenberger
ea83b13350 Bug#9033: For the ELF assembler output, always quote the section name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 22:31:08 +00:00
Richard Osborne
022708f221 Optimize fprintf -> iprintf if there are no floating point arguments 
and siprintf is available on the target.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126940 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 14:20:22 +00:00
Richard Osborne
419454ad37 Optimize sprintf -> siprintf if there are no floating point arguments 
and siprintf is available on the target.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 14:09:28 +00:00
Richard Osborne
3649824bec Optimize printf -> iprintf if there are no floating point arguments 
and iprintf is available on the target. Currently iprintf is only
marked as being available on the XCore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126935 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 13:17:51 +00:00
Eli Friedman
78c1e1781c PR9352: Always emit a relocation for weak symbols. Not emitting relocations 
for calls to weak symbols with a definition has the appearance of working
with LLVM-generated code because weak symbol definitions are put in their
own sections.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126933 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 07:24:36 +00:00
Bob Wilson
1473f35c47 TableGen should not ignore BX instructions for the ARM disassembler. pr9368. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126931 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 07:19:52 +00:00
Bill Wendling
f27a40a971 Check the ASM, not LLVM IR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126918 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 02:02:12 +00:00
Bob Wilson
181d3fe727 pr9367: Add missing predicated BLX instructions. 
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 01:41:01 +00:00
Bill Wendling
cb1c195f53 Testcase for r126913. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126914 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 01:32:56 +00:00
Stuart Hastings
44456e86c8 Test case for r126864. Radar 9056407. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126900 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 23:41:40 +00:00
Stuart Hastings
621c65e089 Test case for r126672. Radar 9055247. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126896 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 23:24:44 +00:00
Kevin Enderby
d39647d913 Fixes an assertion failure while disassembling ARM rsbs reg/reg form. 
Patch by Ted Kremenek!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 23:08:33 +00:00
David Greene
a20244d1ba [AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement 
missing patterns for them.

      Add a SIMD test subdirectory to hold tests for SIMD instruction
      selection correctness and quality.
'


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 17:23:43 +00:00
Cameron Zwarich
56e3793acf Eliminate the unused CodeGenPrepare option to split critical edges. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126825 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 03:31:46 +00:00
Che-Liang Chiou
fd8978b021 Extend initial support for primitive types in PTX backend 
- Allow i16, i32, i64, float, and double types, using the native .u16,
  .u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.

Patch by Justin Holewinski



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126824 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 03:20:28 +00:00
Dan Gohman
0cbe91ba3b Don't re-use existing addrec expansions if they contain casts. 
This fixes PR9259.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126812 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 01:34:10 +00:00
Evan Cheng
f06e6c2ba7 Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 01:08:17 +00:00
Anders Carlsson
d70be0b2c1 Make InstCombiner::FoldAndOfICmps create a ConstantRange that's the 
intersection of the LHS and RHS ConstantRanges and return "false" when
the range is empty.

This simplifies some code and catches some extra cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126744 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-01 15:05:01 +00:00
Nick Lewycky
88cd0aadb2 Optimize "icmp pred (urem X, Y), Y" --> true/false depending on pred. There's 
more work to do here, "icmp ult (urem X, 10), 11" doesn't optimize away yet.
Fixes example 3 from PR9343!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126741 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-01 08:15:50 +00:00
Bill Wendling
a656b63ee4 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-01 01:00:59 +00:00
Eli Friedman
f291ab2fba Add an obvious missing safety check to DAE::RemoveDeadArgumentsFromCallers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126720 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-01 00:33:47 +00:00
Dan Gohman
a722e781cc Delete obsolete test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126680 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 19:58:14 +00:00
Jakob Stoklund Olesen
bafd516d3e Fix typo introduced by r126661: "Fix a typo which ..." 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126666 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 19:18:59 +00:00
Kevin Enderby
d436d5b1c9 Fix the arm's disassembler for blx that was building an MCInst without the 
needed two predicate operands before the imm operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 18:46:31 +00:00
Evan Cheng
c24ab5c654 Fix a typo which cause dag combine crash. rdar://9059537. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126661 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 18:45:27 +00:00
Duncan Sands
377ffe3b11 Windows codegen also dies on this, so restrict to the platform it was 
actually tested on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126652 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 14:22:08 +00:00
Duncan Sands
443612e165 Make this test x86 specific because the ARM backend can't handle it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126650 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 12:30:47 +00:00
Frits van Bommel
f7b2a9d7df Teach SimplifyCFG that (switch (select cond, X, Y)) is better expressed as a branch. 
Based on a patch by Alistair Lynn.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 09:44:07 +00:00
Nick Lewycky
3dc7e49c70 srem doesn't actually have the same resulting sign as its numerator, you could 
also have a zero when numerator = denominator. Reverts parts of r126635 and
r126637.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 09:17:39 +00:00
Nick Lewycky
b042f8e969 Teach InstCombine to fold "(shr exact X, Y) == 0" --> X == 0, fixing #1 from 
PR9343.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126643 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 08:31:40 +00:00
Che-Liang Chiou
f71720231f Add preliminary support for .f32 in the PTX backend. 
- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
  to accept the float type.
- Add appropriate test cases.

Patch by Justin Holewinski



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 06:34:09 +00:00
Nick Lewycky
d8d1584c13 The sign of an srem instruction is the sign of its dividend (the first 
argument), regardless of the divisor. Teach instcombine about this and fix
test7 in PR9343!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 06:20:05 +00:00
Duncan Sands
9c45251e11 Legalize support for fpextend of vector. PR9309. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126574 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-27 14:41:27 +00:00
NAKAMURA Takumi
419f232783 Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs. 
It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126568 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-27 08:47:19 +00:00
Cameron Zwarich
eee444cc4e Fix PR9324 / <rdar://problem/9052489> by handling the case where a PHI has no uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-27 08:06:01 +00:00
Cameron Zwarich
60c8b22dad Give a test file a more sensible name so that it can hold more test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126566 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-27 08:05:57 +00:00
Benjamin Kramer
7466678003 Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic. 
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible

It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-26 22:48:07 +00:00
Chris Lattner
98ea4ce516 split this test into arch specific pieces, so the ARM 
test isn't run when the arm backend isn't built.  This
fixes PR9327


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126500 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-25 19:06:35 +00:00
Benjamin Kramer
278be783b5 Revert "SimplifyCFG: GEPs with just one non-constant index are also cheap." 
Yes, there are other types than i8* and GEPs on them can produce an add+multiply.
We don't consider that cheap enough to be speculatively executed.

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 2011-02-25 10:33:33 +00:00
Bob Wilson
da52506792 Add patterns to use post-increment addressing for Neon VST1-lane instructions. 
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 2011-02-25 06:42:42 +00:00
Benjamin Kramer
9ae59e3444 SimplifyCFG: GEPs with just one non-constant index are also cheap. 
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 2011-02-24 23:26:09 +00:00
Benjamin Kramer
9b61c550c2 SimplifyCFG: GEPs with constant indices are cheap enough to be executed unconditionally. 
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 2011-02-24 22:46:11 +00:00
Joerg Sonnenberger
93c65e6e66 Restore r125595 (reverted in r126336) with modifications: 
Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.


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 2011-02-24 21:59:22 +00:00
Nadav Rotem
8c20ec54d9 Enable support for vector sext and trunc: 
Limit the folding of any_ext and sext  into the load operation to scalars.
Limit the active-bits trunc optimization to scalars.
Document vector trunc and vector sext in LangRef.

Similar to commit 126080 (for enabling zext).



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 2011-02-24 21:01:34 +00:00
Devang Patel
3a96275200 Remove obsolete tests. 
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 2011-02-24 19:09:52 +00:00
Devang Patel
3fe3424a21 Move arch specific tests in arch specific directories. 
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 2011-02-24 19:06:27 +00:00
Richard Osborne
21d7eb3f3b Add XCore intrinsic for eeu instruction. 
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 2011-02-24 13:39:18 +00:00
NAKAMURA Takumi
027f98cd3b test/lit.cfg: Add PATHEXT to 'substitution', to recognize tools on Windows hosts. Thanks to Danil Malyshev! 
Some tests on Windows use the "not" utility and fail with an error "program not executable". The reason for this error is that the name of the executable file sended to the "not" without the extension.

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 2011-02-24 12:34:34 +00:00
Cameron Zwarich
8ca814c4e0 Merge information about the number of zero, one, and sign bits of live-out 
registers at phis. This enables us to eliminate a lot of pointless zexts during
the DAGCombine phase. This fixes <rdar://problem/8760114>.

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 2011-02-24 10:00:25 +00:00
Chris Lattner
091b1e3c74 change instcombine to not turn a call to non-varargs bitcast of 
function prototype into a call to a varargs prototype.  We do
allow the xform if we have a definition, but otherwise we don't
want to risk that we're changing the abi in a subtle way.  On
X86-64, for example, varargs require passing stuff in %al.


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 2011-02-24 05:10:56 +00:00
Evan Cheng
7558e2e415 Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memory 
operands starts at index 2, not 1.
rdar://9045024
PR9305


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 2011-02-24 02:36:52 +00:00
Devang Patel
3a4ae32ed7 Use DW_FORM_data2 for DW_AT_language and let users use DW_LANG_lo_user=0x8000 to DW_LANG_hi_user=0xffff range. 
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 2011-02-23 22:37:04 +00:00
Devang Patel
1d6b2c74c0 Check only relevant strings in output to increase stability of the tests. 
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 2011-02-23 22:35:57 +00:00
Jim Grosbach
f956183643 Remove file. Previous commit deleted content, but left the file around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 21:43:31 +00:00
Jim Grosbach
33b7bebca4 Revert r125595, which is an X86-only undocumented assembly syntax extension 
enabled for all targets. Non-X86 targets should not have this behavior
enabled by default.

Joerg, if you would like to resubmit with the behavior conditionalized to be
X86-ELF only, that's fine.



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 2011-02-23 21:26:51 +00:00
Rafael Espindola
21451e533f Put in the symbol table symbols only used in a .globl statement. 
Fixes PR9292.

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 2011-02-23 20:22:07 +00:00
Richard Osborne
d04b4937d1 Add XCore intrinsic for clre instruction. 
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 2011-02-23 18:52:05 +00:00
Richard Osborne
9935bd0819 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.


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 2011-02-23 18:35:59 +00:00
Richard Osborne
292f62e06f Add XCore intrinsic for the setv instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 16:46:37 +00:00
Richard Osborne
2a2cb28526 Add XCore intrinsic for settw instruction. 
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 2011-02-23 14:45:03 +00:00
Sean Callanan
8fbc00b5ba Fixed a bug in the enhanced disassembler that caused 
it to ignore valid uses of FS and GS as additional
base registers in address computations.  Added a test
case for this.


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 2011-02-23 03:31:28 +00:00
Evan Cheng
e573fb3255 More fcopysign correctness and performance fix. 
The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.

The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
        vmov.i32        d1, #0x80000000
        vbsl    d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702


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 2011-02-23 02:24:55 +00:00
Cameron Zwarich
c4f3d51e12 Make LoopDeletion work on loops with multiple edges, as long as the incoming 
values from all of the loop's exiting blocks are equal. Patch by Andrew Clinton.

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 2011-02-22 22:25:39 +00:00
Joerg Sonnenberger
00743c2218 Use the same (%dx) hack for in[bwl] as for out[bwl]. 
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 2011-02-22 20:40:09 +00:00
NAKAMURA Takumi
6023efb45d Revert r126195, "test/CodeGen/X86/vec_cast.ll: Mark as XFAIL: migw,win32 for workaround of PR8311." 
It seems it affected configuration --target=i686-pc-mingw32, I don't know and will investigate why.

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 2011-02-22 08:22:54 +00:00
NAKAMURA Takumi
0de102b9d8 Relax expressions and add explicit triplets -linux and -win32. 
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 2011-02-22 07:21:59 +00:00
NAKAMURA Takumi
65e9404646 Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126215 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:21:51 +00:00
NAKAMURA Takumi
3f38d20f95 Relax expressions and add explicit triplets -linux and -win32. 
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 2011-02-22 07:21:42 +00:00
NAKAMURA Takumi
aef8871177 Relax expressions and add explicit triplets -linux and -win32. 
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 2011-02-22 07:21:33 +00:00
NAKAMURA Takumi
88234f14a8 Relax expressions and add explicit triplets -linux and -win32. 
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 2011-02-22 07:21:25 +00:00
NAKAMURA Takumi
902f128141 Relax expressions and add explicit triplets -linux and -win32. 
On @foobar(double %d, double* %x),
AMD64: (%xmm0, %rdi)
Win64: (%xmm0, %rdx) (not %rcx!)

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 2011-02-22 07:21:17 +00:00
NAKAMURA Takumi
166b79fb24 Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126210 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:21:08 +00:00