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1298 Commits

Author SHA1 Message Date
Rafael Espindola
9472fd7403 Refactor the setting of PrivateGlobalPrefix. 
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196170 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-02 23:39:26 +00:00
Rafael Espindola
4a6855441c Change the default of AsmWriterClassName and isMCAsmWriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196065 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-02 04:55:42 +00:00
NAKAMURA Takumi
ef70d2a393 [CMake] Let add_public_tablegen_target() provide intrinsics_gen, too. 
I think, in principle, intrinsics_gen may be added explicitly.
That said, it can be added incidentally, since each target already has dependencies to llvm-tblgen.
Almost all source files depend on both CommonTaleGen and intrinsics_gen.

Explicit add_dependencies() have been pruned under lib/Target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195929 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-28 17:04:31 +00:00
NAKAMURA Takumi
ad363187c4 [CMake] Let add_public_tablegen_target responsible to provide dependency to CommonTableGen. 
add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS.
LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195927 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-28 17:04:04 +00:00
NAKAMURA Takumi
9ec9b8434b [CMake] Prune include_directories() in llvm/lib/Target. add_llvm_target() sets them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195921 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-28 14:53:30 +00:00
NAKAMURA Takumi
da99801ab4 SparcFrameLowering.cpp: Prune 'DL' [-Wunused-variable] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195590 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-25 00:52:46 +00:00
Venkatraman Govindaraju
2fee935bba [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195576 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-24 20:23:25 +00:00
Venkatraman Govindaraju
845e93818a [Sparc]: Implement LEA pattern for sparcv9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195575 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-24 20:07:35 +00:00
Venkatraman Govindaraju
cf09ce3b08 [SparcV9]: Do not emit .register directives for global registers that are clobbered by calls but not used in the function itself. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195574 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-24 18:41:49 +00:00
Venkatraman Govindaraju
591719e304 [SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195573 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-24 17:41:41 +00:00
Juergen Ributzka
354362524a [weak vtables] Remove a bunch of weak vtables 
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 00:57:56 +00:00
Alexey Samsonov
b21ab43cfc Revert r194865 and r194874. 
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
  Base *foo = new Child();
  delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-18 09:31:53 +00:00
Juergen Ributzka
5a364c5561 [weak vtables] Remove a bunch of weak vtables 
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-15 22:34:48 +00:00
Roman Divacky
3e94418e85 Expand rotate instructions on sparcv9 as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194500 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-12 19:04:45 +00:00
Venkatraman Govindaraju
fcd5e86396 [SparcV9] Handle i64 <-> float conversions in sparcv9 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193957 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-03 12:28:40 +00:00
Venkatraman Govindaraju
5e45051e0e [Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193947 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-03 08:00:19 +00:00
Venkatraman Govindaraju
11cecbe1a0 [SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193941 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-03 05:59:07 +00:00
Roman Divacky
1d6d49fbb1 SparcV9 doesnt have rem instruction either. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193789 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 19:22:33 +00:00
Rafael Espindola
ffc7dca885 Add a helper getSymbol to AsmPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193627 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-29 17:07:16 +00:00
Rafael Espindola
06957f43f6 Add a MCAsmInfoELF class and factor some code into it. 
We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192760 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 01:34:32 +00:00
Venkatraman Govindaraju
3b73dea538 [Sparc] Disable tail call optimization for sparc64. 
This patch fixes PR17506.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192294 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-09 12:50:39 +00:00
NAKAMURA Takumi
26c46ba11c SparcJITInfo.cpp: Prune "default:" label to fix a warning. [-Wcovered-switch-default] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192179 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 10:29:09 +00:00
NAKAMURA Takumi
35741ad518 Prune trailing linefeeds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192178 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 10:29:03 +00:00
Venkatraman Govindaraju
38aceb8714 [Sparc] Implement JIT for SPARC. 
No new testcases. However, this patch makes all supported JIT testcases in 
test/ExecutionEngine  pass on Sparc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192176 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 07:15:22 +00:00
Venkatraman Govindaraju
3bd3419e86 [Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192160 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 02:50:29 +00:00
Rafael Espindola
ef8c4ca252 Remove getEHExceptionRegister and getEHHandlerRegister. 
They haven't been used for a long time. Patch by MathOnNapkins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192099 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 13:39:22 +00:00
Venkatraman Govindaraju
79c5e0c5ca [Sparc] Do not emit nop after fcmp* instruction with V9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192056 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-06 07:06:44 +00:00
Venkatraman Govindaraju
20b10abf4e [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64. 
This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192054 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-06 03:36:18 +00:00
Venkatraman Govindaraju
bb0ec9840b [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx. 
addx/subx does not modify conditional codes whereas addxcc/subxx does.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192053 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-06 02:11:10 +00:00
Venkatraman Govindaraju
a8147756d6 [Sparc] Use correct alignment while loading/storing fp128 values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192023 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-05 02:29:47 +00:00
Venkatraman Govindaraju
b648122c5f [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192015 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-05 00:31:41 +00:00
Venkatraman Govindaraju
1c9524b624 [Sparc] Correct the floating point conditional code mapping in GetOppositeBranchCondition(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192006 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-04 23:54:30 +00:00
Venkatraman Govindaraju
30ec8a3658 [Sparc] Implements exception handling in SPARC with DwarfCFI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191432 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-26 15:11:00 +00:00
Venkatraman Govindaraju
ff96efee98 [Sparc] Use correct instruction pattern for CMPri. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191180 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-22 18:54:54 +00:00
Venkatraman Govindaraju
0821c72f11 [Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191168 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-22 09:54:42 +00:00
Venkatraman Govindaraju
69ae8f1abd [Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191167 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-22 09:18:26 +00:00
Venkatraman Govindaraju
a432a97b62 [Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191166 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-22 08:51:55 +00:00
Tim Northover
3e84ad28d4 ISelDAG: spot chain cycles involving MachineNodes 
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.

Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.

This should fix PR15840.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-22 08:21:56 +00:00
Venkatraman Govindaraju
7d052f272d [Sparc] Add support for TLS in sparc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191164 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-22 06:48:52 +00:00
Venkatraman Govindaraju
ecd4965c13 [SPARC] Make functions with GLOBAL_OFFSET_TABLE access as non-leaf functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191160 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-22 01:40:24 +00:00
Venkatraman Govindaraju
c12c8d754d [Sparc] Emit .register directive to declare the use of global registers %g2, %g4, %g6 and %g7. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191158 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-22 00:42:30 +00:00
Venkatraman Govindaraju
20b5879e0e [Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191154 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-21 23:51:08 +00:00
Venkatraman Govindaraju
1b41835f02 [Sparc] Correctly handle call to functions with ReturnsTwice attribute. 
In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores
the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7)
using the stored %fp and register windows. However, this does not guarantee that the longjmp
will restore the registers, as they were when the setjmp was called. This is because these
registers may be clobbered after returning from setjmp, but before calling longjmp.

This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask.  



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190033 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-05 05:32:16 +00:00
Venkatraman Govindaraju
bf34f34642 [Sparc] Fix an assertion failure while lowering fcmp on long double. 
This assertion is triggered because an integer constant is created with wrong
  type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189948 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-04 15:15:20 +00:00
Venkatraman Govindaraju
75ddb2bb34 [Sparc] Add support for soft long double (fp128). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189780 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-03 04:11:59 +00:00
Venkatraman Govindaraju
6ee0857bd7 [Sparc] Implement spill and load for long double(f128) registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189768 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-02 18:32:45 +00:00
Venkatraman Govindaraju
2f17d0facf [Sparc] Add long double (f128) instructions to sparc backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189198 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-25 18:30:06 +00:00
Venkatraman Govindaraju
5ec8afa7cf [Sparc] Added V9's extra floating point registers and their aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189195 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-25 17:03:02 +00:00
Jakob Stoklund Olesen
b581261240 Use register masks on SPARC call instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189085 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-23 02:33:47 +00:00
Jakob Stoklund Olesen
d93969c32a Add an OtherPreserved field to the CalleeSaved TableGen class. 
This field specifies registers that are preserved across function calls,
but that should not be included in the generates SaveList array.

This can be used ot generate regmasks for architectures that save
registers through other means, like SPARC's register windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189084 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-23 02:25:47 +00:00
Venkatraman Govindaraju
e3b29fbc5f [Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188738 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-20 01:26:14 +00:00
Venkatraman Govindaraju
d8de58e24c [Sparc] Enable xword directive in sparcv9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188141 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-10 20:13:20 +00:00
NAKAMURA Takumi
8e1d64666f Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen. 
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187780 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 06:38:37 +00:00
Venkatraman Govindaraju
8717679c44 [Sparc] Rewrite MBB's live-in registers for leaf functions. Also, add 
register i7 as a live-in if current function's return address is taken.

This revision fixes PR16269.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187433 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-30 19:53:10 +00:00
Venkatraman Govindaraju
80cdaf35ab [Sparc] Use call's debugloc for the unimp instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187402 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-30 02:26:29 +00:00
Craig Topper
a0ec3f9b7b Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-14 04:42:23 +00:00
Venkatraman Govindaraju
eb4a55c949 [Sparc]: Add memory operands for the frame references in the storeRegToStackSlot 
and loadRegFromStackSlot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184935 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-26 12:40:16 +00:00
Chad Rosier
5b3fca50a0 The getRegForInlineAsmConstraint function should only accept MVT value types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-22 18:37:38 +00:00
Bill Wendling
ba54bca472 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 21:36:55 +00:00
David Blaikie
0187e7a9ba DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-16 20:34:27 +00:00
Venkatraman Govindaraju
1799921672 [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183613 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-08 15:32:59 +00:00
Jakob Stoklund Olesen
ec2aaad01b Remember the anyext patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183589 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 22:59:29 +00:00
Jakob Stoklund Olesen
7de1d327f1 Add missing zextloadi1 to i64 patterns. PR16721. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183587 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 22:55:05 +00:00
Bill Wendling
c1dcb8d654 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183565 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:35:25 +00:00
Roman Divacky
6ca5fd3f30 Fix a typo in asm string of BP* family of instructions. With this fix 
I am able to compile/assemble/link/run /bin/echo from FreeBSD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183537 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 17:46:57 +00:00
Venkatraman Govindaraju
01021a8b93 [Sparc]: Use cmp instruction instead of subcc to compare integers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183463 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 00:03:36 +00:00
Bill Wendling
6a2e7ac0b6 Cache the TargetLowering info object as a pointer. 
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-06 00:43:09 +00:00
Venkatraman Govindaraju
1e06bcbd63 Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183243 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 18:33:25 +00:00
Venkatraman Govindaraju
e7cbb792c9 Sparc: Add support for indirect branch and blockaddress in Sparc backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183094 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 05:58:33 +00:00
Venkatraman Govindaraju
85cc972a06 Sparc: When storing 0, use %g0 directly in the store instruction instead of 
using two instructions (sethi and store).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 00:21:54 +00:00
Venkatraman Govindaraju
65ca7aa57d Sparc: Combine add/or/sethi instruction with restore if possible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183088 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-02 21:48:17 +00:00
Venkatraman Govindaraju
dd48226b15 Sparc: Perform leaf procedure optimization by default 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183083 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-02 02:24:27 +00:00
Venkatraman Govindaraju
a0b34d6c4a Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183079 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-01 20:42:48 +00:00
Venkatraman Govindaraju
72ad17c48c [Sparc] Generate correct code for leaf functions with stack objects 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183067 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-01 04:51:18 +00:00
Ahmed Bougacha
23ed37a6b7 Make SubRegIndex size mandatory, following r183020. 
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-31 23:45:26 +00:00
Andrew Trick
6e0b2a0cb0 Order CALLSEQ_START and CALLSEQ_END nodes. 
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-29 22:03:55 +00:00
NAKAMURA Takumi
d1c180e030 SparcFrameLowering.cpp: Mark verifyLeafProcRegUse() as UNUSED. [-Wunused-function] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182850 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-29 12:10:42 +00:00
Venkatraman Govindaraju
5300869256 [Sparc] Add support for leaf functions in sparc backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182822 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-29 04:46:31 +00:00
Andrew Trick
ac6d9bec67 Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-25 02:42:55 +00:00
Jakob Stoklund Olesen
89f530ebbf Also expand 64-bit bitcasts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182229 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 01:01:43 +00:00
Jakob Stoklund Olesen
5e5b78ca36 Implement spill and fill of I64Regs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182228 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 00:53:25 +00:00
Jakob Stoklund Olesen
900622e099 Mark i64 SETCC as expand so it is turned into a SELECT_CC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182227 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 00:28:36 +00:00
Jakob Stoklund Olesen
634123e98d Don't use %g0 to materialize 0 directly. 
The wired physreg doesn't work on tied operands like on MOVXCC.

Add a README note to fix this later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182225 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-19 21:47:13 +00:00
Jakob Stoklund Olesen
60abcb786e Select i64 values with %icc conditions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182224 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-19 20:38:21 +00:00
Jakob Stoklund Olesen
51d46c36bc Add floating point selects on %xcc predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182222 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-19 20:33:11 +00:00
Jakob Stoklund Olesen
89db6732fb Implement SPselectfcc for i64 operands. 
Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182221 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-19 20:20:54 +00:00
Venkatraman Govindaraju
21886a495a [Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers. 
Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182219 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-19 20:07:20 +00:00
Jakob Stoklund Olesen
00ce0f6512 Handle i64 FrameIndex nodes in SPARC v9 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182216 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-19 19:14:24 +00:00
Venkatraman Govindaraju
a65d33760b [Sparc] Implements hasReservedCallFrame and hasFP. 
This is to generate correct framesetup code when the function
 has variable sized allocas.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182108 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 15:14:34 +00:00
Venkatraman Govindaraju
d6b4caf291 [Sparc] Prevent instructions that defines or uses %o7 to be in call's delay slot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182063 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-16 23:53:29 +00:00
Rafael Espindola
4a971705bc Remove the MachineMove class. 
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-13 01:16:13 +00:00
Rafael Espindola
6e53180db1 Remove unused argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 18:16:59 +00:00
Jakob Stoklund Olesen
ddb14ce76c Passing arguments to varags functions under the SPARC v9 ABI. 
Arguments after the fixed arguments never use the floating point
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179987 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-21 21:36:49 +00:00
Jakob Stoklund Olesen
2c6b5a8d33 Fix the SETHIimm pattern for 64-bit code. 
Don't ignore the high 32 bits of the immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179985 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-21 21:18:03 +00:00
Jakob Stoklund Olesen
da8768b2dd Compile varargs functions for SPARCv9. 
With a little help from the frontend, it looks like the standard va_*
intrinsics can do the job.

Also clean up an old bitcast hack in LowerVAARG that dealt with
unaligned double loads. Load SDNodes can specify an alignment now.

Still missing: Calling varargs functions with float arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179961 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 22:49:16 +00:00
Tim Northover
6265d5c91a Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 12:32:17 +00:00
Jakob Stoklund Olesen
ad36608499 Add 64-bit multiply and divide instructions for SPARC v9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179582 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-16 02:57:02 +00:00
Jakob Stoklund Olesen
d9f88da7b3 Use i32 for all SPARC shift amounts, even in 64-bit mode. 
Test case by llvm-stress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179477 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-14 05:48:50 +00:00
Jakob Stoklund Olesen
618eda7a60 Add support for the abs64 SPARC v9 code model. 
For when 16 TB just isn't enough.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179474 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-14 05:10:36 +00:00
Jakob Stoklund Olesen
87ce01739b Add support for the SPARC v9 abs44 code model. 
This is the default model for non-PIC 64-bit code. It supports
text+data+bss linked anywhere in the low 16 TB of the address space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179473 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-14 04:57:51 +00:00