6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-01 00:11:00 +00:00
Code Issues Projects Releases Wiki Activity
25,570 Commits 39 Branches 0 Tags 277 MiB
ec3c411de8
Commit Graph

6235 Commits

Author SHA1 Message Date
Evan Cheng
abb4d7829f New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29215 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-19 21:29:30 +00:00
Jim Laskey
c06fe8a5ac Do once flag never set to true. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29214 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-19 19:33:08 +00:00
Jim Laskey
613f1f83fd Tidy up a few things. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29213 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-19 19:32:06 +00:00
Jim Laskey
f19807cecb Reduce size of routine. Shrinks .o by 37%. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29210 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-19 17:53:32 +00:00
Chris Lattner
2a785500e0 bswapped load/store instructions are only availble in indexed addressing form. 
As such, use xoaddr (indexed only), not xaddr for address selection.

This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29208 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-19 17:15:36 +00:00
Jim Laskey
e29c2f5ca0 Bug#834 ICE (crash in code generator?) when building PCH . 
Missing Darwin check in Intel ATT ASM printer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29204 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-19 11:54:50 +00:00
Evan Cheng
1c96953d2d Misc. new entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29202 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-19 06:06:24 +00:00
Evan Cheng
1693e489e6 INC / DEC instructions have shorter code size than ADD32ri8, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29194 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-19 00:27:29 +00:00
Evan Cheng
e6f32034db Add code size to target instruction use it as the 3rd isel sorting tie-breaker. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29193 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-19 00:24:41 +00:00
Rafael Espindola
355746359e initial prologue and epilogue implementation. Need to define add and sub before finishing it :-) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29175 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-18 17:00:30 +00:00
Chris Lattner
303c695529 Make the implicit def instructions look like other instrs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29174 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-18 16:33:26 +00:00
Rafael Espindola
84b19be6ab skeleton of a lowerCall implementation for ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29159 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-16 01:02:57 +00:00
Chris Lattner
ba4733d901 Remove what little AIX support we have. It has never been tested and isn't 
complete.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29156 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-15 01:24:23 +00:00
Chris Lattner
a3b5939caa Add an out-of-line virtual method for X86DwarfWriter to give it a home. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29153 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-14 23:05:05 +00:00
Chris Lattner
518f9c7ad0 Add missing PPC64 extload/truncstores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29140 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-14 04:42:02 +00:00
Chris Lattner
1eeedaea59 Add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29139 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-14 04:07:29 +00:00
Chris Lattner
a606b70cf5 Another fix in the rotate encodings, needed when the first two operands are not 
the same.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29136 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-13 21:52:41 +00:00
Chris Lattner
45c04fc676 Print negative immediates as negative values instead of large constants 
when using the immshifted addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29130 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-12 23:24:02 +00:00
Chris Lattner
b2c0650ad3 Fix encoding of rotates, such as rldicl 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29128 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-12 22:08:13 +00:00
Chris Lattner
3bc8a765a9 Implement PPC64 relocations types 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29125 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-12 21:23:20 +00:00
Chris Lattner
3d6721a4a1 An overaggressive #ifdef allows a function to fall off the bottom of the 
function instead of returning a value.  This sometimes allowed the ppc32 jit
to be used in 64-bit mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29123 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-12 20:42:10 +00:00
Chris Lattner
6d3465793f Add information preventing several register class constraints from working. 
This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29118 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-12 16:59:49 +00:00
Chris Lattner
be6a039ad4 The PPC64 JIT needs register numbers to encode instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29114 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 20:53:55 +00:00
Evan Cheng
f7eb5d0b02 Emit inc / dec of registers as one byte instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29110 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 19:49:49 +00:00
Jim Laskey
16d42c6ac6 It was pointed out that DEBUG() is only available with -debug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29106 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 18:25:13 +00:00
Jim Laskey
e37fe9b3a1 Ensure that dump calls that are associated with asserts are removed from 
non-debug build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29105 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 17:58:07 +00:00
Rafael Espindola
a4e64359aa add the memri memory operand 
this makes it possible for ldr instructions with non-zero immediate


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29103 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 11:36:48 +00:00
Chris Lattner
f4dff84c86 Implement the inline asm 'A' constraint. This implements PR825 and 
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29101 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 02:54:03 +00:00
Chris Lattner
804e067042 In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29096 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 00:48:23 +00:00
Evan Cheng
20adf47dbc New entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29091 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-10 21:42:16 +00:00
Evan Cheng
1e60c098cc Fixed stack objects do not specify alignments, but their offsets are known. 
Use that information when doing the transformation to merge multiple loads
into a 128-bit load.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29090 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-10 21:37:44 +00:00
Chris Lattner
d998938459 Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps 
into i16/i32 load/stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29089 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-10 20:56:58 +00:00
Chris Lattner
5c5f4ca6f1 Mark internal function static 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29085 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-10 19:53:12 +00:00
Rafael Espindola
aefe14299a create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29079 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-10 01:41:35 +00:00
Evan Cheng
206ee9d86c X86 target specific DAG combine: turn build_vector (load x), (load x+4), 
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).

e.g.

__m128 test(float a, float b, float c, float d) {
  return _mm_set_ps(d, c, b, a);
}

_test:
        movups 4(%esp), %xmm0
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29042 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-07 08:33:52 +00:00
Chris Lattner
90ac1c0775 Undisable ppc64 jit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29011 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-06 17:10:42 +00:00
Evan Cheng
152ed05353 Added option -code-model to set code model (only used in 64-bit) mode. Valid 
values include small, kernel, medium, large, and default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29009 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-06 01:53:36 +00:00
Evan Cheng
60c07e1aea Reorg. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28999 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-05 22:17:51 +00:00
Evan Cheng
507b0aa062 Fix JIT on non MacOS X i386 systems. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28992 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-05 07:09:13 +00:00
Andrew Lenharth
441a57041d These are already implemented 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28990 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-03 18:00:29 +00:00
Andrew Lenharth
78c252c93d 0 offsets for memory operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28989 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-03 17:57:34 +00:00
Evan Cheng
775ff18257 Should just use xorps to clear XMM registers for all data types. pxor is also one byte longer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28984 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-29 18:04:54 +00:00
Evan Cheng
be33dd95d8 Let X86CompilationCallback pass previous frame and return address to X86CompilationCallback2. Remove alloca hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28982 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-29 01:48:36 +00:00
Evan Cheng
09c545790d Add shift and rotate by 1 instructions / patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28980 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-29 00:36:51 +00:00
Evan Cheng
a8e83ec8c3 Always use xorps to clear XMM registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28979 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-29 00:34:23 +00:00
Evan Cheng
d3f6981174 Move .literal4 and .literal8 support into AsmPrinter.cpp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28978 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-29 00:33:06 +00:00
Chris Lattner
2c79de8018 Hide x86 symbols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28976 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-28 23:27:49 +00:00
Chris Lattner
9525528a7d Use hidden visibility to make symbols in an anonymous namespace get 
dropped.  This shrinks libllvmgcc.dylib another 67K


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28975 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-28 23:17:24 +00:00
Chris Lattner
2a41a98fb7 shrink libllvmgcc.dylib another 25K 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28971 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-28 22:00:36 +00:00
Evan Cheng
33c36f306a Doh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28963 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-28 17:56:43 +00:00