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6051 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
f12ad66741 Shrink down SSE3 code by more multiclass refactoring 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107448 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 23:10:49 +00:00
Bruno Cardoso Lopes
944facac2e Shrink down SSE3 code by some multiclass refactoring - 1st part 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107438 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 22:33:18 +00:00
Bruno Cardoso Lopes
c6fcdeb8f9 Move SSE3 Move patterns to a more appropriate section 
Add AVX SSE3 packed horizontal and & sub instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107405 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
7144821c61 Add AVX SSE3 packed addsub instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 17:08:18 +00:00
Dan Gohman
20d4be151b Enable on-demand fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:58:57 +00:00
Dan Gohman
abd1d859b3 Fix X86FastISel's add folding to actually work, and not fall back 
to SelectionDAG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:58:21 +00:00
Bruno Cardoso Lopes
79b634c244 Add AVX SSE3 replicate and convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:33:39 +00:00
Dan Gohman
5c87bf64d6 Teach X86FastISel to fold constant offsets and scaled indices in 
the same address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 02:27:15 +00:00
Bruno Cardoso Lopes
6596a62076 - Add AVX SSE2 Move doubleword and quadword instructions. 
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
7ac7ed868a Move MOVD/MODQ code around, creating sections for each of them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107308 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:49:10 +00:00
Bruno Cardoso Lopes
e26f14d150 Add AVX SSE2 mask creation and conditional store instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
130acd15fc Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107300 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 18:06:01 +00:00
Bruno Cardoso Lopes
1e4b723b20 Add AVX SSE2 packed integer extract/insert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 17:03:03 +00:00
Gabor Greif
e1c2b9cc3d use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107280 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 13:03:37 +00:00
Bruno Cardoso Lopes
876085dcfa Add AVX SSE2 integer unpack instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107246 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
d252fec7ae Add AVX SSE2 packed integer shuffle instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107245 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
555bea62dd Small refactoring of SSE2 packed integer shuffle instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 03:29:36 +00:00
Bruno Cardoso Lopes
6d5d2b5de2 Add AVX SSE2 pack with saturation integer instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107241 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c0ea94a37c Add AVX SSE2 integer packed compare instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107240 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
5a3a476750 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
6c9fa43716 Add *several* AVX integer packed binop instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107225 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes
2c818072cc Move SSE2 Packed Integer instructions around, and create specific sections for each of them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107211 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 22:12:16 +00:00
Bruno Cardoso Lopes
8d3cebca8e Add AVX Move Aligned/Unaligned packed integers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 21:25:12 +00:00
Bruno Cardoso Lopes
147b7cad2f Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes
721ef73d88 Add AVX non-temporal stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107178 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
de173ca1fb Move non-temporal movs to their own section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 17:42:37 +00:00
Bruno Cardoso Lopes
ea86423cbd Add sqrt, rsqrt and rcp AVX instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107166 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 17:26:30 +00:00
Duncan Sands
78337b4d4d Remove pointless and unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107130 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 12:48:49 +00:00
Bruno Cardoso Lopes
b22dc70a5c Refactoring of arithmetic instruction classes with unary operator 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107116 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 01:33:09 +00:00
Bruno Cardoso Lopes
4548260ab5 Described the missing AVX forms of SSE2 convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107108 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 00:36:02 +00:00
Bill Wendling
c25ccf85e5 Reduce indentation via early exit. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-28 21:08:32 +00:00
Gabor Greif
1cfe44a460 use ArgOperand API 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106944 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 11:51:52 +00:00
Jakob Stoklund Olesen
4f5d84e4ad When creating X86 MUL8 and DIV8 instructions, make sure we don't produce 
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.

Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).

This fixes PR7312.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106934 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-26 00:39:23 +00:00
Bruno Cardoso Lopes
bdffc16d65 Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes
161476ec34 Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes
95325b08a3 revert this now, it's using avx instead of sse :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106906 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes
544a95d716 Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106896 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 22:27:51 +00:00
Dale Johannesen
1784d160e4 The hasMemory argument is irrelevant to how the argument 
for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:55:36 +00:00
Dan Gohman
ca5b8553ea pcmpeqd and friends are Commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106886 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 21:05:35 +00:00
Bill Wendling
730c07e50d - Reapply r106066 now that the bzip2 build regression has been fixed. 
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106880 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:48:10 +00:00
Bruno Cardoso Lopes
39afa908de Move the last piece of SSE2 convert instructions to the Convert Instructions section 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106877 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:29:27 +00:00
Bruno Cardoso Lopes
6560ed35b4 More SSE refactoring, this time with different types of MOVs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 20:22:12 +00:00
Bruno Cardoso Lopes
0491e132fc Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106867 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 18:06:22 +00:00
Bruno Cardoso Lopes
a0ae87fd5d Add some AVX convert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
8b94297727 Refactoring of SSE convert intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 23:37:07 +00:00
Bruno Cardoso Lopes
f241b26792 Refactoring of SSE conversion instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 22:22:21 +00:00
Bruno Cardoso Lopes
e0c437333e Refactor SSE cmp intrinsics and declare the same for AVX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106796 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 22:04:40 +00:00
Bruno Cardoso Lopes
788184365a - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}. 
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 20:48:23 +00:00
Dale Johannesen
e5ff9ef195 Disallow matching "i" constraint to symbol addresses when 
address requires a register or secondary load to compute
(most PIC modes).  This improves "g" constraint handling.  8015842.

The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously.  Fixed to use Linux x86-64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106779 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 20:14:51 +00:00
Dan Gohman
4e39e9da0f Reapply r106634, now that the bug it exposed is fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 14:30:44 +00:00