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f1d0f7781e
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6024 Commits

Author SHA1 Message Date
Craig Topper
f1d0f7781e Prune some includes and forward declarations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153429 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-26 06:58:25 +00:00
Craig Topper
0e5233a9e5 Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153422 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-26 00:45:15 +00:00
Craig Topper
acf2077ca4 Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153421 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-25 23:49:58 +00:00
Craig Topper
805853bc59 Prune some includes and forward declarations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153415 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-25 18:10:17 +00:00
Jim Grosbach
7a46525056 ARM tidy up ARMConstantIsland.cpp. 
No functional change, just tidy up the code and nomenclature a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153347 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-23 23:07:03 +00:00
Silviu Baranga
6fe310e155 Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-22 14:14:49 +00:00
Silviu Baranga
b7c2ed6664 Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-22 13:24:43 +00:00
Silviu Baranga
a0c48eb8f6 Added soft fail cases for the disassembler when decoding MUL instructions on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-22 13:14:39 +00:00
Kevin Enderby
f0586f08df Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test 
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-21 20:54:32 +00:00
Evan Cheng
03a1852538 Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and t2PseudoExpand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153135 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 21:28:05 +00:00
Matt Beaumont-Gay
98a27acc6b remove unused variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153116 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 19:52:05 +00:00
Bob Wilson
aaa1e2f820 Require a base pointer for stack realignment when SP may vary dynamically. 
ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects
but not for stack adjustments around calls.  Use hasReservedCallFrame() to
check for both.  The hasBasePointer function was already correctly checking
both conditions, so the effect of this was that a base pointer would be used
without checking whether the base pointer register could be reserved. I don't
have a small testcase for this.

<rdar://problem/11075906>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153110 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 19:28:25 +00:00
Bob Wilson
055a8127c9 Remove some redundant checks. 
ARMFrameLowering::hasReservedCallFrame is already checking for variable
sized objects, so there's no point in checking it twice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153109 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 19:28:22 +00:00
Kevin Enderby
9f2e160f7a Fix assembling ARM vst2 instructions with double-spaced registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 17:41:51 +00:00
Jim Grosbach
07cdd80ccc ARM non-scattered MachO relocations for movw/movt. 
Needed when building -mdynamic-no-pic code.

rdar://10459256

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153097 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 17:25:45 +00:00
Silviu Baranga
5c062ad926 The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 15:54:56 +00:00
Richard Barton
db9ca59759 Test Commit - add a newline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153083 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 10:50:35 +00:00
Jim Grosbach
fa1f74470a ARM branch relaxation for unconditional t1 branches. 
rdar://11059157

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153055 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 21:32:32 +00:00
Jim Grosbach
ceee984302 ARM assembly, accept optional '#' on lane index number. 
rdar://11057160

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153053 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 20:39:53 +00:00
Anton Korobeynikov
2d7ea04e28 Perform mul combine when multiplying wiht negative constants. 
Patch by Weiming Zhao!
This fixes PR12212


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 19:19:50 +00:00
Craig Topper
c1f6f42049 Reorder includes to match coding standards. Fix an issue or two exposed by that. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 07:33:42 +00:00
Bill Wendling
5aeff3171c Check if we can handle the arguments of a call (and therefore the call) in 
fast-isel before emitting code. If the program bails after code was emitted,
then it could lead to the stack being adjusted more than once (two
CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This
leads to general badness and gnashing of teeth.
<rdar://problem/11050630>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152959 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 23:11:07 +00:00
Jim Grosbach
11d5dc3d50 ARM fix silly typo in optional operand alias. 
rdar://11065671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152954 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 22:18:29 +00:00
Jim Grosbach
66cba302f0 ARM divided syntax fmrx/fmxr mnemonics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152946 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 21:06:13 +00:00
Jim Grosbach
be7cf2b377 ARM ldm/stm register lists can be out of order. 
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.

rdar://11064740

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 20:48:38 +00:00
Jim Grosbach
213d2e7dc3 ARM optional operand on MRC/MCR assembly instructions. 
rdar://11058464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 00:45:58 +00:00
Jim Grosbach
9426ac7b57 ARM vmrs system registers mvfr0 and mvfr1 handling. 
rdar://11058464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 00:27:18 +00:00
Jim Grosbach
89eaa6f554 Remove inadvertant commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152870 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 23:00:30 +00:00
Chad Rosier
0ac754f6f4 [fast-isel] Address Eli's comments for r152847. Specifically, add a test case 
and still allow immediate encoding, just not with cmn.
rdar://11038907


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152869 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 22:54:20 +00:00
Chad Rosier
530b19b702 [fast-isel] Don't try to encode LONG_MIN using cmn instructions. 
rdar://11038907


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152847 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 21:40:23 +00:00
Jim Grosbach
b84ad4aa7d ARM case-insensitive checking for APSR_nzcv. 
rdar://11056591

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 21:34:14 +00:00
Jim Grosbach
6357caec78 ARM aliases for pre-unified syntax fcmpz[sd] mnemonics. 
rdar://11056647

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152834 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 20:48:18 +00:00
Lang Hames
45b5f88938 Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on 
register allocation by allowing all 32 D-registers to be used. Patch by Cameron
Zwarich.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152824 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 18:49:02 +00:00
Kristof Beyls
8a6bcc3722 Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 17:50:29 +00:00
Bob Wilson
2bbb22b8ef Switch to unified syntax for VFP instructions in inline assembly. 
<rdar://problem/11024696>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152548 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-12 06:15:36 +00:00
Craig Topper
c5eaae4e9b Convert more static tables of registers used by calling convention to uint16_t to reduce space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-11 07:57:25 +00:00
Craig Topper
b78ca42384 Use uint16_t to store registers and opcode in static tables in the target specific backends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-11 07:16:55 +00:00
Craig Topper
fac2598149 Use uint16_t to store instruction implicit uses and defs. Reduces static data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 08:22:45 +00:00
Jim Grosbach
fd03ccdded ARM don't use MCRelaxAll, as it's not safe on ARM. 
The ARM code generator makes aggressive assumptions about the encodings
being selected for branches which MCRelaxAll invalidates.

rdar://11006355


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152268 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 00:07:52 +00:00
Chad Rosier
44c98b7114 [fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point 
condition flags to CPSR.  This allows us to simplify SelectCmp.
Patch by Zonr Chang <zonr.xchg@gmail.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152243 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-07 20:59:26 +00:00
Jim Grosbach
05d88f4fea ARM pre-v6 assembly parsing for umull/smull. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152188 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-07 01:09:17 +00:00
Jim Grosbach
0104dd3ffd ARM pre-v6 alias for 'nop' to 'mov r0, r0' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152185 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-07 00:52:41 +00:00
Jim Grosbach
ff3164a189 Tidy up. Remove dead code that slipped into previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152184 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-07 00:52:39 +00:00
Jim Grosbach
4d0983a4d7 ARM more NEON VLD/VST composite physical register refactoring. 
Register pair, all lanes subscripting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 23:10:38 +00:00
Jim Grosbach
c0fc450f07 ARM refactor more NEON VLD/VST instructions to use composite physregs 
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 22:01:44 +00:00
Jim Grosbach
bde1b2a5a8 Tidy up. Kill some dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152131 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 18:59:19 +00:00
Jakob Stoklund Olesen
14f87e01ca Allow the same types in DPair as in QPR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152129 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 18:44:11 +00:00
Kevin Enderby
158c8a49c2 Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 18:33:12 +00:00
Jakob Stoklund Olesen
3247af2949 Add <imp-def> operands when reloading into physregs. 
When an instruction only writes sub-registers, it is still necessary to
add an <imp-def> operand for the super-register.  When reloading into a
virtual register, rewriting will add the operand, but when loading
directly into a virtual register, the <imp-def> operand is still
necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152095 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 02:48:17 +00:00
Lang Hames
4f92b5e616 Split fpscr into two registers: FPSCR and FPSCR_NZCV. 
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 00:19:55 +00:00