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727 Commits

Author SHA1 Message Date
Rafael Espindola
817e7fdb8b implement SRL and MUL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30262 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 19:24:19 +00:00
Rafael Espindola
7cca7c5317 partial implementation of the ARM Addressing Mode 1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30252 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 17:25:40 +00:00
Rafael Espindola
0a200600e7 implement shl and sra 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30191 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-08 17:36:23 +00:00
Rafael Espindola
4e30764d55 add the eor (xor) instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30189 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-08 16:59:47 +00:00
Rafael Espindola
5c2aa0a4d8 implement unconditional branches 
fix select.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30186 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-08 12:47:03 +00:00
Rafael Espindola
b52b54d4af add the orr instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30125 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-06 18:03:12 +00:00
Rafael Espindola
cdda88cd12 add the "eq" condition code 
implement a movcond instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29857 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-24 17:19:08 +00:00
Rafael Espindola
6f602de3b6 create a generic bcond instruction that has a conditional code argument 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29856 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-24 16:13:15 +00:00
Rafael Espindola
687bc49d1a initial support for branches 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-24 13:45:55 +00:00
Rafael Espindola
3c000bf817 initial support for select 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29802 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-21 22:00:32 +00:00
Rafael Espindola
a5dfc835d4 add the and instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29793 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-21 13:58:59 +00:00
Rafael Espindola
f3a335cedf add a "load effective address" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29748 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-17 17:09:40 +00:00
Rafael Espindola
ec46ea34dc Declare the callee saved regs 
Remove the hard coded store and load of the link register
Implement ARMFrameInfo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29727 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-16 14:43:33 +00:00
Evan Cheng
bb7b844bec CALLSEQ_* produces chain even if that's not needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29603 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-11 09:03:33 +00:00
Rafael Espindola
46adf8119d change the addressing mode of the str instruction to reg+imm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29571 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-08 20:35:03 +00:00
Rafael Espindola
f4fda80403 add and use ARMISD::RET_FLAG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29499 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-03 17:02:20 +00:00
Rafael Espindola
1ed3af11b5 start comments with # 
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29451 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-01 18:53:10 +00:00
Rafael Espindola
44819cb20a implemented sub 
correctly update the stack pointer in the prologue and epilogue


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29244 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-21 12:26:16 +00:00
Rafael Espindola
355746359e initial prologue and epilogue implementation. Need to define add and sub before finishing it :-) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29175 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-18 17:00:30 +00:00
Rafael Espindola
84b19be6ab skeleton of a lowerCall implementation for ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29159 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-16 01:02:57 +00:00
Rafael Espindola
a4e64359aa add the memri memory operand 
this makes it possible for ldr instructions with non-zero immediate


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29103 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-11 11:36:48 +00:00
Rafael Espindola
aefe14299a create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29079 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-07-10 01:41:35 +00:00
Rafael Espindola
58421d7d08 initial implementation of ARMRegisterInfo::eliminateFrameIndex 
fixes test/Regression/CodeGen/ARM/ret_arg5.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-18 00:08:07 +00:00
Rafael Espindola
85ede37ca9 Expand ret into "CopyToReg;BRIND" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28559 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-30 17:33:19 +00:00
Rafael Espindola
a1334cdfb2 On ARM, alignment is in bits 
Add lr as a hard coded operand of bx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28494 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-26 10:56:17 +00:00
Rafael Espindola
dc124a234a implement movri 
add a stub LowerFORMAL_ARGUMENTS


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28388 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-18 21:45:49 +00:00
Rafael Espindola
7bc59bc395 added a skeleton of the ARM backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-14 22:18:28 +00:00