* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes
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* Removed instruction scheduling as it is too slow to run in a JIT environment
* Removed other passes because they aren't necessary and can slow JIT down
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6652 91177308-0d34-0410-b5e6-96231b3b80d8
The JIT is designed to code-generate a function at-a-time. That means that any
pass can only make local changes to its function. Period.
Because the Sparc PreSelection pass claims to be a BasicBlock pass while adding
globals to the Module, it cannot be run with the other passes, because by this
time, the globals have been output already by the JIT, and the addresses of any
globals appearing AFTER this point are not recognized.
However, the PreSelection pass is a requirement for correctness in the Sparc
codegen path, so it MUST be run.
::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT :::
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6650 91177308-0d34-0410-b5e6-96231b3b80d8
This avoid generating a register to hold C, which in turn speeds up the
register allocator by a lot: ~9% on 164.gzip and ~17% on 256.bzip2. This
also speeds up other passes. This also speeds up execution of the program
marginally, and makes the asm much easier to read. :)
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Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and
expect %fsr as the parameter in assembly. They are disabled (since not used)
until an encoding, both for code generation and output, is chosen.
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Update file comment to contain a bunch of the overview mapping-info
documentation previously buried within the file.
Remove some unnecessary include/using stmts.
Rename pass to MappingInfoCollector.
Rewrite a lot of it so it doesn't use global instance variables and so
it outputs into MappingInfo objects and then dumps those out, instead of going
straight to an assembly file.
Change name of factory to getMappingInfoCollector.
Fold prologue & epilogue writers into MappingInfo methods.
lib/Target/Sparc/FInfo.cpp:
Correct file comment to reflect above change
lib/Target/Sparc/Sparc.cpp:
Change name of factory to getMappingInfoCollector.
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in Emitter.cpp, just convert the Sparc version of the constant pool into
what's already supported and inter-operate.
* Implemented a first pass at lazy function resolution in the JITResolver. That
required adding a SparcV9CodeEmitter pointer to simplify generating
bit-patterns of the instructions.
* SparcV9CodeEmitter now creates and destroys static TheJITResolver, which makes
sense because the SparcV9CodeEmitter is the only user of TheJITResolver, and
lives for the entire duration of the JIT (via PassManager which lives in VM).
* Changed all return values in the JITResolver to uint64_t because of the 64-bit
Sparc architecture.
* Added a new version of getting the value of a GlobalValue in the
SparcV9CodeEmitter, which now works for already-generated functions (JITted or
library functions).
* Removed little-used and unused functions, cleaning up the internal view of the
SparcV9CodeEmitter.
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laid out closer to the VM so that calls to library functions (e.g. puts()) and
callback (e.g. JITResolver::CompilationCallback) fit into 30 bits of the call
instruction.
* Abort if architecture is not yet supported (not X86 or Sparc) because it
likely requires a different set of parameters to mmap() .
* Stop using hard-coded values for page size; use sysconf(_SC_PAGESIZE) instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6610 91177308-0d34-0410-b5e6-96231b3b80d8
