Commit Graph

826 Commits

Author SHA1 Message Date
Misha Brukman
f86aaa8eb7 Merged in tools/lli/JIT/SparcEmitter.cpp, coupled with the JITResolver taken
from lib/Target/X86/X86CodeEmitter.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6530 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02 04:12:39 +00:00
Brian Gaeke
c3eaa89933 Deal with %lo/%lm/%hm/%hh flags in getMachineOpValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6522 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02 02:13:26 +00:00
Brian Gaeke
76e3dc798b Make the .inc file depend on $(TBLGEN), so that changes to TableGen followed
by a re-link of TableGen will notify Make to rebuild the .inc file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6512 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-01 04:52:51 +00:00
Anand Shukla
55afc33882 Add map info for arguments to call (copies)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6503 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-01 02:48:23 +00:00
Vikram S. Adve
2263df029a Renamed a variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6472 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 07:43:41 +00:00
Vikram S. Adve
5cdb12f958 Minor changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6470 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 07:41:54 +00:00
Vikram S. Adve
f3d3ca18b5 Added MachineCodeForInstruction object as an argument to
TmpInstruction constructors because every TmpInstruction object has
to be registered with a MachineCodeForInstruction to prevent leaks.
This simplifies the user's code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6469 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 07:41:24 +00:00
Vikram S. Adve
7952d6088e Changes to allow explicit physical register arguments that have been
preallocated.  While reg-to-reg dependences were already handled, this
change required new code for adding edges to/from call instructions.
This was part of the extensive changes to the way code generation occurs
for function call arguments and return values.
See log for CodeGen/PhyRegAlloc.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6467 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 07:37:05 +00:00
Vikram S. Adve
9635867d6f Several bug fixes: globals in call operands were not being pulled out;
globals in some other places may not have been pulled out either;
globals in phi operands were being put just before the phi instead of
in the predecessor basic blocks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6466 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 07:34:57 +00:00
Vikram S. Adve
d0d06ad4f3 Extensive changes to the way code generation occurs for function
call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6465 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 07:32:01 +00:00
Vikram S. Adve
af9fd51da2 Reverting previous beautification changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6464 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 07:27:17 +00:00
Misha Brukman
dcbe712841 Removed useless code -- the byte order of output code is correct as is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6462 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 06:26:06 +00:00
Misha Brukman
33cc12319c The 'rd' register is consistently mentioned last in instruction definitions.
Created new classes from which instructions inherit their ordering of fields.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6461 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 06:25:19 +00:00
Misha Brukman
286903909f * Put back into action SLL/SRL/SRA{r,i}6 instructions
* Fixed page numbers referring to the Sparc manual


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6460 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 06:24:29 +00:00
Misha Brukman
b3fabe0c83 Code beautification, no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6459 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 06:22:37 +00:00
Misha Brukman
b17343d81e Enabling some of these passes causes lli to break
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6457 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 04:23:04 +00:00
Misha Brukman
c89d256e95 The actual order of parameters in a 2-reg-immediate assembly instructions is
"rs1, imm, rd": most importantly, rd goes last.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6456 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 04:22:26 +00:00
Misha Brukman
88ba25444c When converting virtual registers to immediate constants, change the opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6452 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 20:36:27 +00:00
Misha Brukman
a9f7f6e25d Added:
* ability to save BasicBlock references to be resolved later
* register remappings from the enum values to the real hardware numbers


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6449 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 20:17:33 +00:00
Misha Brukman
f3453d1695 Fixed the namespace to match SparcInternals.h; added notes on some missing
sections of instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6448 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 20:15:59 +00:00
Misha Brukman
d3d97be4d1 The register types need to be visible outside of the class to be useful.
For one, converting register numbers based on class in the code emitter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6447 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 20:12:42 +00:00
Misha Brukman
7b647942ef Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes.
Code beautification for the rest of the code: changed layout to match the rest
of the code base.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6446 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 20:11:56 +00:00
Misha Brukman
d1ef7a816e Make LLI behave just like LLC with regard to the compile passes it uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6444 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 20:00:13 +00:00
Misha Brukman
ed36fd8da6 Made the register and immediate versions of instructions consecutive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6439 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 19:14:01 +00:00
Misha Brukman
9b03633265 Because the format of the shift instructions is `shift r, shcnt, r', the
instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.

Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.

The other changes are just elimination of unnecessary spaces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6437 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 18:06:10 +00:00
Brian Gaeke
9604416192 Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
 their fields were totally screwed up. This seems to fix the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6429 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 08:02:14 +00:00
Guochun Shi
139f0c279d so far everything compiles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6423 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 00:17:09 +00:00
Misha Brukman
6cf7f6d43d Since there is now another derived .inc file, ignore them all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6411 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29 20:15:27 +00:00
Misha Brukman
6567975ec5 Use an absolute path to TableGen because not everyone (e.g. automatic tester)
has their path set up by this point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6410 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29 20:09:56 +00:00
Misha Brukman
3f7b58bca0 When TableGen finds an error in the SparcV9.td file, it exits with a non-zero
exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only
much later, produces a link error because the key function that TableGen creates
isn't found.

Using a temporary file in the middle forces a good .INC file to be generated by
TableGen, and it will keep trying until you fix the input file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6392 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29 05:29:22 +00:00
Misha Brukman
25f36306ff Fixed to use the correct format of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6390 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29 04:53:56 +00:00
Misha Brukman
983d1d3835 This should work better with re-generating the SparcV9CodeEmitter.inc file.
Also, added a rule to delete the generated .inc file on `make clean'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6389 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29 03:32:49 +00:00
Misha Brukman
dafa504341 * Broke up SparcV9.td into separate files as it was getting unmanageable
* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6388 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29 03:31:43 +00:00
Misha Brukman
8996f44f7a Fixed ordering of elements in instructions: although the binary instructions
list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.

Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6384 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-28 17:49:29 +00:00
Brian Gaeke
e57a529fca Add dependency to make TableGen rule fire.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6383 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-28 17:41:09 +00:00
Misha Brukman
f2ef76782d Fixed an error preventing compilation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6381 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:48:28 +00:00
Misha Brukman
3c4cf15f76 Added the 'r' and 'i' annotations to instructions as their opcode names have
changed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6380 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:44:44 +00:00
Misha Brukman
0d60345dcf Keep track of the current BasicBlock being processed so that a referencing
MachineInstr can later be patched up correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6378 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:41:44 +00:00
Misha Brukman
af6f38e424 Added 'r' and 'i' annotations to instructions as SparcInstr.def has changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6377 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:40:34 +00:00
Misha Brukman
b5b9adc5a0 Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
Non-obvious change: since I have changed ST and STD to be STF and STDF to
(a) closer resemble their name (NOT assembly text) in the Sparc manual, and
(b) clearly specify that they they are floating-point opcodes,
I made the same changes in this file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6376 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:39:01 +00:00
Misha Brukman
91aee47a1b Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
Here I had to make one non-trivial change: add a function to get a version of
the opcode that takes an immediate, given an opcode that takes all registers.

This is required because sometimes it is not known at construction time which
opcode is used because opcodes are passed around between functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6375 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:37:00 +00:00
Misha Brukman
71ed1c997b Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6373 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:35:43 +00:00
Misha Brukman
24b22a18ec Added entries for each of the instructions with annotations ('r' or 'i').
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6372 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:33:39 +00:00
Misha Brukman
6ddd9d87a7 One of the first major changes to make the work of JITting easier: adding
annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.

This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.

As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6371 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:32:38 +00:00
Misha Brukman
86172ab3d6 * Allow passing in an unsigned configuration to allocateSparcTargetMachine()
a default value is set in the header file.
* Fixed some code layout to make it more consistent with the rest of codebase
* Added addPassesToJITCompile() with relevant passes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6369 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:24:48 +00:00
Misha Brukman
51aa21c702 Moved generation of the SparcV9CodeEmitter.inc file higher in the Makefile so
that Makefile.common would see it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6367 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:04:38 +00:00
Misha Brukman
79caf1fe26 Add prototypes to add passes to JIT compilation and code emission.
Also, added annotations to how instructions are modified (reg/imm operands).
Added prototype for adding register numbers to values pass for interfacing with
the target-independent register allocators in the JIT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6366 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:01:10 +00:00
Misha Brukman
0cc640e6c8 Broke out class definition from SparcV9CodeEmitter, and added ability to take a
MachineCodeEmitter to make a pass-through debugger -- output to memory and to
std::cerr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6363 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 21:45:05 +00:00
Misha Brukman
3de36f5309 SparcV9CodeEmitter.cpp is a part of the Sparc code emitter. The main function
that assembles instructions is generated via TableGen (and hence must be built
before building this directory, but that's already the case in the top-level
Makefile).

Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc',
which is included by SparcV9CodeEmitter.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6357 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 20:07:58 +00:00
Misha Brukman
998800cb87 Added definitions for a bunch of floating-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6356 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 20:03:29 +00:00