Commit Graph

7847 Commits

Author SHA1 Message Date
Vincent Lejeune
fd49dac48f R600: Fix JUMP handling so that MachineInstr verification can occur
This allows R600 Target to use the newly created -verify-misched llc flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176819 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11 18:15:06 +00:00
NAKAMURA Takumi
0087f3c6fb llvm/test/CodeGen/X86/handle-move.ll: Mark it as XFAIL:cygming. Investigating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11 16:30:26 +00:00
NAKAMURA Takumi
be15cdda54 Suppress atomic(32|64).ll as XFAIL on win32 codegen. Investigating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11 08:39:48 +00:00
Lang Hames
14d852362c Remove date from test case file name. The PR number provides a unique ID already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176796 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11 03:49:23 +00:00
Lang Hames
f793de7a23 Don't glue users to extract_subreg when selecting the llvm.arm.ldrexd
intrinsic - it can cause impossible-to-schedule subgraphs to be
introduced.

PR15053.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-09 22:56:09 +00:00
Benjamin Kramer
1cb47b9afe Test case hygiene.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176772 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-09 18:25:40 +00:00
Jan Wen Voung
fa785cb22d Disable statistics on Release builds and move tests that depend on -stats.
Summary:
Statistics are still available in Release+Asserts (any +Asserts builds),
and stats can also be turned on with LLVM_ENABLE_STATS.

Move some of the FastISel stats that were moved under DEBUG()
back out of DEBUG(), since stats are disabled across the board now.

Many tests depend on grepping "-stats" output.  Move those into
a orig_dir/Stats/. so that they can be marked as unsupported
when building without statistics.

Differential Revision: http://llvm-reviews.chandlerc.com/D486

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 22:56:31 +00:00
Jakob Stoklund Olesen
778ef97c76 Rewrite the physreg part of findLastUseBefore().
To find the last use of a register unit, start from the bottom and scan
upwards until a user is found.

<rdar://problem/13353090>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176706 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 18:08:57 +00:00
Tom Stellard
7893d29c62 R600: Optimize another selectcc case
fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
     selectcc x, y, a, b, cc

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176700 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 15:37:11 +00:00
Tom Stellard
1454cb86be R600: Improve custom lowering of select_cc
Two changes:
1. Prefer SET* instructions when possible
2. Handle the CND*_INT case with floating-point args

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 15:37:09 +00:00
Tom Stellard
d416505906 R600: Change operation action from Custom to Expand for BR_CC
Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176698 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 15:37:07 +00:00
Tom Stellard
9c6b0b0cce R600: Change operation action from Custom to Expand for SETCC
Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176697 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 15:37:05 +00:00
Tom Stellard
03abf2f2aa LegalizeDAG: Respect the result of TLI.getBooleanContents() when expanding SETCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176695 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 15:37:02 +00:00
Vincent Lejeune
b59f8685e4 R600: Change addresspace in fold-kcache.ll
AddressSpace definition has changed in a previous commit, reflect it
to avoid false failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 15:34:07 +00:00
Tim Northover
fa3dc9ffbb AArch64: specify full triple in test as only Linux works for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176692 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 15:27:30 +00:00
Christian Konig
93a9840c0a R600/SI: adjust test to recent changes
Signed-off-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176691 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 14:44:00 +00:00
Jyotsna Verma
86df21767a Hexagon: Add patterns for zero extended loads from i1->i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 14:15:15 +00:00
Tim Northover
69fe178f77 AArch64: expand sincos operations, we don't support them.
Patch based on Mans Rullgard's.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176688 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 13:55:07 +00:00
David Blaikie
6a66500cbe Another test fix for r176671.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176679 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 02:27:40 +00:00
David Blaikie
3f9fa3b6bb Couple of test fixes for r176671.
Not sure why these aren't failing on my linux machine, but this should cover
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176678 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 02:26:16 +00:00
Bill Wendling
e36b47e17b Revert r176154 in favor of a better approach.
Code generation makes some basic assumptions about the IR it's been given. In
particular, if there is only one 'invoke' in the function, then that invoke
won't be going away. However, with the advent of the `llvm.donothing' intrinsic,
those invokes may go away. If all of them go away, the landing pad no longer has
any users. This confuses the back-end, which asserts.

This happens with SjLj exceptions, because that's the model that modifies the IR
based on there being invokes, etc. in the function.

Remove any invokes of `llvm.donothing' during SjLj EH preparation. This will
give us a CFG that the back-end won't be confused about. If all of the invokes
in a function are removed, then the SjLj EH prepare pass won't insert the bogus
code the relies upon the invokes being there.
<rdar://problem/13228754&13316637>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176677 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 02:21:08 +00:00
David Blaikie
d7e0de5956 Upgrade tests to the latest debug info format.
Mostly this is just changing the named metadata (llvm.dbg.sp, llvm.dbg.gv,
llvm.dbg.<func>.lv, etc -> llvm.dbg.cu), adding a few fields to older records
(DIVariable: flags/inlined-at, DICompileUnit: sp/gv/types,
DISubprogram: local variables list)

The tests to update were discovered by a change I'm working on to remove debug
info version support - so any tests using old debug info versions I haven't
updated probably are bad tests or just not actually designed to test debug
info.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176671 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 00:23:31 +00:00
Chad Rosier
33947b4391 [fast-isel] Add support for the expect intrinsic.
rdar://13370942

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176649 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 20:42:17 +00:00
Jyotsna Verma
a4dd8d6732 Hexagon: Handle i8, i16 and i1 Var Args.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176647 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 20:28:34 +00:00
Jyotsna Verma
b6716187ca Hexagon: Add support to lower block address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 19:10:28 +00:00
Benjamin Kramer
36b36de4e8 Move testcase, this is testing extraction not inserting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176635 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 18:51:02 +00:00
Benjamin Kramer
02c2ecf9f1 X86: Fold EXTRACT_SUBVECTORs of a BUILD_VECTOR into a smaller BUILD_VECTOR.
That can usually be lowered efficiently and is common in sandybridge code.
It would be nice to do this in DAGCombiner but we can't insert arbitrary
BUILD_VECTORs this late.

Fixes PR15462.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 18:48:40 +00:00
Jim Grosbach
34fd0d2b93 SDAG: Handle scalarizing an extend of a <1 x iN> vector.
Just scalarize the element and rebuild a vector of the result type
from that.

rdar://13281568

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176614 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 05:47:54 +00:00
Michael Liao
fe9dbe0066 Fix two remaining issue after fixing PR15355 when CMOV is not available
- Phi nodes should be replaced/updated after lowering CMOV into branch
  because 'mainMBB' updating operand in Phi node is changed.
- Add EFLAGS in livein before lowering the 2nd CMOV. It's necessary as
  we will reuse the EFLAGS generated before the 1st lowered CMOV, which
  won't clobber EFLAGS. However, we need explicitly specify that.
- '-attr=-cmov' test case are added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07 01:01:29 +00:00
Akira Hatanaka
b7656a9cc4 [mips] Custom-legalize BR_JT.
In N64-static, GOT address is needed to compute the branch address.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-06 21:32:03 +00:00
Akira Hatanaka
508d11b19c [mips] Add a line which checks function name. Rename file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176543 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-06 01:58:03 +00:00
Michael Liao
c537f79dcd Fix PR15355
- Clear 'mayStore' flag when loading from the atomic variable before the
  spin loop
- Clear kill flag from one use to multiple use in registers forming the
  address to that atomic variable
- don't use a physical register as live-in register in BB (neither entry
  nor landing pad.) by copying it into virtual register

(patch by Cameron Zwarich)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176538 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-06 00:17:04 +00:00
Akira Hatanaka
5ffd24c49f [mips] Remove android calling convention.
This calling convention was added just to handle functions which return vector
of floats. The fix committed in r165585 solves the problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176530 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 23:22:30 +00:00
Akira Hatanaka
1e3e869899 [mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets
returned in registers $2 and $4.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 22:54:59 +00:00
Akira Hatanaka
7433b2e114 [mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly
handle fp128 returns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176523 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 22:41:55 +00:00
Akira Hatanaka
cb2eafdfa3 [mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floating
point registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176521 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 22:20:28 +00:00
Akira Hatanaka
5fdee6d2b5 [mips] Correct handling of fp128 (long double) formals and read long double
parameters from floating point registers if target is mips64 hard float.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 22:13:04 +00:00
Jyotsna Verma
0d44328ce8 reverting patch 176508.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 20:29:23 +00:00
Jyotsna Verma
c34f17140f Hexagon: Add support for lowering block address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 19:37:46 +00:00
Jyotsna Verma
18daead3ff Hexagon: Expand addc, adde, subc and sube.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 19:04:47 +00:00
Jyotsna Verma
ee0ef13eba Hexagon: Add encoding bits to the TFR64 instructions.
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 18:42:28 +00:00
Vincent Lejeune
cae6801b7d R600: Turn BUILD_VECTOR into Reg_Sequence
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176487 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 15:04:49 +00:00
Vincent Lejeune
f49cf1c320 R600: Use MUL_IEEE for trig/fdiv intrinsic
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176485 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 15:04:37 +00:00
NAKAMURA Takumi
a0a790b0b7 llvm/test/CodeGen/Mips/mips64-f128.ll: Add explicit -mtriple=mips64el-unknown-unknown to appease win32.
FIXME: Is it expected for win32 to affect mips targets?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 02:18:59 +00:00
NAKAMURA Takumi
466508bab1 llvm/test/CodeGen/Thumb/iabs.ll: Add explicit -mtriple=thumb-unknown-unknown to appease win32 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176470 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 02:18:52 +00:00
Akira Hatanaka
1ae08e0077 [mips] Print move instructions.
"move $4, $5" is printed instead of "or $4, $5, $zero".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04 22:25:01 +00:00
Jack Carter
0b9675d631 Mips specific inline assembler constraint 'R'
'R' An address that can be sued in a non-macro load or store.
This patch includes a positive test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176452 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04 21:33:15 +00:00
Eli Bendersky
75d0ad4215 Reapply r176381, writing the CHECKs in a more forgiving manner to account for
running llvm-objdump on Darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176443 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04 18:20:31 +00:00
Preston Gurd
9a2cfffdb6 Bypass Slow Divides
* Only apply divide bypass optimization when not optimizing for size. 
* Fixed bug caused by constant for 0 value of type Int32,
  used dividend type to generate the constant instead.
* For atom x86-64 apply the divide bypass to use 16-bit divides instead of
  64-bit divides when operand values are small enough.
* Added lit tests for 64-bit divide bypass.

Patch by Tyler Nowicki!




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04 18:13:57 +00:00
Jim Grosbach
7bf504c58f ARM: Creating a vector from a lane of another.
The VDUP instruction source register doesn't allow a non-constant lane
index, so make sure we don't construct a ARM::VDUPLANE node asking it to
do so.

rdar://13328063
http://llvm.org/bugs/show_bug.cgi?id=13963

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02 20:16:24 +00:00