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6b9f97dd89
llvm-6502/test/MC/Disassembler/ARM
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Silviu Baranga 6b9f97dd89 Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 14:09:07 +00:00
..
arm-tests.txt Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction. 2012-04-18 13:02:55 +00:00
basic-arm-instructions.txt Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 2011-10-20 22:23:58 +00:00
fp-encoding.txt ARM VLDR/VSTR instructions don't need a size suffix. 2011-11-14 23:03:21 +00:00
invalid-Bcc-thumb.txt Tighten Thumb1 branch predicate decoding. 2011-08-09 21:07:45 +00:00
invalid-BFI-arm.txt Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 2011-08-09 22:48:45 +00:00
invalid-CPS2p-arm.txt Tighten operand checking on CPS instructions. 2011-08-09 23:05:39 +00:00
invalid-CPS3p-arm.txt Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. 2011-10-28 18:02:13 +00:00
invalid-DMB-thumb.txt Tighten operand checking on memory barrier instructions. 2011-08-09 23:25:42 +00:00
invalid-DSB-arm.txt Tighten operand checking on memory barrier instructions. 2011-08-09 23:25:42 +00:00
invalid-IT-CBNZ-thumb.txt Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 2011-09-08 22:42:49 +00:00
invalid-IT-CC15.txt Change ARMInstPrinter::printPredicateOperand() so it will not abort if it 2012-03-01 22:13:02 +00:00
invalid-IT-thumb.txt Add a testcase for r138625. 2011-08-26 06:45:08 +00:00
invalid-LDC-form-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-LDM-thumb.txt LDM writeback is not allowed if Rn is in the target register list. 2011-09-09 23:13:33 +00:00
invalid-LDR_POST-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-LDR_PRE-arm.txt invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 2011-08-26 20:43:14 +00:00
invalid-LDRB_POST-arm.txt Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 2011-08-17 17:44:15 +00:00
invalid-LDRD_PRE-thumb.txt Thumb2 assembly parsing and encoding for LDRD(immediate). 2011-09-08 22:07:06 +00:00
invalid-LDRrs-arm.txt Fix single word and unsigned byte data transfer instruction encodings so that 2011-03-31 19:28:35 +00:00
invalid-MCR-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-MOVr-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-MOVs-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-MOVs-LSL-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-MOVTi16-arm.txt Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 2011-08-10 00:03:03 +00:00
invalid-MRRC2-arm.txt Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. 2012-04-18 13:12:50 +00:00
invalid-MSRi-arm.txt Continue to tighten decoding by performing more operand validation. 2011-08-11 20:21:46 +00:00
invalid-RFEorLDMIA-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-SBFX-arm.txt Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 2011-08-10 00:03:03 +00:00
invalid-SMLAD-arm.txt Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 2011-08-10 00:03:03 +00:00
invalid-SRS-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-STMIA_UPD-thumb.txt Continue to tighten decoding by performing more operand validation. 2011-08-11 20:21:46 +00:00
invalid-SXTB-arm.txt Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 2011-08-10 00:03:03 +00:00
invalid-t2Bcc-thumb.txt Tighten operand checking on memory barrier instructions. 2011-08-09 23:25:42 +00:00
invalid-t2LDRBT-thumb.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-t2LDREXD-thumb.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
invalid-t2LDRSHi8-thumb.txt Improve operand validation for Thumb2 addressing modes. 2011-08-11 20:40:40 +00:00
invalid-t2LDRSHi12-thumb.txt Improve operand validation for Thumb2 addressing modes. 2011-08-11 20:40:40 +00:00
invalid-t2PUSH-thumb.txt Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either. 2011-09-12 21:28:46 +00:00
invalid-t2STR_POST-thumb.txt Improve operand validation for Thumb2 addressing modes. 2011-08-11 20:40:40 +00:00
invalid-t2STRD_PRE-thumb.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
invalid-t2STREXB-thumb.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
invalid-t2STREXD-thumb.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-UMAAL-arm.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-VLD1DUPq8_UPD-arm.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
invalid-VLD3DUPd32_UPD-thumb.txt Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 2011-08-09 20:55:18 +00:00
invalid-VLDMSDB_UPD-arm.txt Improve error checking in the new ARM disassembler. Patch by James Molloy. 2011-08-11 18:24:51 +00:00
invalid-VQADD-arm.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
invalid-VST1d8Twb_register-thumb.txt Fixed a case of ARM disassembly getting an assert on a bad encoding 2012-04-11 22:40:17 +00:00
invalid-VST2b32_UPD-arm.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
ldrd-armv4.txt Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node. 2012-04-02 15:20:39 +00:00
lit.local.cfg Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu 2012-03-25 09:02:19 +00:00
memory-arm-instructions.txt Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 2011-08-15 20:51:32 +00:00
neon-tests.txt Simplify some uses of utohexstr. 2011-11-07 21:00:59 +00:00
neon.txt Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) 2012-04-17 00:49:27 +00:00
neont2.txt Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) 2012-04-17 00:49:27 +00:00
thumb1.txt Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 2011-08-26 18:09:22 +00:00
thumb2.txt Fix an incorrect decoder test. 2011-09-26 23:08:34 +00:00
thumb-MSR-MClass.txt Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 2011-09-28 14:21:38 +00:00
thumb-printf.txt Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 2011-09-07 19:42:28 +00:00
thumb-tests.txt Thumb2 assembly parsing and encoding for LDC/STC. 2011-10-12 20:54:17 +00:00
unpredictable-ADC-arm.txt Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions. 2012-04-05 16:19:29 +00:00
unpredictable-ADDREXT3-arm.txt Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 2012-03-22 14:14:49 +00:00
unpredictable-AI1cmp-arm.txt Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler. 2012-04-18 12:48:43 +00:00
unpredictable-LDR-arm.txt Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM 2012-03-22 13:24:43 +00:00
unpredictable-LDRD-arm.txt Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 2012-03-22 14:14:49 +00:00
unpredictable-LSL-regform.txt The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 2012-03-20 15:54:56 +00:00
unpredictable-MRRC2-arm.txt Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. 2012-04-18 13:12:50 +00:00
unpredictable-MRS-arm.txt Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors. 2012-04-18 14:09:07 +00:00
unpredictable-MUL-arm.txt Added soft fail cases for the disassembler when decoding MUL instructions on ARM. 2012-03-22 13:14:39 +00:00
unpredictable-RSC-arm.txt The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 2012-03-20 15:54:56 +00:00
unpredictable-SHADD16-arm.txt Added support for handling unpredictable arithmetic instructions on ARM. 2012-04-05 16:13:15 +00:00
unpredictable-SSAT-arm.txt The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 2012-03-20 15:54:56 +00:00
unpredictable-STRBrs-arm.txt The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 2012-03-20 15:54:56 +00:00
unpredictable-UQADD8-arm.txt The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 2012-03-20 15:54:56 +00:00
unpredictables-thumb.txt Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. 2012-02-09 10:56:31 +00:00
vfp4.txt Fix a number of problems with ARM fused multiply add/subtract instructions. 2012-04-11 00:13:00 +00:00