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ebd4eec538
llvm-6502/test/CodeGen/R600
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Michel Danzer ebd4eec538 R600/SI: Fix broken encoding of DS_WRITE_B32 
The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD
instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused
it to corrupt the encoding of that by clobbering the first operand with
the second one.

Undo that damage and only apply the SMRD logic to that.

Fixes some derivates related piglit regressions with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188558 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 16:19:24 +00:00
..
64bit-kernel-args.ll R600: Add 64-bit float load/store support 2013-08-01 15:23:42 +00:00
128bit-kernel-args.ll R600: Use KCache for kernel arguments 2013-07-23 01:48:18 +00:00
add.ll R600: Use KCache for kernel arguments 2013-07-23 01:48:18 +00:00
and.ll R600: Set scheduling preference to Sched::Source 2013-08-12 22:33:21 +00:00
bfe_uint.ll R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns 2013-05-10 02:09:45 +00:00
bfi_int.ll R600/SI: Add more special cases for opcodes to ensureSRegLimit() 2013-08-06 23:08:18 +00:00
bitcast.ll R600/SI: Allow conversion between v32i8 and v8i32 2013-08-14 22:22:09 +00:00
build_vector.ll R600: Add 64-bit float load/store support 2013-08-01 15:23:42 +00:00
call_fs.ll R600: Add a test for r183108 2013-06-04 15:03:35 +00:00
cf_end.ll R600: Stop emitting the instruction type byte before each instruction 2013-05-06 17:50:44 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
disconnected-predset-break-bug.ll R600: use native for alu 2013-04-30 00:14:38 +00:00
dot4-folding.ll R600: Const/Neg/Abs can be folded to dot4 2013-06-04 23:17:15 +00:00
elf.ll R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE 2013-04-26 18:32:24 +00:00
elf.r600.ll R600: Emit config values in register / value pairs 2013-05-06 17:50:51 +00:00
fabs.ll DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free 2013-07-23 23:55:03 +00:00
fadd64.ll R600/SI: Add initial double precision support for SI 2013-07-12 18:14:56 +00:00
fadd.ll R600: Set scheduling preference to Sched::Source 2013-08-12 22:33:21 +00:00
fcmp64.ll R600/SI: Implement select and compares for SI 2013-07-12 18:15:19 +00:00
fcmp-cnd.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
fcmp-cnde-int-args.ll R600: Improve custom lowering of select_cc 2013-03-08 15:37:09 +00:00
fcmp.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
fconst64.ll R600: Reapply testcase from r186178, the big endian issue should be fixed by r186196. 2013-07-12 21:54:43 +00:00
fdiv64.ll R600/SI: Add initial double precision support for SI 2013-07-12 18:14:56 +00:00
fdiv.ll R600: Add 64-bit float load/store support 2013-08-01 15:23:42 +00:00
fetch-limits.r600.ll R600: Fix the fetch limits for R600 generation GPUs 2013-06-07 20:28:55 +00:00
fetch-limits.r700+.ll R600: Fix the fetch limits for R600 generation GPUs 2013-06-07 20:28:55 +00:00
floor.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
fma.ll R600/SI: Add FMA pattern 2013-08-10 10:38:47 +00:00
fmad.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
fmax.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
fmin.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
fmul64.ll R600/SI: Add initial double precision support for SI 2013-07-12 18:14:56 +00:00
fmul.ll R600: Set scheduling preference to Sched::Source 2013-08-12 22:33:21 +00:00
fmul.v4f32.ll R600: Set scheduling preference to Sched::Source 2013-08-12 22:33:21 +00:00
fmuladd.ll R600/SI: FMA is faster than fmul and fadd for f64 2013-08-10 10:38:54 +00:00
fneg.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
fp64_to_sint.ll R600/SI: Implement sint<->fp64 conversions 2013-08-08 16:06:08 +00:00
fp_to_sint.ll R600: Add 64-bit float load/store support 2013-08-01 15:23:42 +00:00
fp_to_uint.ll R600/SI: Add pattern for fp_to_uint 2013-08-14 22:21:57 +00:00
fpext.ll R600/SI: Implement fp32<->fp64 conversions 2013-08-08 16:06:15 +00:00
fptrunc.ll R600/SI: Implement fp32<->fp64 conversions 2013-08-08 16:06:15 +00:00
fsqrt.ll R600/SI: Add fsqrt pattern for SI 2013-07-12 18:15:13 +00:00
fsub64.ll R600/SI: Add double precision fsub pattern for SI 2013-07-12 18:15:08 +00:00
fsub.ll R600: Set scheduling preference to Sched::Source 2013-08-12 22:33:21 +00:00
i8-to-double-to-float.ll R600: Use KCache for kernel arguments 2013-07-23 01:48:18 +00:00
icmp-select-sete-reverse-args.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
imm.ll R600/SI: Add support for buffer stores v2 2013-04-05 23:31:51 +00:00
indirect-addressing-si.ll R600/SI: Add missing test for r187749 2013-08-05 22:45:56 +00:00
indirect-addressing.ll R600: Fix calculation of stack offset in AMDGPUFrameLowering 2013-06-07 20:52:05 +00:00
jump-address.ll R600: Don't emit empty then clause and use alu_pop_after 2013-07-19 21:45:15 +00:00
kcache-fold.ll R600: Set scheduling preference to Sched::Source 2013-08-12 22:33:21 +00:00
legalizedag-bug-expand-setcc.ll LegalizeDAG: Respect the result of TLI.getBooleanContents() when expanding SETCC 2013-03-08 15:37:02 +00:00
lit.local.cfg [tests] Cleanup initialization of test suffixes. 2013-08-16 00:37:11 +00:00
literals.ll R600: Enable folding of inline literals into REQ_SEQUENCE instructions 2013-08-16 01:11:55 +00:00
llvm.AMDGPU.barrier.local.ll R600: Add support for GROUP_BARRIER instruction 2013-06-28 15:46:59 +00:00
llvm.AMDGPU.cube.ll R600: Use new getNamedOperandIdx function generated by TableGen 2013-06-25 21:22:18 +00:00
llvm.AMDGPU.imax.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.imin.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.mul.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
llvm.AMDGPU.tex.ll R600: Swizzle texture/export instructions 2013-06-04 15:04:53 +00:00
llvm.AMDGPU.trunc.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
llvm.AMDGPU.umax.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.umin.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.cos.ll R600: Use DAG lowering pass to handle fcos/fsin 2013-07-09 15:03:11 +00:00
llvm.pow.ll R600: Support schedule and packetization of trans-only inst 2013-06-29 19:32:43 +00:00
llvm.SI.fs.interp.constant.ll R600/SI: Add processor types for each SI variant 2013-04-05 23:31:35 +00:00
llvm.SI.imageload.ll R600/SI: Use i8 types for resource descriptors in tests 2013-08-14 23:24:37 +00:00
llvm.SI.resinfo.ll R600/SI: Use i8 types for resource descriptors in tests 2013-08-14 23:24:37 +00:00
llvm.SI.sample.ll R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics 2013-08-14 23:24:53 +00:00
llvm.SI.sampled.ll R600/SI: Convert v16i8 resource descriptors to i128 2013-08-14 23:24:45 +00:00
llvm.SI.tid.ll R600/SI: Add intrinsic for retrieving the current thread ID 2013-07-10 16:36:52 +00:00
llvm.sin.ll R600: Use DAG lowering pass to handle fcos/fsin 2013-07-09 15:03:11 +00:00
load64.ll R600/SI: Add initial double precision support for SI 2013-07-12 18:14:56 +00:00
load-input-fold.ll R600: Lower int_load_input to copyFromReg instead of Register node 2013-05-17 16:51:06 +00:00
load.ll R600: Add support for global vector loads with element types less than 32-bits 2013-08-16 01:12:16 +00:00
load.vec.ll R600: Add 64-bit float load/store support 2013-08-01 15:23:42 +00:00
local-memory-two-objects.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
local-memory.ll R600/SI: Fix broken encoding of DS_WRITE_B32 2013-08-16 16:19:24 +00:00
loop-address.ll R600: Use KCache for kernel arguments 2013-07-23 01:48:18 +00:00
lshl.ll R600/SI: Add more special cases for opcodes to ensureSRegLimit() 2013-08-06 23:08:18 +00:00
lshr.ll R600/SI: Add more special cases for opcodes to ensureSRegLimit() 2013-08-06 23:08:18 +00:00
mad_int24.ll R600: Add support for 24-bit MAD instructions 2013-07-23 01:48:49 +00:00
mad_uint24.ll R600: Add support for 24-bit MAD instructions 2013-07-23 01:48:49 +00:00
max-literals.ll R600: Avoid more than 4 literals in the same instruction group at scheduling 2013-07-31 19:32:07 +00:00
mul_int24.ll R600: Add support for 24-bit MUL instructions 2013-07-23 01:48:42 +00:00
mul_uint24.ll R600: Add support for 24-bit MUL instructions 2013-07-23 01:48:42 +00:00
mul.ll R600/SI: Expand mul of v2i32/v4i32 for SI 2013-06-25 13:55:26 +00:00
mulhu.ll R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
or.ll R600/SI: Expand or of v2i32/v4i32 for SI 2013-06-25 13:55:29 +00:00
packetizer.ll R600: Fix typo in R600Schedule.td 2013-06-25 02:39:20 +00:00
parallelandifcollapse.ll Factor FlattenCFG out from SimplifyCFG 2013-08-06 02:43:45 +00:00
parallelorifcollapse.ll Factor FlattenCFG out from SimplifyCFG 2013-08-06 02:43:45 +00:00
predicates.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
pv-packing.ll R600: PV stores Reg id, not index 2013-06-17 20:16:40 +00:00
pv.ll R600: use capital letter for PV channel 2013-06-03 15:44:35 +00:00
r600-encoding.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
r600cfg.ll R600: Don't emit empty then clause and use alu_pop_after 2013-07-19 21:45:15 +00:00
README R600: Reorganize lit tests and document how they should be organized 2013-04-19 02:10:53 +00:00
reciprocal.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
rotr.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
rv7x0_count3.ll R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen. 2013-06-17 20:16:26 +00:00
schedule-fs-loop-nested-if.ll llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts. 2013-03-11 23:16:30 +00:00
schedule-fs-loop-nested.ll llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts. 2013-03-11 23:16:30 +00:00
schedule-fs-loop.ll llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts. 2013-03-11 23:16:30 +00:00
schedule-if-2.ll llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts. 2013-03-11 23:16:30 +00:00
schedule-if.ll llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts. 2013-03-11 23:16:30 +00:00
schedule-vs-if-nested-loop.ll llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts. 2013-03-11 23:16:30 +00:00
sdiv.ll R600: Add CF_END 2013-04-23 17:34:00 +00:00
selectcc-cnd.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
selectcc-cnde-int.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
selectcc-icmp-select-float.ll R600: Prettier asmPrint of Alu 2013-05-02 21:52:30 +00:00
selectcc-opt.ll R600: Use KCache for kernel arguments 2013-07-23 01:48:18 +00:00
set-dx10.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
setcc.ll R600: Set scheduling preference to Sched::Source 2013-08-12 22:33:21 +00:00
seto.ll R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
setuo.ll R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
sgpr-copy.ll R600/SI: Use VSrc_* register classes as the default classes for types 2013-08-06 23:08:28 +00:00
shl.ll R600/SI: Expand shl of v2i32/v4i32 for SI 2013-06-25 13:55:32 +00:00
short-args.ll R600: Improve support for < 32-bit loads 2013-07-23 01:48:35 +00:00
si-lod-bias.ll R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2 2013-08-14 23:24:32 +00:00
si-vector-hang.ll R600: Add support for i16 and i8 global stores 2013-08-16 01:12:06 +00:00
sign_extend.ll R600/SI: Custom lower i64 sign_extend 2013-06-03 17:40:03 +00:00
sint_to_fp64.ll R600/SI: Implement sint<->fp64 conversions 2013-08-08 16:06:08 +00:00
sint_to_fp.ll R600: Add 64-bit float load/store support 2013-08-01 15:23:42 +00:00
sra.ll R600/SI: Add support for 64-bit loads 2013-07-15 19:00:09 +00:00
srl.ll R600/SI: Expand srl of v2i32/v4i32 for SI 2013-06-25 13:55:37 +00:00
store.ll R600: Add support for global vector stores with elements less than 32-bits 2013-08-16 01:12:11 +00:00
store.r600.ll R600: Change the RAT instruction assembly names so they match the docs 2013-08-16 01:11:46 +00:00
sub.ll R600: Set scheduling preference to Sched::Source 2013-08-12 22:33:21 +00:00
swizzle-export.ll [R600] Replicate old DAGCombiner behavior in target specific DAG combine. 2013-07-30 00:27:16 +00:00
tex-clause-antidep.ll R600: Anti dep better handled in tex clause 2013-06-07 23:30:26 +00:00
texture-input-merge.ll R600: Add a pass that merge Vector Register 2013-06-05 21:38:04 +00:00
udiv.ll R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG 2013-06-25 13:55:43 +00:00
uint_to_fp.ll R600: Add 64-bit float load/store support 2013-08-01 15:23:42 +00:00
unsupported-cc.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
urecip.ll R600/SI: Add pattern for AMDGPUurecip 2013-04-10 17:17:56 +00:00
urem.ll R600/SI: Expand urem of v2i32/v4i32 for SI 2013-06-25 13:55:46 +00:00
vertex-fetch-encoding.ll R600: Add support for v4i32 stores on Cayman 2013-08-16 01:12:00 +00:00
vselect.ll Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
vtx-schedule.ll R600: Use KCache for kernel arguments 2013-07-23 01:48:18 +00:00
work-item-intrinsics.ll R600: Change the RAT instruction assembly names so they match the docs 2013-08-16 01:11:46 +00:00
xor.ll R600/SI: Expand xor v2i32/v4i32 2013-06-25 13:55:52 +00:00
zero_extend.ll R600: Change the RAT instruction assembly names so they match the docs 2013-08-16 01:11:46 +00:00

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.