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integrate zero-riscy

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marqs
2018-10-06 01:07:53 +03:00
parent e1d8446752
commit 4676cbd2f0
44 changed files with 11897 additions and 9998 deletions
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software/sys_controller_bsp/HAL/src/alt_busy_sleep.c
+5 -69
View File
@@ -57,77 +57,13 @@ unsigned int alt_busy_sleep (unsigned int us)
* skipped to speed up simulation.
*/
#ifndef ALT_SIM_OPTIMIZE
int i;
int big_loops;
alt_u32 cycles_per_loop;
if (!strcmp(NIOS2_CPU_IMPLEMENTATION,"tiny"))
{
cycles_per_loop = 9;
}
else
{
cycles_per_loop = 3;
}
unsigned long i, loops;
big_loops = us / (INT_MAX/
(ALT_CPU_FREQ/(cycles_per_loop * 1000000)));
// 1 loop >= 7 cyc
loops = ((ALT_CPU_FREQ/1000000)*us)/7;
if (big_loops)
{
for(i=0;i<big_loops;i++)
{
/*
* Do NOT Try to single step the asm statement below
* (single step will never return)
* Step out of this function or set a breakpoint after the asm statements
*/
__asm__ volatile (
"\n0:"
"\n\taddi %0,%0, -1"
"\n\tbne %0,zero,0b"
"\n1:"
"\n\t.pushsection .debug_alt_sim_info"
"\n\t.int 4, 0, 0b, 1b"
"\n\t.popsection"
:: "r" (INT_MAX));
us -= (INT_MAX/(ALT_CPU_FREQ/
(cycles_per_loop * 1000000)));
}
/*
* Do NOT Try to single step the asm statement below
* (single step will never return)
* Step out of this function or set a breakpoint after the asm statements
*/
__asm__ volatile (
"\n0:"
"\n\taddi %0,%0, -1"
"\n\tbne %0,zero,0b"
"\n1:"
"\n\t.pushsection .debug_alt_sim_info"
"\n\t.int 4, 0, 0b, 1b"
"\n\t.popsection"
:: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000))));
}
else
{
/*
* Do NOT Try to single step the asm statement below
* (single step will never return)
* Step out of this function or set a breakpoint after the asm statements
*/
__asm__ volatile (
"\n0:"
"\n\taddi %0,%0, -1"
"\n\tbgt %0,zero,0b"
"\n1:"
"\n\t.pushsection .debug_alt_sim_info"
"\n\t.int 4, 0, 0b, 1b"
"\n\t.popsection"
:: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000))));
}
for (i=7; i<loops; i++)
asm volatile ("nop");
#endif /* #ifndef ALT_SIM_OPTIMIZE */
return 0;
}
software/sys_controller_bsp/HAL/src/alt_putcharbuf.c
+80
View File
@@ -0,0 +1,80 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#ifdef ALT_SEMIHOSTING
#include "sys/alt_stdio.h"
#include "unistd.h"
#ifndef ALT_PUTBUF_SIZE
#define ALT_PUTBUF_SIZE 64
#endif
// Buffer for the printed chars
static char buf[ALT_PUTBUF_SIZE] ={0};
// index into the buffer
static unsigned int fill_index;
/*
* ALT putcharbuf funtion
* Used only for semihosting.
* Not thread safe!
* This fucntion buffers up chars to be printed until either alt_putbufflush()
* is called or the buffer is full.
* It is called by alt_printf when semihosting is turned on
* Its purpose is to minimize the number of Break 1 issuesd by the semihosting
* libraries.
*/
int
alt_putcharbuf(int c)
{
buf[fill_index++] = (char)(c & 0xff);
if(fill_index >= ALT_PUTBUF_SIZE)
alt_putbufflush();
return c;
}
/*
* ALT putbufflush
* used only for smehosting
* Not thread safe!
* Dumps all the chars in the buffer to STDOUT
*/
int
alt_putbufflush()
{
int results;
results = write(STDOUT_FILENO,buf,fill_index);
fill_index = 0;
return results;
}
#endif
software/sys_controller_bsp/Makefile
+1
View File
@@ -256,6 +256,7 @@ hal_C_LIB_SRCS := \
$(hal_SRCS_ROOT)/src/alt_dev_llist_insert.c \
$(hal_SRCS_ROOT)/src/alt_errno.c \
$(hal_SRCS_ROOT)/src/alt_flash_dev.c \
$(hal_SRCS_ROOT)/src/alt_main.c
# i2c_opencores_driver sources root
i2c_opencores_driver_SRCS_ROOT := drivers
software/sys_controller_bsp/alt_sys_init.c
+4 -4
View File
@@ -83,11 +83,11 @@ I2C_OPENCORES_INSTANCE ( I2C_OPENCORES_1, i2c_opencores_1);
* present for backwards-compatibility.
*/
/*void alt_irq_init ( const void* base )
void alt_irq_init ( const void* base )
{
ALTERA_NIOS2_GEN2_IRQ_INIT ( NIOS2_QSYS_0, nios2_qsys_0);
alt_irq_cpu_enable_interrupts();
}*/
/*ALTERA_NIOS2_GEN2_IRQ_INIT ( NIOS2_QSYS_0, nios2_qsys_0);
alt_irq_cpu_enable_interrupts();*/
}
/*
* Initialize the non-interrupt controller devices.
software/sys_controller_bsp/drivers/inc/Altera_UP_SD_Card_Avalon_Interface_mod.h
-166
View File
@@ -1,166 +0,0 @@
#ifndef __ALTERA_UP_SD_CARD_AVALON_INTERFACE_H__
#define __ALTERA_UP_SD_CARD_AVALON_INTERFACE_H__
#include <stddef.h>
#include <alt_types.h>
#include <sys/alt_dev.h>
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
#define SD_RAW_IFACE
/*
* Device structure definition. Each instance of the driver uses one
* of these structures to hold its associated state.
*/
typedef struct alt_up_sd_card_dev {
/// @brief character mode device structure
/// @sa Developing Device Drivers for the HAL in Nios II Software Developer's Handbook
alt_dev dev;
/// @brief the base address of the device
unsigned int base;
} alt_up_sd_card_dev;
#ifndef bool
typedef enum e_bool { false = 0, true = 1 } bool;
#endif
//////////////////////////////////////////////////////////////////////////
// HAL system functions
alt_up_sd_card_dev* alt_up_sd_card_open_dev(const char *name);
/* Open an SD Card Interface if it is connected to the system. */
bool alt_up_sd_card_is_Present(void);
/* Check if there is an SD Card insterted into the SD Card socket.
*/
#ifndef SD_RAW_IFACE
bool alt_up_sd_card_is_FAT16(void);
/* This function reads the SD card data in an effort to determine if the card is formated as a FAT16
* volume. Please note that FAT12 has a similar format, but will not be supported by this driver.
*/
short int alt_up_sd_card_fopen(char *name, bool create);
/* This function reads the SD card data in an effort to determine if the card is formated as a FAT16
* volume. Please note that FAT12 has a similar format, but will not be supported by this driver.
*
* Inputs:
* name - a file name including a directory, relative to the root directory
* create - a flag set to true to create a file if it does not already exist
* Output:
* An index to the file record assigned to the specified file. -1 is returned if the file could not be opened.
*/
short int alt_up_sd_card_find_first(char *directory_to_search_through, char *file_name);
/* This function sets up a search algorithm to go through a given directory looking for files.
* If the search directory is valid, then the function searches for the first file it finds.
* Inputs:
* directory_to_search_through - name of the directory to search through
* file_name - an array to store a name of the file found. Must be 13 bytes long (12 bytes for file name and 1 byte of NULL termination).
* Outputs:
* 0 - success
* 1 - invalid directory
* 2 - No card or incorrect card format.
*
* To specify a directory give the name in a format consistent with the following regular expression:
* [{[valid_chars]+}/]*.
*
* In other words, give a path name starting at the root directory, where each directory name is followed by a '/'.
* Then, append a '.' to the directory name. Examples:
* "." - look through the root directory
* "first/." - look through a directory named "first" that is located in the root directory.
* "first/sub/." - look through a directory named "sub", that is located within the subdirectory named "first". "first" is located in the root directory.
* Invalid examples include:
* "/.", "/////." - this is not the root directory.
* "/first/." - the first character may not be a '/'.
*/
short int alt_up_sd_card_find_next(char *file_name);
/* This function searches for the next file in a given directory, as specified by the find_first function.
* Inputs:
* file_name - an array to store a name of the file found. Must be 13 bytes long (12 bytes for file name and 1 byte of NULL termination).
* Outputs:
* -1 - end of directory.
* 0 - success
* 2 - No card or incorrect card format.
* 4 - find_first has not been called successfully.
*/
void alt_up_sd_card_set_attributes(short int file_handle, short int attributes);
/* Set file attributes as needed.
*/
short int alt_up_sd_card_get_attributes(short int file_handle);
/* Return file attributes, or -1 if the file_handle is invalid.
*/
short int alt_up_sd_card_read(short int file_handle);
/* Read a single character from the given file. Return -1 if at the end of a file. Any other negative number
* means that the file could not be read. A number between 0 and 255 is an ASCII character read from the SD Card. */
bool alt_up_sd_card_write(short int file_handle, char byte_of_data);
/* Write a single character to a given file. Return true if successful, and false otherwise. */
bool alt_up_sd_card_fclose(short int file_handle);
// This function closes an opened file and saves data to SD Card if necessary.
#else
bool Write_Sector_Data(int sector_index, int partition_offset);
bool Save_Modified_Sector();
bool Read_Sector_Data(int sector_index, int partition_offset);
#endif //SD_RAW_IFACE
//////////////////////////////////////////////////////////////////////////
// file-like operation functions
//////////////////////////////////////////////////////////////////////////
// direct operation functions
/*
* Macros used by alt_sys_init
*/
#define ALTERA_UP_SD_CARD_AVALON_INTERFACE_MOD_INSTANCE(name, device) \
static alt_up_sd_card_dev device = \
{ \
{ \
ALT_LLIST_ENTRY, \
name##_NAME, \
NULL , /* open */ \
NULL , /* close */ \
NULL, /* read */ \
NULL, /* write */ \
NULL , /* lseek */ \
NULL , /* fstat */ \
NULL , /* ioctl */ \
}, \
name##_BASE, \
}
#define ALTERA_UP_SD_CARD_AVALON_INTERFACE_MOD_INIT(name, device) \
{ \
alt_dev_reg(&device.dev); \
}
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_UP_SD_CARD_AVALON_INTERFACE_H__ */
software/sys_controller_bsp/drivers/inc/altera_avalon_timer.h
+193
View File
@@ -0,0 +1,193 @@
#ifndef __ALT_AVALON_TIMER_H__
#define __ALT_AVALON_TIMER_H__
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#include <string.h>
#include "alt_types.h"
#include "sys/alt_dev.h"
#include "sys/alt_warning.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
#define __ALT_COUNTER_SIZE(name) name##_COUNTER_SIZE
#define _ALT_COUNTER_SIZE(name) __ALT_COUNTER_SIZE(name)
#define ALT_SYS_CLK_COUNTER_SIZE _ALT_COUNTER_SIZE(ALT_SYS_CLK)
#define ALT_TIMESTAMP_COUNTER_SIZE _ALT_COUNTER_SIZE(ALT_TIMESTAMP_CLK)
#if (ALT_SYS_CLK_COUNTER_SIZE == 64)
#define alt_sysclk_type alt_u64
#else
#define alt_sysclk_type alt_u32
#endif
#if (ALT_TIMESTAMP_COUNTER_SIZE == 64)
#define alt_timestamp_type alt_u64
#else
#define alt_timestamp_type alt_u32
#endif
/*
* The function alt_avalon_timer_sc_init() is the initialisation function for
* the system clock. It registers the timers interrupt handler, and then calls
* the system clock regestration function, alt_sysclk_init().
*/
extern void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id,
alt_u32 irq, alt_u32 freq);
/*
* Variables used to store the timestamp parameters, when the device is to be
* accessed using the high resolution timestamp driver.
*/
extern void* altera_avalon_timer_ts_base;
extern alt_u32 altera_avalon_timer_ts_freq;
/*
* ALTERA_AVALON_TIMER_INSTANCE is the macro used by alt_sys_init() to
* allocate any per device memory that may be required. In this case no
* allocation is necessary.
*/
#define ALTERA_AVALON_TIMER_INSTANCE(name, dev) extern int alt_no_storage
/*
* Macro used to calculate the timer interrupt frequency. Although this is
* somewhat fearsome, when compiled with -O2 it will be resolved at compile
* time to a constant value.
*/
#define ALTERA_AVALON_TIMER_FREQ(freq, period, units) \
strcmp (units, "us") ? \
(strcmp (units, "ms") ? \
(strcmp (units, "s") ? \
((freq + (period - 1))/period) \
: 1) \
: (1000 + (period - 1))/period) \
: ((1000000 + (period - 1))/period)
/*
* Construct macros which contain the base address of the system clock and the
* timestamp device. These are used below to determine which driver to use for
* a given timer.
*/
#define __ALT_CLK_BASE(name) name##_BASE
#define _ALT_CLK_BASE(name) __ALT_CLK_BASE(name)
#define ALT_SYS_CLK_BASE _ALT_CLK_BASE(ALT_SYS_CLK)
#define ALT_TIMESTAMP_CLK_BASE _ALT_CLK_BASE(ALT_TIMESTAMP_CLK)
/*
* If there is no system clock, then the above macro will result in
* ALT_SYS_CLK_BASE being set to none_BASE. We therefore need to provide an
* invalid value for this, so that no timer is wrongly identified as the system
* clock.
*/
#define none_BASE 0xffffffff
/*
* ALTERA_AVALON_TIMER_INIT is the macro used by alt_sys_init() to provide
* the run time initialisation of the device. In this case this translates to
* a call to alt_avalon_timer_sc_init() if the device is the system clock, i.e.
* if it has the name "sysclk".
*
* If the device is not the system clock, then it is used to provide the
* timestamp facility.
*
* To ensure as much as possible is evaluated at compile time, rather than
* compare the name of the device to "/dev/sysclk" using strcmp(), the base
* address of the device is compared to SYSCLK_BASE to determine whether it's
* the system clock. Since the base address of a device must be unique, these
* two aproaches are equivalent.
*
* This macro performs a sanity check to ensure that the interrupt has been
* connected for this device. If not, then an apropriate error message is
* generated at build time.
*/
#define ALTERA_AVALON_TIMER_INIT(name, dev) \
if (name##_BASE == ALT_SYS_CLK_BASE) \
{ \
if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \
{ \
ALT_LINK_ERROR ("Error: Interrupt not connected for " #dev ". " \
"The system clock driver requires an interrupt to be " \
"connected. Please select an IRQ for this device in " \
"SOPC builder."); \
} \
else \
{ \
alt_avalon_timer_sc_init((void*) name##_BASE, \
name##_IRQ_INTERRUPT_CONTROLLER_ID, \
name##_IRQ, \
ALTERA_AVALON_TIMER_FREQ(name##_FREQ, \
name##_PERIOD, \
name##_PERIOD_UNITS));\
} \
} \
else if (name##_BASE == ALT_TIMESTAMP_CLK_BASE) \
{ \
if (name##_SNAPSHOT) \
{ \
altera_avalon_timer_ts_base = (void*) name##_BASE; \
altera_avalon_timer_ts_freq = name##_FREQ; \
} \
else \
{ \
ALT_LINK_ERROR ("Error: Snapshot register not available for " \
#dev ". " \
"The timestamp driver requires the snapshot register " \
"to be readable. Please enable this register for this " \
"device in SOPC builder."); \
} \
}
/*
*
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_AVALON_TIMER_H__ */
software/sys_controller_bsp/drivers/inc/altera_avalon_timer_regs.h
+202
View File
@@ -0,0 +1,202 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#ifndef __ALTERA_AVALON_TIMER_REGS_H__
#define __ALTERA_AVALON_TIMER_REGS_H__
#include <io.h>
/* STATUS register */
#define ALTERA_AVALON_TIMER_STATUS_REG 0
#define IOADDR_ALTERA_AVALON_TIMER_STATUS(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_STATUS_REG)
#define IORD_ALTERA_AVALON_TIMER_STATUS(base) \
IORD(base, ALTERA_AVALON_TIMER_STATUS_REG)
#define IOWR_ALTERA_AVALON_TIMER_STATUS(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_STATUS_REG, data)
#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1)
#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0)
#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2)
#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1)
/* CONTROL register */
#define ALTERA_AVALON_TIMER_CONTROL_REG 1
#define IOADDR_ALTERA_AVALON_TIMER_CONTROL(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_CONTROL_REG)
#define IORD_ALTERA_AVALON_TIMER_CONTROL(base) \
IORD(base, ALTERA_AVALON_TIMER_CONTROL_REG)
#define IOWR_ALTERA_AVALON_TIMER_CONTROL(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_CONTROL_REG, data)
#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1)
#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0)
#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2)
#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1)
#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4)
#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2)
#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8)
#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3)
/* Period and SnapShot Register for COUNTER_SIZE = 32 */
/*----------------------------------------------------*/
/* PERIODL register */
#define ALTERA_AVALON_TIMER_PERIODL_REG 2
#define IOADDR_ALTERA_AVALON_TIMER_PERIODL(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODL_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIODL(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIODL_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIODL(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIODL_REG, data)
#define ALTERA_AVALON_TIMER_PERIODL_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIODL_OFST (0)
/* PERIODH register */
#define ALTERA_AVALON_TIMER_PERIODH_REG 3
#define IOADDR_ALTERA_AVALON_TIMER_PERIODH(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODH_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIODH(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIODH_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIODH(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIODH_REG, data)
#define ALTERA_AVALON_TIMER_PERIODH_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIODH_OFST (0)
/* SNAPL register */
#define ALTERA_AVALON_TIMER_SNAPL_REG 4
#define IOADDR_ALTERA_AVALON_TIMER_SNAPL(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPL_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAPL(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAPL_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAPL(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAPL_REG, data)
#define ALTERA_AVALON_TIMER_SNAPL_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAPL_OFST (0)
/* SNAPH register */
#define ALTERA_AVALON_TIMER_SNAPH_REG 5
#define IOADDR_ALTERA_AVALON_TIMER_SNAPH(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPH_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAPH(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAPH_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAPH(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAPH_REG, data)
#define ALTERA_AVALON_TIMER_SNAPH_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAPH_OFST (0)
/* Period and SnapShot Register for COUNTER_SIZE = 64 */
/*----------------------------------------------------*/
/* PERIOD_0 register */
#define ALTERA_AVALON_TIMER_PERIOD_0_REG 2
#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_0(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_0_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIOD_0(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIOD_0_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIOD_0(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIOD_0_REG, data)
#define ALTERA_AVALON_TIMER_PERIOD_0_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIOD_0_OFST (0)
/* PERIOD_1 register */
#define ALTERA_AVALON_TIMER_PERIOD_1_REG 3
#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_1(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_1_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIOD_1(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIOD_1_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIOD_1(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIOD_1_REG, data)
#define ALTERA_AVALON_TIMER_PERIOD_1_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIOD_1_OFST (0)
/* PERIOD_2 register */
#define ALTERA_AVALON_TIMER_PERIOD_2_REG 4
#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_2(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_2_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIOD_2(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIOD_2_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIOD_2(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIOD_2_REG, data)
#define ALTERA_AVALON_TIMER_PERIOD_2_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIOD_2_OFST (0)
/* PERIOD_3 register */
#define ALTERA_AVALON_TIMER_PERIOD_3_REG 5
#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_3(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_3_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIOD_3(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIOD_3_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIOD_3(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIOD_3_REG, data)
#define ALTERA_AVALON_TIMER_PERIOD_3_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIOD_3_OFST (0)
/* SNAP_0 register */
#define ALTERA_AVALON_TIMER_SNAP_0_REG 6
#define IOADDR_ALTERA_AVALON_TIMER_SNAP_0(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_0_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAP_0(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAP_0_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAP_0(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAP_0_REG, data)
#define ALTERA_AVALON_TIMER_SNAP_0_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAP_0_OFST (0)
/* SNAP_1 register */
#define ALTERA_AVALON_TIMER_SNAP_1_REG 7
#define IOADDR_ALTERA_AVALON_TIMER_SNAP_1(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_1_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAP_1(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAP_1_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAP_1(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAP_1_REG, data)
#define ALTERA_AVALON_TIMER_SNAP_1_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAP_1_OFST (0)
/* SNAP_2 register */
#define ALTERA_AVALON_TIMER_SNAP_2_REG 8
#define IOADDR_ALTERA_AVALON_TIMER_SNAP_2(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_2_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAP_2(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAP_2_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAP_2(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAP_2_REG, data)
#define ALTERA_AVALON_TIMER_SNAP_2_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAP_2_OFST (0)
/* SNAP_3 register */
#define ALTERA_AVALON_TIMER_SNAP_3_REG 9
#define IOADDR_ALTERA_AVALON_TIMER_SNAP_3(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_3_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAP_3(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAP_3_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAP_3(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAP_3_REG, data)
#define ALTERA_AVALON_TIMER_SNAP_3_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAP_3_OFST (0)
#endif /* __ALTERA_AVALON_TIMER_REGS_H__ */
software/sys_controller_bsp/drivers/src/Altera_UP_SD_Card_Avalon_Interface_mod.c
-1908
View File
File diff suppressed because it is too large Load Diff
software/sys_controller_bsp/drivers/src/altera_avalon_timer_sc.c
+110
View File
@@ -0,0 +1,110 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#include <string.h>
#include "sys/alt_alarm.h"
#include "sys/alt_irq.h"
#include "altera_avalon_timer.h"
#include "altera_avalon_timer_regs.h"
#include "alt_types.h"
#include "sys/alt_log_printf.h"
/*
* alt_avalon_timer_sc_irq() is the interrupt handler used for the system
* clock. This is called periodically when a timer interrupt occurs. The
* function first clears the interrupt condition, and then calls the
* alt_tick() function to notify the system that a timer tick has occurred.
*
* alt_tick() increments the system tick count, and updates any registered
* alarms, see alt_tick.c for further details.
*/
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
static void alt_avalon_timer_sc_irq (void* base)
#else
static void alt_avalon_timer_sc_irq (void* base, alt_u32 id)
#endif
{
alt_irq_context cpu_sr;
/* clear the interrupt */
IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0);
/*
* Dummy read to ensure IRQ is negated before the ISR returns.
* The control register is read because reading the status
* register has side-effects per the register map documentation.
*/
IORD_ALTERA_AVALON_TIMER_CONTROL (base);
/* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */
ALT_LOG_SYS_CLK_HEARTBEAT();
/*
* Notify the system of a clock tick. disable interrupts
* during this time to safely support ISR preemption
*/
cpu_sr = alt_irq_disable_all();
alt_tick ();
alt_irq_enable_all(cpu_sr);
}
/*
* alt_avalon_timer_sc_init() is called to initialise the timer that will be
* used to provide the periodic system clock. This is called from the
* auto-generated alt_sys_init() function.
*/
void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id,
alt_u32 irq, alt_u32 freq)
{
/* set the system clock frequency */
alt_sysclk_init (freq);
/* set to free running mode */
IOWR_ALTERA_AVALON_TIMER_CONTROL (base,
ALTERA_AVALON_TIMER_CONTROL_ITO_MSK |
ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
ALTERA_AVALON_TIMER_CONTROL_START_MSK);
/* register the interrupt handler, and enable the interrupt */
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq,
base, NULL);
#else
alt_irq_register (irq, base, alt_avalon_timer_sc_irq);
#endif
}
software/sys_controller_bsp/drivers/src/altera_avalon_timer_ts.c
+143
View File
@@ -0,0 +1,143 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#include <string.h>
#include "system.h"
#include "sys/alt_timestamp.h"
#include "altera_avalon_timer.h"
#include "altera_avalon_timer_regs.h"
#include "alt_types.h"
/*
* These functions are only available if a timestamp device has been selected
* for this system.
*/
#if (ALT_TIMESTAMP_CLK_BASE != none_BASE)
/*
* The function alt_timestamp_start() can be called at application level to
* initialise the timestamp facility. In this case the period register is
* set to full scale, i.e. 0xffffffff, and then started running. Note that
* the period register may not be writable, depending on the hardware
* configuration, in which case this function does not reset the period.
*
* The timer is not run in continuous mode, so that the user can detect timer
* roll-over, i.e. alt_timestamp() returns 0.
*
* The return value of this function is 0 upon sucess and -1 if in timestamp
* device has not been registered.
*/
int alt_timestamp_start(void)
{
void* base = altera_avalon_timer_ts_base;
if (!altera_avalon_timer_ts_freq)
{
return -1;
}
else
{
if(ALT_TIMESTAMP_COUNTER_SIZE == 64) {
IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK);
IOWR_ALTERA_AVALON_TIMER_PERIOD_0 (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_PERIOD_1 (base, 0xFFFF);;
IOWR_ALTERA_AVALON_TIMER_PERIOD_2 (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_PERIOD_3 (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK);
} else {
IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK);
IOWR_ALTERA_AVALON_TIMER_PERIODL (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_PERIODH (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK);
}
}
return 0;
}
/*
* alt_timestamp() returns the current timestamp count. In the event that
* the timer has run full period, or there is no timestamp available, this
* function return -1.
*
* The returned timestamp counts up from the last time the period register
* was reset.
*/
alt_timestamp_type alt_timestamp(void)
{
void* base = altera_avalon_timer_ts_base;
if (!altera_avalon_timer_ts_freq)
{
#if (ALT_TIMESTAMP_COUNTER_SIZE == 64)
return 0xFFFFFFFFFFFFFFFFULL;
#else
return 0xFFFFFFFF;
#endif
}
else
{
#if (ALT_TIMESTAMP_COUNTER_SIZE == 64)
IOWR_ALTERA_AVALON_TIMER_SNAP_0 (base, 0);
alt_timestamp_type snap_0 = IORD_ALTERA_AVALON_TIMER_SNAP_0(base) & ALTERA_AVALON_TIMER_SNAP_0_MSK;
alt_timestamp_type snap_1 = IORD_ALTERA_AVALON_TIMER_SNAP_1(base) & ALTERA_AVALON_TIMER_SNAP_1_MSK;
alt_timestamp_type snap_2 = IORD_ALTERA_AVALON_TIMER_SNAP_2(base) & ALTERA_AVALON_TIMER_SNAP_2_MSK;
alt_timestamp_type snap_3 = IORD_ALTERA_AVALON_TIMER_SNAP_3(base) & ALTERA_AVALON_TIMER_SNAP_3_MSK;
return (0xFFFFFFFFFFFFFFFFULL - ( (snap_3 << 48) | (snap_2 << 32) | (snap_1 << 16) | (snap_0) ));
#else
IOWR_ALTERA_AVALON_TIMER_SNAPL (base, 0);
alt_timestamp_type lower = IORD_ALTERA_AVALON_TIMER_SNAPL(base) & ALTERA_AVALON_TIMER_SNAPL_MSK;
alt_timestamp_type upper = IORD_ALTERA_AVALON_TIMER_SNAPH(base) & ALTERA_AVALON_TIMER_SNAPH_MSK;
return (0xFFFFFFFF - ((upper << 16) | lower));
#endif
}
}
/*
* Return the number of timestamp ticks per second. This will be 0 if no
* timestamp device has been registered.
*/
alt_u32 alt_timestamp_freq(void)
{
return altera_avalon_timer_ts_freq;
}
#endif /* timestamp available */
software/sys_controller_bsp/drivers/src/altera_avalon_timer_vars.c
+45
View File
@@ -0,0 +1,45 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#include <string.h>
#include "altera_avalon_timer.h"
#include "alt_types.h"
/*
* Variables used to store the timestamp parameters. These are initialised
* from alt_sys_init() using the ALTERA_AVALON_TIMER_INIT macro
* defined in altera_avalon_timer.h.
*/
void* altera_avalon_timer_ts_base = (void*) 0;
alt_u32 altera_avalon_timer_ts_freq = 0;
software/sys_controller_bsp/libhal_bsp.a
BIN
View File
Binary file not shown.
software/sys_controller_bsp/linker.h
+5 -5
View File
@@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
* SOPC Builder design path: ../../sys.sopcinfo
*
* Generated: Sun Oct 16 12:18:06 EEST 2016
* Generated: Fri Oct 05 19:59:02 EEST 2018
*/
/*
@@ -65,11 +65,11 @@
*
*/
#define EPCQ_CONTROLLER_0_AVL_MEM_REGION_BASE 0x0
#define EPCQ_CONTROLLER_0_AVL_MEM_REGION_BASE 0x800000
#define EPCQ_CONTROLLER_0_AVL_MEM_REGION_SPAN 8388608
#define ONCHIP_MEMORY2_0_REGION_BASE 0x810020
#define ONCHIP_MEMORY2_0_REGION_SPAN 40928
#define RESET_REGION_BASE 0x810000
#define ONCHIP_MEMORY2_0_REGION_BASE 0x10020
#define ONCHIP_MEMORY2_0_REGION_SPAN 36832
#define RESET_REGION_BASE 0x10000
#define RESET_REGION_SPAN 32
software/sys_controller_bsp/linker.x
+26 -26
View File
@@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
* SOPC Builder design path: ../../sys.sopcinfo
*
* Generated: Sun Oct 16 12:18:06 EEST 2016
* Generated: Fri Oct 05 19:59:02 EEST 2018
*/
/*
@@ -50,14 +50,14 @@
MEMORY
{
epcq_controller_0_avl_mem : ORIGIN = 0x0, LENGTH = 8388608
reset : ORIGIN = 0x810000, LENGTH = 32
onchip_memory2_0 : ORIGIN = 0x810020, LENGTH = 40928
reset : ORIGIN = 0x10000, LENGTH = 32
onchip_memory2_0 : ORIGIN = 0x10020, LENGTH = 36832
epcq_controller_0_avl_mem : ORIGIN = 0x800000, LENGTH = 8388608
}
/* Define symbols for each memory base-address */
__alt_mem_epcq_controller_0_avl_mem = 0x0;
__alt_mem_onchip_memory2_0 = 0x810000;
__alt_mem_onchip_memory2_0 = 0x10000;
__alt_mem_epcq_controller_0_avl_mem = 0x800000;
OUTPUT_FORMAT( "elf32-littlenios2",
"elf32-littlenios2",
@@ -309,24 +309,7 @@ SECTIONS
*
*/
.epcq_controller_0_avl_mem : AT ( LOADADDR (.bss) + SIZEOF (.bss) )
{
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_start = ABSOLUTE(.));
*(.epcq_controller_0_avl_mem .epcq_controller_0_avl_mem. epcq_controller_0_avl_mem.*)
. = ALIGN(4);
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_end = ABSOLUTE(.));
} > epcq_controller_0_avl_mem
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_load_addr = LOADADDR(.epcq_controller_0_avl_mem));
/*
*
* This section's LMA is set to the .text region.
* crt0 will copy to this section's specified mapped region virtual memory address (VMA)
*
*/
.onchip_memory2_0 LOADADDR (.epcq_controller_0_avl_mem) + SIZEOF (.epcq_controller_0_avl_mem) : AT ( LOADADDR (.epcq_controller_0_avl_mem) + SIZEOF (.epcq_controller_0_avl_mem) )
.onchip_memory2_0 LOADADDR (.bss) + SIZEOF (.bss) : AT ( LOADADDR (.bss) + SIZEOF (.bss) )
{
PROVIDE (_alt_partition_onchip_memory2_0_start = ABSOLUTE(.));
*(.onchip_memory2_0 .onchip_memory2_0. onchip_memory2_0.*)
@@ -339,6 +322,23 @@ SECTIONS
PROVIDE (_alt_partition_onchip_memory2_0_load_addr = LOADADDR(.onchip_memory2_0));
/*
*
* This section's LMA is set to the .text region.
* crt0 will copy to this section's specified mapped region virtual memory address (VMA)
*
*/
.epcq_controller_0_avl_mem : AT ( LOADADDR (.onchip_memory2_0) + SIZEOF (.onchip_memory2_0) )
{
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_start = ABSOLUTE(.));
*(.epcq_controller_0_avl_mem .epcq_controller_0_avl_mem. epcq_controller_0_avl_mem.*)
. = ALIGN(4);
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_end = ABSOLUTE(.));
} > epcq_controller_0_avl_mem
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_load_addr = LOADADDR(.epcq_controller_0_avl_mem));
/*
* Stabs debugging sections.
*
@@ -386,7 +386,7 @@ SECTIONS
/*
* Don't override this, override the __alt_stack_* symbols instead.
*/
__alt_data_end = 0x81a000;
__alt_data_end = 0x19000;
/*
* The next two symbols define the location of the default stack. You can
@@ -402,4 +402,4 @@ PROVIDE( __alt_stack_limit = __alt_stack_base );
* Override this symbol to put the heap in a different memory.
*/
PROVIDE( __alt_heap_start = end );
PROVIDE( __alt_heap_limit = 0x81a000 );
PROVIDE( __alt_heap_limit = 0x19000 );
software/sys_controller_bsp/mem_init.mk
+10 -10
View File
@@ -161,7 +161,7 @@ ACDS_VERSION := 17.1
SIM_OPTIMIZE ?= 0
# The CPU reset address as needed by elf2flash
RESET_ADDRESS ?= 0x00810000
RESET_ADDRESS ?= 0x00010000
# The specific Nios II ELF file format to use.
NIOS2_ELF_FORMAT ?= elf32-littlenios2
@@ -175,8 +175,8 @@ MEM_0 := epcq_controller_0
$(MEM_0)_NAME := epcq_controller_0
HEX_FILES += $(MEM_INIT_DIR)/$(MEM_0).hex
MEM_INIT_INSTALL_FILES += $(MEM_INIT_INSTALL_DIR)/$(MEM_0).hex
$(MEM_0)_START := 0x00000000
$(MEM_0)_END := 0x007fffff
$(MEM_0)_START := 0x00800000
$(MEM_0)_END := 0x00ffffff
$(MEM_0)_SPAN := 0x00800000
$(MEM_0)_HIERARCHICAL_PATH := epcq_controller_0
$(MEM_0)_WIDTH := 32
@@ -198,9 +198,9 @@ DAT_FILES += $(HDL_SIM_DIR)/$(MEM_1).dat
HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_1).dat
SYM_FILES += $(HDL_SIM_DIR)/$(MEM_1).sym
HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_1).sym
$(MEM_1)_START := 0x00810000
$(MEM_1)_END := 0x00819fff
$(MEM_1)_SPAN := 0x0000a000
$(MEM_1)_START := 0x00010000
$(MEM_1)_END := 0x00018fff
$(MEM_1)_SPAN := 0x00009000
$(MEM_1)_HIERARCHICAL_PATH := onchip_memory2_0
$(MEM_1)_WIDTH := 32
$(MEM_1)_HEX_DATA_WIDTH := 32
@@ -304,10 +304,10 @@ ELF_TO_HEX_CMD = $(strip $(if $(flash_mem_boot_loader_flag), \
$(ELF_TO_HEX_CMD_NO_BOOTLOADER) \
))
$(HEX_FILES): %.hex: $(ELF)
$(post-process-info)
@$(MKDIR) $(@D)
$(ELF_TO_HEX_CMD)
#$(HEX_FILES): %.hex: $(ELF)
# $(post-process-info)
# @$(MKDIR) $(@D)
# $(ELF_TO_HEX_CMD)
$(SYM_FILES): %.sym: $(ELF)
$(post-process-info)
software/sys_controller_bsp/memory.gdb
+5 -5
View File
@@ -3,7 +3,7 @@
# Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
# SOPC Builder design path: ../../sys.sopcinfo
#
# Generated: Sun Oct 16 12:18:06 EEST 2016
# Generated: Fri Oct 05 19:59:02 EEST 2018
# DO NOT MODIFY THIS FILE
#
@@ -46,8 +46,8 @@
# The cache attribute is specified which improves GDB performance
# by allowing GDB to cache memory contents on the host.
# epcq_controller_0_avl_mem
memory 0x0 0x800000 cache
# onchip_memory2_0
memory 0x810000 0x81a000 cache
memory 0x10000 0x19000 cache
# epcq_controller_0_avl_mem
memory 0x800000 0x1000000 cache
software/sys_controller_bsp/settings.bsp
+27 -27
View File
@@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Sep 25, 2018 9:18:49 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1537899529022</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Oct 5, 2018 8:21:01 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1538758741996</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
@@ -898,101 +898,101 @@
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<MemoryMap>
<slaveDescriptor>epcq_controller_0_avl_mem</slaveDescriptor>
<addressRange>0x00000000 - 0x007FFFFF</addressRange>
<addressSpan>8388608</addressSpan>
<attributes>flash, memory, non-volatile</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>onchip_memory2_0</slaveDescriptor>
<addressRange>0x00810000 - 0x00819FFF</addressRange>
<addressRange>0x00010000 - 0x00019FFF</addressRange>
<addressSpan>40960</addressSpan>
<attributes>memory</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>timer_0</slaveDescriptor>
<addressRange>0x00821000 - 0x0082101F</addressRange>
<addressRange>0x00020000 - 0x0002001F</addressRange>
<addressSpan>32</addressSpan>
<attributes>timer</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>jtag_uart_0</slaveDescriptor>
<addressRange>0x00020020 - 0x00020027</addressRange>
<addressSpan>8</addressSpan>
<attributes>printable</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>epcq_controller_0_avl_csr</slaveDescriptor>
<addressRange>0x00821020 - 0x0082103F</addressRange>
<addressRange>0x00020100 - 0x0002011F</addressRange>
<addressSpan>32</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>i2c_opencores_1</slaveDescriptor>
<addressRange>0x00821040 - 0x0082105F</addressRange>
<addressRange>0x00021020 - 0x0002103F</addressRange>
<addressSpan>32</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>i2c_opencores_0</slaveDescriptor>
<addressRange>0x00821060 - 0x0082107F</addressRange>
<addressRange>0x00021040 - 0x0002105F</addressRange>
<addressSpan>32</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_8</slaveDescriptor>
<addressRange>0x00821080 - 0x0082108F</addressRange>
<addressRange>0x00021060 - 0x0002106F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_7</slaveDescriptor>
<addressRange>0x00821090 - 0x0082109F</addressRange>
<addressRange>0x00021070 - 0x0002107F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_6</slaveDescriptor>
<addressRange>0x008210A0 - 0x008210AF</addressRange>
<addressRange>0x00021080 - 0x0002108F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_5</slaveDescriptor>
<addressRange>0x008210B0 - 0x008210BF</addressRange>
<addressRange>0x00021090 - 0x0002109F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_4</slaveDescriptor>
<addressRange>0x008210C0 - 0x008210CF</addressRange>
<addressRange>0x000210A0 - 0x000210AF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_3</slaveDescriptor>
<addressRange>0x008210D0 - 0x008210DF</addressRange>
<addressRange>0x000210B0 - 0x000210BF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_2</slaveDescriptor>
<addressRange>0x008210E0 - 0x008210EF</addressRange>
<addressRange>0x000210C0 - 0x000210CF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_1</slaveDescriptor>
<addressRange>0x008210F0 - 0x008210FF</addressRange>
<addressRange>0x000210D0 - 0x000210DF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_0</slaveDescriptor>
<addressRange>0x00821100 - 0x0082110F</addressRange>
<addressRange>0x000210E0 - 0x000210EF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>jtag_uart_0</slaveDescriptor>
<addressRange>0x00821110 - 0x00821117</addressRange>
<addressSpan>8</addressSpan>
<attributes>printable</attributes>
<slaveDescriptor>epcq_controller_0_avl_mem</slaveDescriptor>
<addressRange>0x00800000 - 0x00FFFFFF</addressRange>
<addressSpan>8388608</addressSpan>
<attributes>flash, memory, non-volatile</attributes>
</MemoryMap>
<LinkerSection>
<sectionName>.text</sectionName>
@@ -1018,4 +1018,4 @@
<sectionName>.stack</sectionName>
<regionName>onchip_memory2_0</regionName>
</LinkerSection>
</sch:Settings>
</sch:Settings>
software/sys_controller_bsp/system.h
+29 -29
View File
@@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
* SOPC Builder design path: ../../sys.sopcinfo
*
* Generated: Sun Mar 25 16:51:03 EEST 2018
* Generated: Fri Oct 05 19:59:02 EEST 2018
*/
/*
@@ -62,7 +62,7 @@
#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x00820820
#define ALT_CPU_BREAK_ADDR 0x00000820
#define ALT_CPU_CPU_ARCH_NIOS2_R1
#define ALT_CPU_CPU_FREQ 27000000u
#define ALT_CPU_CPU_ID_SIZE 1
@@ -72,7 +72,7 @@
#define ALT_CPU_DCACHE_LINE_SIZE 0
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_DCACHE_SIZE 0
#define ALT_CPU_EXCEPTION_ADDR 0x00810020
#define ALT_CPU_EXCEPTION_ADDR 0x00010020
#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
#define ALT_CPU_FLUSHDA_SUPPORTED
@@ -87,10 +87,10 @@
#define ALT_CPU_ICACHE_LINE_SIZE 0
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_ICACHE_SIZE 0
#define ALT_CPU_INST_ADDR_WIDTH 0x18
#define ALT_CPU_INST_ADDR_WIDTH 0x11
#define ALT_CPU_NAME "nios2_qsys_0"
#define ALT_CPU_OCI_VERSION 1
#define ALT_CPU_RESET_ADDR 0x00810000
#define ALT_CPU_RESET_ADDR 0x00010000
/*
@@ -99,7 +99,7 @@
*/
#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x00820820
#define NIOS2_BREAK_ADDR 0x00000820
#define NIOS2_CPU_ARCH_NIOS2_R1
#define NIOS2_CPU_FREQ 27000000u
#define NIOS2_CPU_ID_SIZE 1
@@ -109,7 +109,7 @@
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_EXCEPTION_ADDR 0x00810020
#define NIOS2_EXCEPTION_ADDR 0x00010020
#define NIOS2_FLASH_ACCELERATOR_LINES 0
#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
#define NIOS2_FLUSHDA_SUPPORTED
@@ -123,9 +123,9 @@
#define NIOS2_ICACHE_LINE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE_LOG2 0
#define NIOS2_ICACHE_SIZE 0
#define NIOS2_INST_ADDR_WIDTH 0x18
#define NIOS2_INST_ADDR_WIDTH 0x11
#define NIOS2_OCI_VERSION 1
#define NIOS2_RESET_ADDR 0x00810000
#define NIOS2_RESET_ADDR 0x00010000
/*
@@ -140,7 +140,7 @@
#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0_N 0x9
//#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N,(A))
#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N 0x8
#define ALT_CI_NIOS2_HW_CRC32_0(n,A) n
#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(A) A
#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) A
@@ -179,19 +179,19 @@
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart_0"
#define ALT_STDERR_BASE 0x821110
#define ALT_STDERR_BASE 0x20020
#define ALT_STDERR_DEV jtag_uart_0
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart_0"
#define ALT_STDIN_BASE 0x821110
#define ALT_STDIN_BASE 0x20020
#define ALT_STDIN_DEV jtag_uart_0
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart_0"
#define ALT_STDOUT_BASE 0x821110
#define ALT_STDOUT_BASE 0x20020
#define ALT_STDOUT_DEV jtag_uart_0
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
@@ -205,7 +205,7 @@
*/
#define ALT_MODULE_CLASS_epcq_controller_0_avl_csr altera_epcq_controller_mod
#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x821020
#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x20100
#define EPCQ_CONTROLLER_0_AVL_CSR_FLASH_TYPE "EPCS64"
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ 2
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
@@ -225,7 +225,7 @@
*/
#define ALT_MODULE_CLASS_epcq_controller_0_avl_mem altera_epcq_controller_mod
#define EPCQ_CONTROLLER_0_AVL_MEM_BASE 0x0
#define EPCQ_CONTROLLER_0_AVL_MEM_BASE 0x800000
#define EPCQ_CONTROLLER_0_AVL_MEM_FLASH_TYPE "EPCS64"
#define EPCQ_CONTROLLER_0_AVL_MEM_IRQ -1
#define EPCQ_CONTROLLER_0_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
@@ -255,7 +255,7 @@
*/
#define ALT_MODULE_CLASS_i2c_opencores_0 i2c_opencores
#define I2C_OPENCORES_0_BASE 0x821060
#define I2C_OPENCORES_0_BASE 0x21040
#define I2C_OPENCORES_0_IRQ 3
#define I2C_OPENCORES_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define I2C_OPENCORES_0_NAME "/dev/i2c_opencores_0"
@@ -269,7 +269,7 @@
*/
#define ALT_MODULE_CLASS_i2c_opencores_1 i2c_opencores
#define I2C_OPENCORES_1_BASE 0x821040
#define I2C_OPENCORES_1_BASE 0x21020
#define I2C_OPENCORES_1_IRQ 4
#define I2C_OPENCORES_1_IRQ_INTERRUPT_CONTROLLER_ID 0
#define I2C_OPENCORES_1_NAME "/dev/i2c_opencores_1"
@@ -283,7 +283,7 @@
*/
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
#define JTAG_UART_0_BASE 0x821110
#define JTAG_UART_0_BASE 0x20020
#define JTAG_UART_0_IRQ 1
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
@@ -303,7 +303,7 @@
#define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2
#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEMORY2_0_BASE 0x810000
#define ONCHIP_MEMORY2_0_BASE 0x10000
#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
#define ONCHIP_MEMORY2_0_DUAL_PORT 0
#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "AUTO"
@@ -330,7 +330,7 @@
*/
#define ALT_MODULE_CLASS_pio_0 altera_avalon_pio
#define PIO_0_BASE 0x821100
#define PIO_0_BASE 0x210e0
#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_0_CAPTURE 0
@@ -357,7 +357,7 @@
*/
#define ALT_MODULE_CLASS_pio_1 altera_avalon_pio
#define PIO_1_BASE 0x8210f0
#define PIO_1_BASE 0x210d0
#define PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_1_CAPTURE 0
@@ -384,7 +384,7 @@
*/
#define ALT_MODULE_CLASS_pio_2 altera_avalon_pio
#define PIO_2_BASE 0x8210e0
#define PIO_2_BASE 0x210c0
#define PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_2_CAPTURE 0
@@ -411,7 +411,7 @@
*/
#define ALT_MODULE_CLASS_pio_3 altera_avalon_pio
#define PIO_3_BASE 0x8210d0
#define PIO_3_BASE 0x210b0
#define PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_3_CAPTURE 0
@@ -438,7 +438,7 @@
*/
#define ALT_MODULE_CLASS_pio_4 altera_avalon_pio
#define PIO_4_BASE 0x8210c0
#define PIO_4_BASE 0x210a0
#define PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_4_CAPTURE 0
@@ -465,7 +465,7 @@
*/
#define ALT_MODULE_CLASS_pio_5 altera_avalon_pio
#define PIO_5_BASE 0x8210b0
#define PIO_5_BASE 0x21090
#define PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_5_CAPTURE 0
@@ -492,7 +492,7 @@
*/
#define ALT_MODULE_CLASS_pio_6 altera_avalon_pio
#define PIO_6_BASE 0x8210a0
#define PIO_6_BASE 0x21080
#define PIO_6_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_6_CAPTURE 0
@@ -519,7 +519,7 @@
*/
#define ALT_MODULE_CLASS_pio_7 altera_avalon_pio
#define PIO_7_BASE 0x821090
#define PIO_7_BASE 0x21070
#define PIO_7_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_7_CAPTURE 0
@@ -546,7 +546,7 @@
*/
#define ALT_MODULE_CLASS_pio_8 altera_avalon_pio
#define PIO_8_BASE 0x821080
#define PIO_8_BASE 0x21060
#define PIO_8_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_8_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_8_CAPTURE 0
@@ -574,7 +574,7 @@
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
#define TIMER_0_ALWAYS_RUN 0
#define TIMER_0_BASE 0x821000
#define TIMER_0_BASE 0x20000
#define TIMER_0_COUNTER_SIZE 32
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_FREQ 27000000