9 Commits

Author	SHA1	Message	Date
marqs	238cf0b285	update epcq_controller_mod to epcq_controller2	2020-11-10 19:46:07 +02:00
marqs	2319a6f8bd	misc tool updates	2020-04-28 18:48:35 +03:00
marqs	9d496383c3	optimize clock network ... * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl	2019-10-06 23:54:32 +03:00
marqs	6266976114	first OSD implementation	2019-10-03 02:03:43 +03:00
marqs	aa43991534	add mask color option	2019-09-30 19:31:05 +03:00
marqs	7914a2ee83	clean up and update README	2018-10-08 00:37:42 +03:00
marqs	f55e9a877e	SD SPI implementation finished	2016-10-21 01:19:53 +03:00
marqs	c83653c880	Release 0.69 ... * Improved remote control handling code * Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal * Fixed randomly missing blue channel at power-on when using DVI output mode * Added H-PLL coast options * Finer tuning range for scanline strength and mask	2016-04-15 22:05:53 +03:00
marqs	f502b2e46c	Release 0.67. ... - Code cleanup - Some project files added - PAL linetriple added - FPGA PLL parameters optimized - Reduced jitter on low video clock sources	2016-03-27 23:09:31 +03:00