Apple-1-HW/verilog-apple-one
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170 Commits 3 Branches 0 Tags
Commit Graph

72 Commits

Author SHA1 Message Date
Alan Garfield
2432225d01 Initial VGA working with the apple one output. YAY! 2018-01-31 00:48:47 +11:00
Alan Garfield
4fef9bc10b Initial VGA module, still WIP, just outputs fixed VRAM 2018-01-29 22:53:16 +11:00
Alan Garfield
b2ebc23e3a added license headers and tidied up 2018-01-29 22:15:21 +11:00
Alan Garfield
119d077e1a Fixed differences for iceube2 and yosys 2018-01-29 21:36:32 +11:00
Alan Garfield
474cabbab0 Made core neater and trying to get naming better 2018-01-29 21:00:38 +11:00
Alan Garfield
2717184e71 Added yosys support again, yay for FOSS! 2018-01-29 17:45:01 +11:00
Niels Moseley
fe05766894 Fixed address lines of Basic ROM 2018-01-28 20:18:56 +01:00
Alan Garfield
69f1b53e18 added basic rom and fix uart issue on HX 2018-01-28 15:02:51 +11:00
Alan Garfield
164cb06992 added ledx output pins 2018-01-28 13:09:34 +11:00
Niels Moseley
d280d2abaa Added basic ps2 keyboard interface block 2018-01-28 02:00:21 +01:00
Niels Moseley
fba6bda601 Adding missing DE0 timing constraints file 2018-01-27 23:02:05 +01:00
Niels Moseley
6823d0e3f9 Added 6502 PC monitoring 2018-01-27 18:11:33 +01:00
Niels Moseley
0527dbb999 Updated DE0 top level and Quartus DE0 project to new directory layout 2018-01-27 16:01:27 +01:00
Alan Garfield
e9ff2b294e more project file fiddles by the tool. :/ 2018-01-28 00:23:43 +11:00
Alan Garfield
b42567e759 fiddled project files from icecube 2018-01-28 00:19:59 +11:00
Alan Garfield
c4d42fae3c fixed testbench and split CPU cores 2018-01-27 17:00:33 +11:00
Alan Garfield
04323a6256 more moving around, added params for hex files 2018-01-27 14:27:10 +11:00
Alan Garfield
0ca73c561a fixed project path for HX8K 2018-01-27 13:58:03 +11:00
Alan Garfield
149334259d Cleaned up mess, and added HX8K board top file 2018-01-27 13:40:59 +11:00
Niels Moseley
f067774293 Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal. 2018-01-26 22:38:46 +01:00
Niels Moseley
9beb3e5f5e Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files. 2018-01-26 21:29:12 +01:00
Alan Garfield
7bdccf3d1a move things around. 2018-01-27 00:21:05 +11:00