Compare commits
97 Commits
| Author | SHA1 | Date |
|---|---|---|
Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Unknown
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Unknown
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Florian Reitz
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Florian Reitz
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Florian Reitz
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Florian Reitz
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freitz85
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Florian Reitz
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freitz85
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Florian Reitz
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freitz85
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cf98c54e77 |
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@ -3,6 +3,42 @@
|
|||
Thumbs.db
|
||||
.DS_Store
|
||||
|
||||
#Ignore files build by Visual Studio
|
||||
*.obj
|
||||
*.exe
|
||||
*.pdb
|
||||
*.user
|
||||
*.aps
|
||||
*.pch
|
||||
*.vspscc
|
||||
*_i.c
|
||||
*_p.c
|
||||
*.ncb
|
||||
*.suo
|
||||
*.tlb
|
||||
*.tlh
|
||||
*.bak
|
||||
*.cache
|
||||
*.ilk
|
||||
*.log
|
||||
[Bb]in
|
||||
[Dd]ebug*/
|
||||
*.lib
|
||||
*.sbr
|
||||
obj/
|
||||
[Rr]elease*/
|
||||
_ReSharper*/
|
||||
[Tt]est[Rr]esult*
|
||||
.vs/
|
||||
|
||||
*.opendb
|
||||
**/Debug
|
||||
*.db
|
||||
*.dbg
|
||||
*.lbl
|
||||
*.map
|
||||
Makefile\.options
|
||||
|
||||
# Ignore list for Eagle, a PCB layout tool
|
||||
|
||||
# Backup files
|
||||
|
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@ -177,3 +213,14 @@ Hardware/SD_A2\.b\$1
|
|||
*.nga
|
||||
|
||||
*.tspec
|
||||
|
||||
|
||||
VHDL/_pace\.ucf
|
||||
|
||||
VHDL/AppleIISd\.tim
|
||||
|
||||
VHDL/AppleIISd\.jed
|
||||
|
||||
Firmware/AppleIISd.bin
|
||||
|
||||
Software/Flasher.bin
|
||||
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|
|||
BIN
AppleIISd.bin
BIN
AppleIISd.bin
Binary file not shown.
|
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@ -1,21 +0,0 @@
|
|||
Stückliste exportiert aus C:/Projekte/AppleIISd/trunk/Hardware/SD_A2.sch am 24.08.2017 17:37
|
||||
|
||||
Qty Value Device Package Parts Description
|
||||
1 A2-50PINSLOT1-3 A2-50PIN-SL1-3 ST1 Apple ][ Peripheral Card Connector
|
||||
1 LEDSQR2X5 LED2X5 LED1 LED
|
||||
1 MA03-1 MA03-1 SV1 PIN HEADER
|
||||
1 MA06-1 MA06-1 SV2 PIN HEADER
|
||||
6 100k R-EU_R0603 R0603 R3, R5, R6, R7, R9, R11 RESISTOR, European symbol
|
||||
6 100n C-EUC0603K C0603K C1, C3, C4, C5, C6, C7 CAPACITOR, European symbol
|
||||
1 104H-TDA0-R 104H-TDA0-R 104H-TDA0-R U$2
|
||||
1 10k R-EU_R0603 R0603 R10 RESISTOR, European symbol
|
||||
3 10n C-EUC0603K C0603K C8, C9, C10 CAPACITOR, European symbol
|
||||
1 1u CPOL-EU153CLV-0405 153CLV-0405 C2 POLARIZED CAPACITOR, European symbol
|
||||
1 200 R-EU_R0603 R0603 R1 RESISTOR, European symbol
|
||||
1 2716 / 2732 2716 DIL24 IC3 MEMORY
|
||||
1 330 R-EU_R0603 R0603 R2 RESISTOR, European symbol
|
||||
1 470 R-EU_R0603 R0603 R4 RESISTOR, European symbol
|
||||
1 68k R-EU_R0603 R0603 R8 RESISTOR, European symbol
|
||||
1 74HCT245N 74HCT245N DIL20 IC1 Octal BUS TRANSCEIVER, 3-state
|
||||
1 LM317 LM317TL 317TL IC2 VOLTAGE REGULATOR
|
||||
1 XC9572XL XC9572_S44 S44 IC4
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
:10000000A220A000A203A0FF2058FFBABD00018DCE
|
||||
:10001000F807290F853D0A0A0A0A852BAA2CFFCF6B
|
||||
:1000200020A9C99003A92F002000C8C900F0010031
|
||||
:10003000A9018542A62B85436444A90885456446E9
|
||||
:1000400064472CFFCF20CFC94C0108D82058FFBAF5
|
||||
:10005000BD00018DF807290F853D0A0A0A0A852B84
|
||||
:10006000AA2CFFCF20A9C99004A92F801FA9803CEA
|
||||
:1000700083C0F029A542C900F014C901F013C902D8
|
||||
:10008000F012C903F011C9FFF010A90138604CC18A
|
||||
:10009000C94CCFC94C38CA4CA9CA4CADCA2000C8FB
|
||||
:1000A000B0EA80D000000000000000000000000066
|
||||
:1000B0000000000000000000000000000000000040
|
||||
:1000C0000000000000000000000000000000000030
|
||||
:1000D0000000000000000000000000000000000020
|
||||
:1000E0000000000000000000000000000000000010
|
||||
:1000F000000000000000000000000000FFFF174BA0
|
||||
:10010000D8A9039D81C0BD83C009019D83C0A907F3
|
||||
:100110009D82C0A00AA9FF9D80C03C81C010FB88C1
|
||||
:10012000D0F5BD83C029FE9D83C0A9318540A9CBF0
|
||||
:10013000854120EBC820FFC8C901D039A93D8540C1
|
||||
:10014000A9CB854120EBC8201AC9C901D02AA949E9
|
||||
:100150008540A9CB854120EBC820FFC8A94F854029
|
||||
:10016000A9CB854120EBC820FFC8C901F0E0C90038
|
||||
:10017000D0034CB2C84CD9C8A9498540A9CB854108
|
||||
:1001800020EBC8A9558540A9CB854120EBC820FFAD
|
||||
:10019000C8C901F0E3C900D0034CB2C8A9378540F3
|
||||
:1001A000A9CB854120EBC820FFC8C901F0F6C900E2
|
||||
:1001B000D027A9438540A9CB854120EBC820FFC8A3
|
||||
:1001C000C900D015BD83C009809D83C0BD81C00911
|
||||
:1001D000049D81C018A000900338A027BD83C009EA
|
||||
:1001E000019D83C0A9009D82C098605AA000B140C3
|
||||
:1001F0009D80C03C81C010FBC8C00690F17A60A908
|
||||
:10020000FF9D80C03C81C010FBBD80C0853C298023
|
||||
:10021000D0EDA9FF9D80C0A53C6020FFC8485AA032
|
||||
:1002200004A9FF9D80C03C81C010FBBD80C04888F0
|
||||
:10023000D0EFA43D6899F805689978056899F804A5
|
||||
:10024000689978047AA9FF9D80C06860DA5AA63D53
|
||||
:10025000A5469DF805A5479D7805A9009DF8049D34
|
||||
:100260007804A9802443F005A9019DF804A0091E83
|
||||
:10027000F8053E78053EF8043E780488D0F17AFA15
|
||||
:10028000605AA43D9D80C0B978049D80C0B9F8042F
|
||||
:100290009D80C0B978059D80C0B9F8059D80C0A932
|
||||
:1002A000FF9D80C020FFC87A6048A9403C83C018E9
|
||||
:1002B000F00138686048A9203C83C018F001386814
|
||||
:1002C00060A900A2FFA0FF20B5C99002A92B602061
|
||||
:1002D0004CC9BD83C029FE9D83C0A9512081C9C9D5
|
||||
:1002E00000D050A9FF9D80C0BD80C0C9FED0F4A041
|
||||
:1002F00002BD81C009109D81C0A9FF9D80C0643CE2
|
||||
:10030000BD80C09244E644D002E645E63CD0F18888
|
||||
:10031000D0ECBD80C0BD80C0BD80C0BD81C029EF14
|
||||
:100320009D81C018A9000848BD83C009019D83C0F4
|
||||
:1003300068286038A92780EE20B5C9B067204CC96D
|
||||
:10034000BD83C029FE9D83C0A9582081C9C900D0A2
|
||||
:100350004EA9FF9D80C0A9FE9D80C0A002643CB252
|
||||
:10036000449D80C0E644D002E645E63CD0F188D00A
|
||||
:10037000EC9D80C09D80C09D80C0BD80C0291FC9EC
|
||||
:1003800005D01C18A9000848A9FF9D80C0BD80C0E9
|
||||
:10039000C900F0F4BD83C009019D83C0682860389E
|
||||
:1003A000A92780E238A92B80DD38A90160A43DA9E6
|
||||
:1003B0000220F5BEB07999F8068545A9009978061E
|
||||
:1003C0008544A000989144C8D0FAE645989144C865
|
||||
:1003D000D0FAA902A43D8542AD78068544B9F80655
|
||||
:1003E000854564466447A62B204BC7B042A901A4AB
|
||||
:1003F0003D8542B978068544B9F80685456446646A
|
||||
:1004000047A62B204BC7B027A43DB978068544B931
|
||||
:10041000F8068545A00098D144D015C8D0F8E64527
|
||||
:1004200098D144D00BC8D0F820F8BE18A9006000BD
|
||||
:10043000004000000000954100000000F948000065
|
||||
:1004400001AA875000000200FF77000000006569E4
|
||||
:0B04500040000000776900000000FF82
|
||||
:00000001FF
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
{signal: [
|
||||
['Apple',
|
||||
{name: '7M', wave: 'n........', period: 2 },
|
||||
{name: 'Phi0', wave: 'hl......h......l..'},
|
||||
{name: 'Q3', wave: 'lh...l..h...l..h..'},
|
||||
{name: 'ADD', wave: 'x.....=.........x.', data: "IO-Address", phase: 0.5},
|
||||
{name: '/DEV_SEL',wave: 'h.......0......1..'},
|
||||
{},
|
||||
{name: 'R/W', wave: 'x.....=.........x.', phase: 0.5},
|
||||
{name: 'DATA', wave: 'x.....z..x.=....z.', phase: 0.5},
|
||||
],
|
||||
{},
|
||||
['Card',
|
||||
{name: 'Address', wave: 'x........=.......x'},
|
||||
{name: 'DATA', wave: 'x........z.=....z.', data: 'FromPeripheral', phase: 0.5},
|
||||
],
|
||||
]}
|
||||
914
AppleIISd.lst
914
AppleIISd.lst
|
|
@ -1,914 +0,0 @@
|
|||
1 ********************************
|
||||
2 *
|
||||
3 * Apple][Sd Firmware
|
||||
4 * Version 0.7
|
||||
5 *
|
||||
6 * (c) Florian Reitz, 2017
|
||||
7 *
|
||||
8 * X register usually contains SLOT16
|
||||
9 * Y register is used for counting or SLOT
|
||||
10 *
|
||||
11 ********************************
|
||||
12
|
||||
22-OCT-17 20:21
|
||||
14
|
||||
15 XC ; enable 65C02 code
|
||||
16 DEBUG = 0
|
||||
17 DO DEBUG
|
||||
18 ORG $8000
|
||||
19 ELSE
|
||||
20 ORG $C700 ; Expansion ROM
|
||||
21 FIN
|
||||
22
|
||||
23 * Memory defines
|
||||
24
|
||||
25 SLOT16 = $2B ; $s0 -> slot * 16
|
||||
26 WORK = $3C
|
||||
27 SLOT = $3D ; $0s
|
||||
28 CMDLO = $40
|
||||
29 CMDHI = $41
|
||||
30
|
||||
31 DCMD = $42 ; Command code
|
||||
32 BUFFER = $44 ; Buffer address
|
||||
33 BLOCK = $46 ; Block number
|
||||
34
|
||||
35 CURSLOT = $07F8 ; $Cs
|
||||
36 DATA = $C080
|
||||
37 CTRL = DATA+1
|
||||
38 DIV = DATA+2
|
||||
39 SS = DATA+3
|
||||
40 R30 = $0478
|
||||
41 R31 = $04F8
|
||||
42 R32 = $0578
|
||||
43 R33 = $05F8
|
||||
44 RAM0 = $0678
|
||||
45 RAM1 = $06F8
|
||||
46
|
||||
47 * Constants
|
||||
48
|
||||
49 DUMMY = $FF
|
||||
50 FRX = $10 ; CTRL register
|
||||
51 ECE = $04
|
||||
52 SS0 = $01 ; SS register
|
||||
53 WP = $20
|
||||
54 CD = $40
|
||||
55 INITED = $80
|
||||
56
|
||||
57
|
||||
58 * signature bytes
|
||||
59
|
||||
C700: A2 20 60 LDX #$20
|
||||
C702: A0 00 61 LDY #$00
|
||||
C704: A2 03 62 LDX #$03
|
||||
C706: A0 FF 63 LDY #$FF ; neither 5.25 nor Smartport
|
||||
64
|
||||
65 * find slot nr
|
||||
66
|
||||
67 DO DEBUG
|
||||
68 LDA #$04
|
||||
69 STA SLOT
|
||||
70 LDA #$C4
|
||||
71 STA CURSLOT
|
||||
72 LDA #$40
|
||||
73
|
||||
74 ELSE
|
||||
C708: 20 58 FF 75 JSR $FF58
|
||||
C70B: BA 76 TSX
|
||||
C70C: BD 00 01 77 LDA $0100,X
|
||||
C70F: 8D F8 07 78 STA CURSLOT ; $Cs
|
||||
C712: 29 0F 79 AND #$0F
|
||||
C714: 85 3D 80 STA SLOT ; $0s
|
||||
C716: 0A 81 ASL A
|
||||
C717: 0A 82 ASL A
|
||||
C718: 0A 83 ASL A
|
||||
C719: 0A 84 ASL A
|
||||
85 FIN
|
||||
86
|
||||
C71A: 85 2B 87 STA SLOT16 ; $s0
|
||||
C71C: AA 88 TAX ; X holds now SLOT16
|
||||
C71D: 2C FF CF 89 BIT $CFFF
|
||||
C720: 20 A9 C9 90 JSR CARDDET
|
||||
C723: 90 03 91 BCC :INIT
|
||||
C725: A9 2F 92 LDA #$2F ; no card inserted
|
||||
C727: 00 93 BRK
|
||||
94
|
||||
C728: 20 00 C8 95 :INIT JSR INIT
|
||||
96
|
||||
97
|
||||
98 ********************************
|
||||
99 *
|
||||
100 * Install SD card driver
|
||||
101 *
|
||||
102 ********************************
|
||||
103
|
||||
104 DO DEBUG
|
||||
105
|
||||
106 * see if slot has a driver already
|
||||
107
|
||||
108 LDX $BF31 ; get devcnt
|
||||
109 INSTALL LDA $BF32,X ; get a devnum
|
||||
110 AND #$70 ; isolate slot
|
||||
111 CMP SLOT16 ; slot?
|
||||
112 BEQ :INSOUT ; yes, skip it
|
||||
113 DEX
|
||||
114 BPL INSTALL ; keep up the search
|
||||
115
|
||||
116 * restore the devnum to the list
|
||||
117
|
||||
118 LDX $BF31 ; get devcnt again
|
||||
119 CPX #$0D ; device table full?
|
||||
120 BNE :INST2
|
||||
121
|
||||
122 JSR $FF3A ; bell
|
||||
123 JMP :INSOUT ; do something!
|
||||
124
|
||||
125 :INST2 LDA $BF32-1,X ; move all entries down
|
||||
126 STA $BF32,X ; to make room at front
|
||||
127 DEX ; for a new entry
|
||||
128 BNE :INST2
|
||||
129 LDA #$04 ; ProFile type device
|
||||
130 ORA SLOT16
|
||||
131 STA $BF32 ; slot, drive 1 at top of list
|
||||
132 INC $BF31 ; update devcnt
|
||||
133
|
||||
134 * now insert the device driver vector
|
||||
135
|
||||
136 LDA SLOT
|
||||
137 ASL
|
||||
138 TAX
|
||||
139 LDA #<DRIVER
|
||||
140 STA $BF10,X ; write to driver table
|
||||
141 LDA #>DRIVER
|
||||
142 STA $BF11,X
|
||||
143 :INSOUT RTS
|
||||
144
|
||||
145
|
||||
146 ********************************
|
||||
147 *
|
||||
148 * Boot from SD card
|
||||
149 *
|
||||
150 ********************************
|
||||
151
|
||||
152 ELSE
|
||||
153
|
||||
C72B: C9 00 154 BOOT CMP #0 ; check for error
|
||||
C72D: F0 01 155 BEQ :BOOT1
|
||||
C72F: 00 156 BRK
|
||||
157
|
||||
C730: A9 01 158 :BOOT1 LDA #$01
|
||||
C732: 85 42 159 STA DCMD ; load command
|
||||
C734: A6 2B 160 LDX SLOT16
|
||||
C736: 85 43 161 STA $43 ; slot number
|
||||
C738: 64 44 162 STZ BUFFER ; buffer lo
|
||||
C73A: A9 08 163 LDA #$08
|
||||
C73C: 85 45 164 STA BUFFER+1 ; buffer hi
|
||||
C73E: 64 46 165 STZ BLOCK ; block lo
|
||||
C740: 64 47 166 STZ BLOCK+1 ; block hi
|
||||
C742: 2C FF CF 167 BIT $CFFF
|
||||
C745: 20 CF C9 168 JSR READ ; call driver
|
||||
C748: 4C 01 08 169 JMP $801 ; goto bootloader
|
||||
170
|
||||
171 FIN
|
||||
172
|
||||
173
|
||||
174 ********************************
|
||||
175 *
|
||||
176 * Jump table
|
||||
177 *
|
||||
178 ********************************
|
||||
179
|
||||
C74B: D8 180 DRIVER CLD
|
||||
181
|
||||
182 DO DEBUG
|
||||
183 LDA #$04
|
||||
184 STA SLOT
|
||||
185 LDA #$C4
|
||||
186 STA CURSLOT
|
||||
187 LDA #$40
|
||||
188
|
||||
189 ELSE
|
||||
C74C: 20 58 FF 190 JSR $FF58 ; find slot nr
|
||||
C74F: BA 191 TSX
|
||||
C750: BD 00 01 192 LDA $0100,X
|
||||
C753: 8D F8 07 193 STA CURSLOT ; $Cs
|
||||
C756: 29 0F 194 AND #$0F
|
||||
C758: 85 3D 195 STA SLOT ; $0s
|
||||
C75A: 0A 196 ASL A
|
||||
C75B: 0A 197 ASL A
|
||||
C75C: 0A 198 ASL A
|
||||
C75D: 0A 199 ASL A
|
||||
200 FIN
|
||||
201
|
||||
C75E: 85 2B 202 STA SLOT16 ; $s0
|
||||
C760: AA 203 TAX ; X holds now SLOT16
|
||||
C761: 2C FF CF 204 BIT $CFFF
|
||||
C764: 20 A9 C9 205 JSR CARDDET
|
||||
C767: 90 04 206 BCC :INITED
|
||||
C769: A9 2F 207 LDA #$2F ; no card inserted
|
||||
C76B: 80 1F 208 BRA :DONE
|
||||
209
|
||||
C76D: A9 80 210 :INITED LDA #INITED ; check for init
|
||||
C76F: 3C 83 C0 211 BIT SS,X
|
||||
C772: F0 29 212 BEQ :INIT
|
||||
213
|
||||
C774: A5 42 214 :CMD LDA DCMD ; get command
|
||||
C776: C9 00 215 CMP #0
|
||||
C778: F0 14 216 BEQ :STATUS
|
||||
C77A: C9 01 217 CMP #1
|
||||
C77C: F0 13 218 BEQ :READ
|
||||
C77E: C9 02 219 CMP #2
|
||||
C780: F0 12 220 BEQ :WRITE
|
||||
C782: C9 03 221 CMP #3
|
||||
C784: F0 11 222 BEQ :FORMAT
|
||||
C786: C9 FF 223 CMP #$FF
|
||||
C788: F0 10 224 BEQ :TEST
|
||||
C78A: A9 01 225 LDA #1 ; unknown command
|
||||
226
|
||||
C78C: 38 227 :DONE SEC
|
||||
C78D: 60 228 RTS
|
||||
229
|
||||
C78E: 4C C1 C9 230 :STATUS JMP STATUS
|
||||
C791: 4C CF C9 231 :READ JMP READ
|
||||
C794: 4C 38 CA 232 :WRITE JMP WRITE
|
||||
C797: 4C A9 CA 233 :FORMAT JMP FORMAT
|
||||
C79A: 4C AD CA 234 :TEST JMP TEST ; do device test
|
||||
C79D: 20 00 C8 235 :INIT JSR INIT
|
||||
C7A0: B0 EA 236 BCS :DONE ; init failure
|
||||
C7A2: 80 D0 237 BRA :CMD
|
||||
238
|
||||
239
|
||||
240 * Signature bytes
|
||||
241
|
||||
C7A4: 00 00 00 242 DS \ ; fill with zeroes
|
||||
C7A7: 00 00 00 00
|
||||
C7AB: 00 00 00 00
|
||||
C7AF: 00 00 00 00
|
||||
C7B3: 00 00 00 00
|
||||
C7B7: 00 00 00 00
|
||||
C7BB: 00 00 00 00
|
||||
C7BF: 00 00 00 00
|
||||
C7C3: 00 00 00 00
|
||||
C7C7: 00 00 00 00
|
||||
C7CB: 00 00 00 00
|
||||
C7CF: 00 00 00 00
|
||||
C7D3: 00 00 00 00
|
||||
C7D7: 00 00 00 00
|
||||
C7DB: 00 00 00 00
|
||||
C7DF: 00 00 00 00
|
||||
C7E3: 00 00 00 00
|
||||
C7E7: 00 00 00 00
|
||||
C7EB: 00 00 00 00
|
||||
C7EF: 00 00 00 00
|
||||
C7F3: 00 00 00 00
|
||||
C7F7: 00 00 00 00
|
||||
C7FB: 00 00 00 00
|
||||
C7FF: 00
|
||||
243 DS -4 ; locate to $xxFC
|
||||
C7FC: FF FF 244 DW $FFFF ; 65535 blocks
|
||||
C7FE: 17 245 DB $17 ; Status bits
|
||||
C7FF: 4B 246 DB #<DRIVER ; LSB of driver
|
||||
247
|
||||
248 ********************************
|
||||
249 *
|
||||
250 * Initialize SD card
|
||||
251 *
|
||||
252 * C Clear - No error
|
||||
253 * Set - Error
|
||||
254 * A $00 - No error
|
||||
255 * $27 - I/O error - Init failed
|
||||
256 * $2F - No card inserted
|
||||
257 *
|
||||
258 ********************************
|
||||
259
|
||||
C800: D8 260 INIT CLD
|
||||
C801: A9 03 261 LDA #$03 ; set SPI mode 3
|
||||
C803: 9D 81 C0 262 STA CTRL,X
|
||||
C806: BD 83 C0 263 LDA SS,X
|
||||
C809: 09 01 264 ORA #SS0 ; set CS high
|
||||
C80B: 9D 83 C0 265 STA SS,X
|
||||
C80E: A9 07 266 LDA #7
|
||||
C810: 9D 82 C0 267 STA DIV,X
|
||||
C813: A0 0A 268 LDY #10
|
||||
C815: A9 FF 269 LDA #DUMMY
|
||||
270
|
||||
C817: 9D 80 C0 271 :LOOP STA DATA,X
|
||||
C81A: 3C 81 C0 272 :WAIT BIT CTRL,X
|
||||
C81D: 10 FB 273 BPL :WAIT
|
||||
C81F: 88 274 DEY
|
||||
C820: D0 F5 275 BNE :LOOP ; do 10 times
|
||||
C822: BD 83 C0 276 LDA SS,X
|
||||
C825: 29 FE 277 AND #$FF!SS0 ; set CS low
|
||||
C827: 9D 83 C0 278 STA SS,X
|
||||
279
|
||||
C82A: A9 31 280 LDA #<CMD0 ; send CMD0
|
||||
C82C: 85 40 281 STA CMDLO
|
||||
C82E: A9 CB 282 LDA #>CMD0
|
||||
C830: 85 41 283 STA CMDHI
|
||||
C832: 20 EB C8 284 JSR CMD
|
||||
C835: 20 FF C8 285 JSR GETR1 ; get response
|
||||
C838: C9 01 286 CMP #$01
|
||||
C83A: D0 39 287 BNE :ERROR1 ; error!
|
||||
288
|
||||
C83C: A9 3D 289 LDA #<CMD8 ; send CMD8
|
||||
C83E: 85 40 290 STA CMDLO
|
||||
C840: A9 CB 291 LDA #>CMD8
|
||||
C842: 85 41 292 STA CMDHI
|
||||
C844: 20 EB C8 293 JSR CMD
|
||||
C847: 20 1A C9 294 JSR GETR3
|
||||
C84A: C9 01 295 CMP #$01
|
||||
C84C: D0 2A 296 BNE :SDV1 ; may be SD Ver. 1
|
||||
297
|
||||
298 * check for $01aa match!
|
||||
C84E: A9 49 299 :SDV2 LDA #<CMD55
|
||||
C850: 85 40 300 STA CMDLO
|
||||
C852: A9 CB 301 LDA #>CMD55
|
||||
C854: 85 41 302 STA CMDHI
|
||||
C856: 20 EB C8 303 JSR CMD
|
||||
C859: 20 FF C8 304 JSR GETR1
|
||||
C85C: A9 4F 305 LDA #<ACMD4140
|
||||
C85E: 85 40 306 STA CMDLO
|
||||
C860: A9 CB 307 LDA #>ACMD4140
|
||||
C862: 85 41 308 STA CMDHI
|
||||
C864: 20 EB C8 309 JSR CMD
|
||||
C867: 20 FF C8 310 JSR GETR1
|
||||
C86A: C9 01 311 CMP #$01
|
||||
C86C: F0 E0 312 BEQ :SDV2 ; wait for ready
|
||||
C86E: C9 00 313 CMP #$00
|
||||
C870: D0 03 314 BNE :ERROR1 ; error!
|
||||
315 * send CMD58
|
||||
316 * SD Ver. 2 initialized!
|
||||
C872: 4C B2 C8 317 JMP :BLOCKSZ
|
||||
318
|
||||
C875: 4C D9 C8 319 :ERROR1 JMP :IOERROR ; needed for far jump
|
||||
320
|
||||
C878: A9 49 321 :SDV1 LDA #<CMD55
|
||||
C87A: 85 40 322 STA CMDLO
|
||||
C87C: A9 CB 323 LDA #>CMD55
|
||||
C87E: 85 41 324 STA CMDHI
|
||||
C880: 20 EB C8 325 JSR CMD ; ignore response
|
||||
C883: A9 55 326 LDA #<ACMD410
|
||||
C885: 85 40 327 STA CMDLO
|
||||
C887: A9 CB 328 LDA #>ACMD410
|
||||
C889: 85 41 329 STA CMDHI
|
||||
C88B: 20 EB C8 330 JSR CMD
|
||||
C88E: 20 FF C8 331 JSR GETR1
|
||||
C891: C9 01 332 CMP #$01
|
||||
C893: F0 E3 333 BEQ :SDV1 ; wait for ready
|
||||
C895: C9 00 334 CMP #$00
|
||||
C897: D0 03 335 BNE :MMC ; may be MMC card
|
||||
336 * SD Ver. 1 initialized!
|
||||
C899: 4C B2 C8 337 JMP :BLOCKSZ
|
||||
338
|
||||
C89C: A9 37 339 :MMC LDA #<CMD1
|
||||
C89E: 85 40 340 STA CMDLO
|
||||
C8A0: A9 CB 341 LDA #>CMD1
|
||||
C8A2: 85 41 342 STA CMDHI
|
||||
C8A4: 20 EB C8 343 :LOOP1 JSR CMD
|
||||
C8A7: 20 FF C8 344 JSR GETR1
|
||||
C8AA: C9 01 345 CMP #$01
|
||||
C8AC: F0 F6 346 BEQ :LOOP1 ; wait for ready
|
||||
C8AE: C9 00 347 CMP #$00
|
||||
C8B0: D0 27 348 BNE :IOERROR ; error!
|
||||
349 * MMC Ver. 3 initialized!
|
||||
350
|
||||
C8B2: A9 43 351 :BLOCKSZ LDA #<CMD16
|
||||
C8B4: 85 40 352 STA CMDLO
|
||||
C8B6: A9 CB 353 LDA #>CMD16
|
||||
C8B8: 85 41 354 STA CMDHI
|
||||
C8BA: 20 EB C8 355 JSR CMD
|
||||
C8BD: 20 FF C8 356 JSR GETR1
|
||||
C8C0: C9 00 357 CMP #$00
|
||||
C8C2: D0 15 358 BNE :IOERROR ; error!
|
||||
359
|
||||
C8C4: BD 83 C0 360 :END LDA SS,X
|
||||
C8C7: 09 80 361 ORA #INITED ; initialized
|
||||
C8C9: 9D 83 C0 362 STA SS,X
|
||||
C8CC: BD 81 C0 363 LDA CTRL,X
|
||||
C8CF: 09 04 364 ORA #ECE ; enable 7MHz
|
||||
C8D1: 9D 81 C0 365 STA CTRL,X
|
||||
C8D4: 18 366 CLC ; all ok
|
||||
C8D5: A0 00 367 LDY #0
|
||||
C8D7: 90 03 368 BCC :END1
|
||||
C8D9: 38 369 :IOERROR SEC
|
||||
C8DA: A0 27 370 LDY #$27 ; init error
|
||||
C8DC: BD 83 C0 371 :END1 LDA SS,X ; set CS high
|
||||
C8DF: 09 01 372 ORA #SS0
|
||||
C8E1: 9D 83 C0 373 STA SS,X
|
||||
C8E4: A9 00 374 LDA #0 ; set div to 2
|
||||
C8E6: 9D 82 C0 375 STA DIV,X
|
||||
C8E9: 98 376 TYA ; retval in A
|
||||
C8EA: 60 377 RTS
|
||||
378
|
||||
379
|
||||
380 ********************************
|
||||
381 *
|
||||
382 * Send SD command
|
||||
383 * Call with command in CMDHI and CMDLO
|
||||
384 *
|
||||
385 ********************************
|
||||
386
|
||||
C8EB: 5A 387 CMD PHY
|
||||
C8EC: A0 00 388 LDY #0
|
||||
C8EE: B1 40 389 :LOOP LDA (CMDLO),Y
|
||||
C8F0: 9D 80 C0 390 STA DATA,X
|
||||
C8F3: 3C 81 C0 391 :WAIT BIT CTRL,X ; TC is in N
|
||||
C8F6: 10 FB 392 BPL :WAIT
|
||||
C8F8: C8 393 INY
|
||||
C8F9: C0 06 394 CPY #6
|
||||
C8FB: 90 F1 395 BCC :LOOP
|
||||
C8FD: 7A 396 PLY
|
||||
C8FE: 60 397 RTS
|
||||
398
|
||||
399
|
||||
400 ********************************
|
||||
401 *
|
||||
402 * Get R1
|
||||
403 * R1 is in A
|
||||
404 *
|
||||
405 ********************************
|
||||
406
|
||||
C8FF: A9 FF 407 GETR1 LDA #DUMMY
|
||||
C901: 9D 80 C0 408 STA DATA,X
|
||||
C904: 3C 81 C0 409 :WAIT BIT CTRL,X
|
||||
C907: 10 FB 410 BPL :WAIT
|
||||
C909: BD 80 C0 411 LDA DATA,X ; get response
|
||||
C90C: 85 3C 412 STA WORK ; save R1
|
||||
C90E: 29 80 413 AND #$80
|
||||
C910: D0 ED 414 BNE GETR1 ; wait for MSB=0
|
||||
C912: A9 FF 415 LDA #DUMMY
|
||||
C914: 9D 80 C0 416 STA DATA,X ; send another dummy
|
||||
C917: A5 3C 417 LDA WORK ; restore R1
|
||||
C919: 60 418 RTS
|
||||
419
|
||||
420
|
||||
421 ********************************
|
||||
422 *
|
||||
423 * Get R3
|
||||
424 * R1 is in A
|
||||
425 * R3 is in scratchpad ram
|
||||
426 *
|
||||
427 ********************************
|
||||
428
|
||||
C91A: 20 FF C8 429 GETR3 JSR GETR1 ; get R1 first
|
||||
C91D: 48 430 PHA ; save R1
|
||||
C91E: 5A 431 PHY ; save Y
|
||||
C91F: A0 04 432 LDY #04 ; load counter
|
||||
C921: A9 FF 433 :LOOP LDA #DUMMY ; send dummy
|
||||
C923: 9D 80 C0 434 STA DATA,X
|
||||
C926: 3C 81 C0 435 :WAIT BIT CTRL,X
|
||||
C929: 10 FB 436 BPL :WAIT
|
||||
C92B: BD 80 C0 437 LDA DATA,X
|
||||
C92E: 48 438 PHA
|
||||
C92F: 88 439 DEY
|
||||
C930: D0 EF 440 BNE :LOOP ; do 4 times
|
||||
C932: A4 3D 441 LDY SLOT
|
||||
C934: 68 442 PLA
|
||||
C935: 99 F8 05 443 STA R33,Y ; save R3
|
||||
C938: 68 444 PLA
|
||||
C939: 99 78 05 445 STA R32,Y
|
||||
C93C: 68 446 PLA
|
||||
C93D: 99 F8 04 447 STA R31,Y
|
||||
C940: 68 448 PLA
|
||||
C941: 99 78 04 449 STA R30,Y
|
||||
C944: 7A 450 PLY ; restore Y
|
||||
C945: A9 FF 451 LDA #DUMMY
|
||||
C947: 9D 80 C0 452 STA DATA,X ; send another dummy
|
||||
C94A: 68 453 PLA ; restore R1
|
||||
C94B: 60 454 RTS
|
||||
455
|
||||
456
|
||||
457 ********************************
|
||||
458 *
|
||||
459 * Calculate block address
|
||||
460 * Unit number is in $43 DSSS0000
|
||||
461 * Block no is in $46-47
|
||||
462 * Address is in R30-R33
|
||||
463 *
|
||||
464 ********************************
|
||||
465
|
||||
C94C: DA 466 GETBLOCK PHX ; save X
|
||||
C94D: 5A 467 PHY ; save Y
|
||||
C94E: A6 3D 468 LDX SLOT
|
||||
C950: A5 46 469 LDA BLOCK ; store block num
|
||||
C952: 9D F8 05 470 STA R33,X ; in R30-R33
|
||||
C955: A5 47 471 LDA BLOCK+1
|
||||
C957: 9D 78 05 472 STA R32,X
|
||||
C95A: A9 00 473 LDA #0
|
||||
C95C: 9D F8 04 474 STA R31,X
|
||||
C95F: 9D 78 04 475 STA R30,X
|
||||
476
|
||||
C962: A9 80 477 LDA #$80 ; drive number
|
||||
C964: 24 43 478 BIT $43
|
||||
C966: F0 05 479 BEQ :SHIFT ; D1
|
||||
C968: A9 01 480 LDA #1 ; D2
|
||||
C96A: 9D F8 04 481 STA R31,X
|
||||
482
|
||||
C96D: A0 09 483 :SHIFT LDY #9 ; ASL can't be used with Y
|
||||
C96F: 1E F8 05 484 :LOOP ASL R33,X ; mul block num
|
||||
C972: 3E 78 05 485 ROL R32,X ; by 512 to get
|
||||
C975: 3E F8 04 486 ROL R31,X ; real address
|
||||
C978: 3E 78 04 487 ROL R30,X
|
||||
C97B: 88 488 DEY
|
||||
C97C: D0 F1 489 BNE :LOOP
|
||||
C97E: 7A 490 PLY ; restore Y
|
||||
C97F: FA 491 PLX ; restore X
|
||||
C980: 60 492 RTS
|
||||
493
|
||||
494
|
||||
495 ********************************
|
||||
496 *
|
||||
497 * Send SD command
|
||||
498 * Cmd is in A
|
||||
499 *
|
||||
500 ********************************
|
||||
501
|
||||
C981: 5A 502 COMMAND PHY ; save Y
|
||||
C982: A4 3D 503 LDY SLOT
|
||||
C984: 9D 80 C0 504 STA DATA,X ; send command
|
||||
C987: B9 78 04 505 LDA R30,Y ; get arg from R30 on
|
||||
C98A: 9D 80 C0 506 STA DATA,X
|
||||
C98D: B9 F8 04 507 LDA R31,Y
|
||||
C990: 9D 80 C0 508 STA DATA,X
|
||||
C993: B9 78 05 509 LDA R32,Y
|
||||
C996: 9D 80 C0 510 STA DATA,X
|
||||
C999: B9 F8 05 511 LDA R33,Y
|
||||
C99C: 9D 80 C0 512 STA DATA,X
|
||||
C99F: A9 FF 513 LDA #DUMMY
|
||||
C9A1: 9D 80 C0 514 STA DATA,X ; dummy crc
|
||||
C9A4: 20 FF C8 515 JSR GETR1
|
||||
C9A7: 7A 516 PLY ; restore Y
|
||||
C9A8: 60 517 RTS
|
||||
518
|
||||
519
|
||||
520 ********************************
|
||||
521 *
|
||||
522 * Check for card detect
|
||||
523 *
|
||||
524 * C Clear - card in slot
|
||||
525 * Set - no card in slot
|
||||
526 *
|
||||
527 ********************************
|
||||
528
|
||||
C9A9: 48 529 CARDDET PHA
|
||||
C9AA: A9 40 530 LDA #CD ; 0: card in
|
||||
C9AC: 3C 83 C0 531 BIT SS,X ; 1: card out
|
||||
C9AF: 18 532 CLC
|
||||
C9B0: F0 01 533 BEQ :DONE ; card is in
|
||||
C9B2: 38 534 SEC ; card is out
|
||||
C9B3: 68 535 :DONE PLA
|
||||
C9B4: 60 536 RTS
|
||||
537
|
||||
538
|
||||
539 ********************************
|
||||
540 *
|
||||
541 * Check for write protect
|
||||
542 *
|
||||
543 * C Clear - card not protected
|
||||
544 * Set - card write protected
|
||||
545 *
|
||||
546 ********************************
|
||||
547
|
||||
C9B5: 48 548 WRPROT PHA
|
||||
C9B6: A9 20 549 LDA #WP ; 0: write enabled
|
||||
C9B8: 3C 83 C0 550 BIT SS,X ; 1: write disabled
|
||||
C9BB: 18 551 CLC
|
||||
C9BC: F0 01 552 BEQ :DONE
|
||||
C9BE: 38 553 SEC
|
||||
C9BF: 68 554 :DONE PLA
|
||||
C9C0: 60 555 RTS
|
||||
556
|
||||
557
|
||||
558 ********************************
|
||||
559 *
|
||||
560 * Status request
|
||||
561 * $43 Unit number DSSS000
|
||||
562 * $44-45 Unused
|
||||
563 * $46-47 Unused
|
||||
564 *
|
||||
565 * C Clear - No error
|
||||
566 * Set - Error
|
||||
567 * A $00 - No error
|
||||
568 * $2B - Card write protected
|
||||
569 * $2F - No card inserted
|
||||
570 * X - Blocks avail (low byte)
|
||||
571 * Y - Blocks avail (high byte)
|
||||
572 *
|
||||
573 ********************************
|
||||
574
|
||||
C9C1: A9 00 575 STATUS LDA #0 ; no error
|
||||
C9C3: A2 FF 576 LDX #$FF ; 32 MB partition
|
||||
C9C5: A0 FF 577 LDY #$FF
|
||||
578
|
||||
C9C7: 20 B5 C9 579 JSR WRPROT
|
||||
C9CA: 90 02 580 BCC :DONE
|
||||
C9CC: A9 2B 581 LDA #$2B ; card write protected
|
||||
582
|
||||
C9CE: 60 583 :DONE RTS
|
||||
584
|
||||
585
|
||||
586 ********************************
|
||||
587 *
|
||||
588 * Read 512 byte block
|
||||
589 * $43 Unit number DSSS0000
|
||||
590 * $44-45 Address (LO/HI) of buffer
|
||||
591 * $46-47 Block number (LO/HI)
|
||||
592 *
|
||||
593 * C Clear - No error
|
||||
594 * Set - Error
|
||||
595 * A $00 - No error
|
||||
596 * $27 - Bad block number
|
||||
597 *
|
||||
598 ********************************
|
||||
599
|
||||
C9CF: 20 4C C9 600 READ JSR GETBLOCK ; calc block address
|
||||
601
|
||||
C9D2: BD 83 C0 602 LDA SS,X ; enable /CS
|
||||
C9D5: 29 FE 603 AND #$FF!SS0
|
||||
C9D7: 9D 83 C0 604 STA SS,X
|
||||
C9DA: A9 51 605 LDA #$51 ; send CMD17
|
||||
C9DC: 20 81 C9 606 JSR COMMAND ; send command
|
||||
607
|
||||
C9DF: C9 00 608 CMP #0 ; check for error
|
||||
C9E1: D0 50 609 BNE :ERROR
|
||||
610
|
||||
C9E3: A9 FF 611 :GETTOK LDA #DUMMY ; get data token
|
||||
C9E5: 9D 80 C0 612 STA DATA,X
|
||||
C9E8: BD 80 C0 613 LDA DATA,X ; get response
|
||||
C9EB: C9 FE 614 CMP #$FE
|
||||
C9ED: D0 F4 615 BNE :GETTOK ; wait for $FE
|
||||
616
|
||||
C9EF: A0 02 617 LDY #2 ; read data from card
|
||||
C9F1: BD 81 C0 618 LDA CTRL,X ; enable FRX
|
||||
C9F4: 09 10 619 ORA #FRX
|
||||
C9F6: 9D 81 C0 620 STA CTRL,X
|
||||
C9F9: A9 FF 621 LDA #DUMMY
|
||||
C9FB: 9D 80 C0 622 STA DATA,X
|
||||
C9FE: 64 3C 623 :LOOPY STZ WORK
|
||||
CA00: BD 80 C0 624 :LOOPW LDA DATA,X
|
||||
CA03: 92 44 625 STA (BUFFER)
|
||||
CA05: E6 44 626 INC BUFFER
|
||||
CA07: D0 02 627 BNE :INW
|
||||
CA09: E6 45 628 INC BUFFER+1 ; inc msb on page boundary
|
||||
CA0B: E6 3C 629 :INW INC WORK
|
||||
CA0D: D0 F1 630 BNE :LOOPW
|
||||
CA0F: 88 631 DEY
|
||||
CA10: D0 EC 632 BNE :LOOPY
|
||||
633
|
||||
CA12: BD 80 C0 634 :CRC LDA DATA,X ; read two bytes crc
|
||||
CA15: BD 80 C0 635 LDA DATA,X ; and ignore
|
||||
CA18: BD 80 C0 636 LDA DATA,X ; read a dummy byte
|
||||
637
|
||||
CA1B: BD 81 C0 638 LDA CTRL,X ; disable FRX
|
||||
CA1E: 29 EF 639 AND #$FF!FRX
|
||||
CA20: 9D 81 C0 640 STA CTRL,X
|
||||
CA23: 18 641 CLC ; no error
|
||||
CA24: A9 00 642 LDA #0
|
||||
643
|
||||
CA26: 08 644 :DONE PHP
|
||||
CA27: 48 645 PHA
|
||||
CA28: BD 83 C0 646 LDA SS,X
|
||||
CA2B: 09 01 647 ORA #SS0
|
||||
CA2D: 9D 83 C0 648 STA SS,X ; disable /CS
|
||||
CA30: 68 649 PLA
|
||||
CA31: 28 650 PLP
|
||||
CA32: 60 651 RTS
|
||||
652
|
||||
CA33: 38 653 :ERROR SEC ; an error occured
|
||||
CA34: A9 27 654 LDA #$27
|
||||
CA36: 80 EE 655 BRA :DONE
|
||||
656
|
||||
657
|
||||
658 ********************************
|
||||
659 *
|
||||
660 * Write 512 byte block
|
||||
661 * $43 Unit number DSSS0000
|
||||
662 * $44-45 Address (LO/HI) of buffer
|
||||
663 * $46-47 Block number (LO/HI)
|
||||
664 *
|
||||
665 * C Clear - No error
|
||||
666 * Set - Error
|
||||
667 * A $00 - No error
|
||||
668 * $27 - I/O error or bad block number
|
||||
669 * $2B - Card write protected
|
||||
670 *
|
||||
671 ********************************
|
||||
672
|
||||
CA38: 20 B5 C9 673 WRITE JSR WRPROT
|
||||
CA3B: B0 67 674 BCS :WPERROR ; card write protected
|
||||
675
|
||||
CA3D: 20 4C C9 676 JSR GETBLOCK ; calc block address
|
||||
677
|
||||
CA40: BD 83 C0 678 LDA SS,X ; enable /CS
|
||||
CA43: 29 FE 679 AND #$FF!SS0
|
||||
CA45: 9D 83 C0 680 STA SS,X
|
||||
CA48: A9 58 681 LDA #$58 ; send CMD24
|
||||
CA4A: 20 81 C9 682 JSR COMMAND ; send command
|
||||
683
|
||||
CA4D: C9 00 684 CMP #0 ; check for error
|
||||
CA4F: D0 4E 685 BNE :IOERROR
|
||||
686
|
||||
CA51: A9 FF 687 LDA #DUMMY
|
||||
CA53: 9D 80 C0 688 STA DATA,X ; send dummy
|
||||
CA56: A9 FE 689 LDA #$FE
|
||||
CA58: 9D 80 C0 690 STA DATA,X ; send data token
|
||||
691
|
||||
CA5B: A0 02 692 LDY #2 ; send data to card
|
||||
CA5D: 64 3C 693 :LOOPY STZ WORK
|
||||
CA5F: B2 44 694 :LOOPW LDA (BUFFER)
|
||||
CA61: 9D 80 C0 695 STA DATA,X
|
||||
CA64: E6 44 696 INC BUFFER
|
||||
CA66: D0 02 697 BNE :INW
|
||||
CA68: E6 45 698 INC BUFFER+1 ; inc msb on page boundary
|
||||
CA6A: E6 3C 699 :INW INC WORK
|
||||
CA6C: D0 F1 700 BNE :LOOPW
|
||||
CA6E: 88 701 DEY
|
||||
CA6F: D0 EC 702 BNE :LOOPY
|
||||
703
|
||||
CA71: 9D 80 C0 704 :CRC STA DATA,X ; send 2 dummy crc bytes
|
||||
CA74: 9D 80 C0 705 STA DATA,X
|
||||
706
|
||||
CA77: 9D 80 C0 707 STA DATA,X ; get data response
|
||||
CA7A: BD 80 C0 708 LDA DATA,X
|
||||
CA7D: 29 1F 709 AND #$1F
|
||||
CA7F: C9 05 710 CMP #$05
|
||||
CA81: D0 1C 711 BNE :IOERROR ; check for write error
|
||||
CA83: 18 712 CLC ; no error
|
||||
CA84: A9 00 713 LDA #0
|
||||
714
|
||||
CA86: 08 715 :DONE PHP
|
||||
CA87: 48 716 PHA
|
||||
CA88: A9 FF 717 :WAIT LDA #DUMMY
|
||||
CA8A: 9D 80 C0 718 STA DATA,X ; wait for write cycle
|
||||
CA8D: BD 80 C0 719 LDA DATA,X ; to complete
|
||||
CA90: C9 00 720 CMP #$00
|
||||
CA92: F0 F4 721 BEQ :WAIT
|
||||
722
|
||||
CA94: BD 83 C0 723 LDA SS,X ; disable /CS
|
||||
CA97: 09 01 724 ORA #SS0
|
||||
CA99: 9D 83 C0 725 STA SS,X
|
||||
CA9C: 68 726 PLA
|
||||
CA9D: 28 727 PLP
|
||||
CA9E: 60 728 RTS
|
||||
729
|
||||
CA9F: 38 730 :IOERROR SEC ; an error occured
|
||||
CAA0: A9 27 731 LDA #$27
|
||||
CAA2: 80 E2 732 BRA :DONE
|
||||
733
|
||||
CAA4: 38 734 :WPERROR SEC
|
||||
CAA5: A9 2B 735 LDA #$2B
|
||||
CAA7: 80 DD 736 BRA :DONE
|
||||
737
|
||||
738
|
||||
739
|
||||
740 ********************************
|
||||
741 *
|
||||
742 * Format
|
||||
743 * not supported!
|
||||
744 *
|
||||
745 ********************************
|
||||
746
|
||||
CAA9: 38 747 FORMAT SEC
|
||||
CAAA: A9 01 748 LDA #$01 ; invalid command
|
||||
CAAC: 60 749 RTS
|
||||
750
|
||||
751
|
||||
752 ********************************
|
||||
753 *
|
||||
754 * Test routine
|
||||
755 *
|
||||
756 ********************************
|
||||
757
|
||||
758 TEST
|
||||
759
|
||||
760 * get buffer
|
||||
CAAD: A4 3D 761 LDY SLOT
|
||||
CAAF: A9 02 762 LDA #2 ; get 512 byte buffer
|
||||
CAB1: 20 F5 BE 763 JSR $BEF5 ; call GETBUFR
|
||||
CAB4: B0 79 764 BCS :ERROR
|
||||
CAB6: 99 F8 06 765 STA RAM1,Y
|
||||
CAB9: 85 45 766 STA BUFFER+1
|
||||
CABB: A9 00 767 LDA #0
|
||||
CABD: 99 78 06 768 STA RAM0,Y
|
||||
CAC0: 85 44 769 STA BUFFER
|
||||
770
|
||||
771 * fill buffer
|
||||
CAC2: A0 00 772 LDY #0
|
||||
CAC4: 98 773 :LOOP TYA
|
||||
CAC5: 91 44 774 STA (BUFFER),Y
|
||||
CAC7: C8 775 INY
|
||||
CAC8: D0 FA 776 BNE :LOOP
|
||||
CACA: E6 45 777 INC BUFFER+1
|
||||
CACC: 98 778 :LOOP1 TYA
|
||||
CACD: 91 44 779 STA (BUFFER),Y
|
||||
CACF: C8 780 INY
|
||||
CAD0: D0 FA 781 BNE :LOOP1
|
||||
782
|
||||
783 * write to card
|
||||
CAD2: A9 02 784 LDA #2 ; write cmd
|
||||
CAD4: A4 3D 785 LDY SLOT
|
||||
CAD6: 85 42 786 STA DCMD
|
||||
CAD8: AD 78 06 787 LDA RAM0 ; buffer address
|
||||
CADB: 85 44 788 STA BUFFER
|
||||
CADD: B9 F8 06 789 LDA RAM1,Y
|
||||
CAE0: 85 45 790 STA BUFFER+1
|
||||
CAE2: 64 46 791 STZ BLOCK ; block number
|
||||
CAE4: 64 47 792 STZ BLOCK+1
|
||||
CAE6: A6 2B 793 LDX SLOT16
|
||||
CAE8: 20 4B C7 794 JSR DRIVER
|
||||
CAEB: B0 42 795 BCS :ERROR
|
||||
796
|
||||
797 * read from card
|
||||
CAED: A9 01 798 LDA #1 ; read cmd
|
||||
CAEF: A4 3D 799 LDY SLOT
|
||||
CAF1: 85 42 800 STA DCMD
|
||||
CAF3: B9 78 06 801 LDA RAM0,Y ; buffer address
|
||||
CAF6: 85 44 802 STA BUFFER
|
||||
CAF8: B9 F8 06 803 LDA RAM1,Y
|
||||
CAFB: 85 45 804 STA BUFFER+1
|
||||
CAFD: 64 46 805 STZ BLOCK ; block number
|
||||
CAFF: 64 47 806 STZ BLOCK+1
|
||||
CB01: A6 2B 807 LDX SLOT16
|
||||
CB03: 20 4B C7 808 JSR DRIVER
|
||||
CB06: B0 27 809 BCS :ERROR
|
||||
810
|
||||
811 * check for errors
|
||||
CB08: A4 3D 812 LDY SLOT
|
||||
CB0A: B9 78 06 813 LDA RAM0,Y ; buffer address
|
||||
CB0D: 85 44 814 STA BUFFER
|
||||
CB0F: B9 F8 06 815 LDA RAM1,Y
|
||||
CB12: 85 45 816 STA BUFFER+1
|
||||
CB14: A0 00 817 LDY #0
|
||||
CB16: 98 818 :LOOP2 TYA
|
||||
CB17: D1 44 819 CMP (BUFFER),Y
|
||||
CB19: D0 15 820 BNE :ERRCMP ; error in buffer
|
||||
CB1B: C8 821 INY
|
||||
CB1C: D0 F8 822 BNE :LOOP2
|
||||
CB1E: E6 45 823 INC BUFFER+1
|
||||
CB20: 98 824 :LOOP3 TYA
|
||||
CB21: D1 44 825 CMP (BUFFER),Y
|
||||
CB23: D0 0B 826 BNE :ERRCMP
|
||||
CB25: C8 827 INY
|
||||
CB26: D0 F8 828 BNE :LOOP3
|
||||
829
|
||||
830 * free buffer
|
||||
CB28: 20 F8 BE 831 JSR $BEF8 ; call FREEBUFR
|
||||
CB2B: 18 832 CLC
|
||||
CB2C: A9 00 833 LDA #0
|
||||
CB2E: 60 834 RTS
|
||||
835
|
||||
CB2F: 00 836 :ERROR BRK
|
||||
CB30: 00 837 :ERRCMP BRK
|
||||
838
|
||||
839
|
||||
CB31: 40 00 00 840 CMD0 HEX 400000
|
||||
CB34: 00 00 95 841 HEX 000095
|
||||
CB37: 41 00 00 842 CMD1 HEX 410000
|
||||
CB3A: 00 00 F9 843 HEX 0000F9
|
||||
CB3D: 48 00 00 844 CMD8 HEX 480000
|
||||
CB40: 01 AA 87 845 HEX 01AA87
|
||||
CB43: 50 00 00 846 CMD16 HEX 500000
|
||||
CB46: 02 00 FF 847 HEX 0200FF
|
||||
CB49: 77 00 00 848 CMD55 HEX 770000
|
||||
CB4C: 00 00 65 849 HEX 000065
|
||||
CB4F: 69 40 00 850 ACMD4140 HEX 694000
|
||||
CB52: 00 00 77 851 HEX 000077
|
||||
CB55: 69 00 00 852 ACMD410 HEX 690000
|
||||
CB58: 00 00 FF 853 HEX 0000FF
|
||||
|
||||
|
||||
--End assembly, 1115 bytes, Errors: 0
|
||||
|
||||
|
||||
Symbol table - alphabetical order:
|
||||
|
||||
ACMD410 =$CB55 ACMD4140=$CB4F BLOCK =$46 ? BOOT =$C72B
|
||||
BUFFER =$44 CARDDET =$C9A9 CD =$40 CMD =$C8EB
|
||||
CMD0 =$CB31 CMD1 =$CB37 CMD16 =$CB43 CMD55 =$CB49
|
||||
CMD8 =$CB3D CMDHI =$41 CMDLO =$40 COMMAND =$C981
|
||||
CTRL =$C081 CURSLOT =$07F8 DATA =$C080 DCMD =$42
|
||||
DEBUG =$00 DIV =$C082 DRIVER =$C74B DUMMY =$FF
|
||||
ECE =$04 FORMAT =$CAA9 FRX =$10 GETBLOCK=$C94C
|
||||
GETR1 =$C8FF GETR3 =$C91A INIT =$C800 INITED =$80
|
||||
R30 =$0478 R31 =$04F8 R32 =$0578 R33 =$05F8
|
||||
RAM0 =$0678 RAM1 =$06F8 READ =$C9CF SLOT =$3D
|
||||
SLOT16 =$2B SS =$C083 SS0 =$01 STATUS =$C9C1
|
||||
TEST =$CAAD WORK =$3C WP =$20 WRITE =$CA38
|
||||
WRPROT =$C9B5
|
||||
|
||||
|
||||
Symbol table - numerical order:
|
||||
|
||||
DEBUG =$00 SS0 =$01 ECE =$04 FRX =$10
|
||||
WP =$20 SLOT16 =$2B WORK =$3C SLOT =$3D
|
||||
CMDLO =$40 CD =$40 CMDHI =$41 DCMD =$42
|
||||
BUFFER =$44 BLOCK =$46 INITED =$80 DUMMY =$FF
|
||||
R30 =$0478 R31 =$04F8 R32 =$0578 R33 =$05F8
|
||||
RAM0 =$0678 RAM1 =$06F8 CURSLOT =$07F8 DATA =$C080
|
||||
CTRL =$C081 DIV =$C082 SS =$C083 ? BOOT =$C72B
|
||||
DRIVER =$C74B INIT =$C800 CMD =$C8EB GETR1 =$C8FF
|
||||
GETR3 =$C91A GETBLOCK=$C94C COMMAND =$C981 CARDDET =$C9A9
|
||||
WRPROT =$C9B5 STATUS =$C9C1 READ =$C9CF WRITE =$CA38
|
||||
FORMAT =$CAA9 TEST =$CAAD CMD0 =$CB31 CMD1 =$CB37
|
||||
CMD8 =$CB3D CMD16 =$CB43 CMD55 =$CB49 ACMD4140=$CB4F
|
||||
ACMD410 =$CB55
|
||||
|
||||
BIN
AppleIISd.pdf
BIN
AppleIISd.pdf
Binary file not shown.
854
AppleIISd.s
854
AppleIISd.s
|
|
@ -1,854 +0,0 @@
|
|||
********************************
|
||||
*
|
||||
* Apple][Sd Firmware
|
||||
* Version 0.7
|
||||
*
|
||||
* (c) Florian Reitz, 2017
|
||||
*
|
||||
* X register usually contains SLOT16
|
||||
* Y register is used for counting or SLOT
|
||||
*
|
||||
********************************
|
||||
|
||||
DAT
|
||||
|
||||
XC ; enable 65C02 code
|
||||
DEBUG = 0
|
||||
DO DEBUG
|
||||
ORG $8000
|
||||
ELSE
|
||||
ORG $C700 ; Expansion ROM
|
||||
FIN
|
||||
|
||||
* Memory defines
|
||||
|
||||
SLOT16 = $2B ; $s0 -> slot * 16
|
||||
WORK = $3C
|
||||
SLOT = $3D ; $0s
|
||||
CMDLO = $40
|
||||
CMDHI = $41
|
||||
|
||||
DCMD = $42 ; Command code
|
||||
BUFFER = $44 ; Buffer address
|
||||
BLOCK = $46 ; Block number
|
||||
|
||||
CURSLOT = $07F8 ; $Cs
|
||||
DATA = $C080
|
||||
CTRL = DATA+1
|
||||
DIV = DATA+2
|
||||
SS = DATA+3
|
||||
R30 = $0478
|
||||
R31 = $04F8
|
||||
R32 = $0578
|
||||
R33 = $05F8
|
||||
RAM0 = $0678
|
||||
RAM1 = $06F8
|
||||
|
||||
* Constants
|
||||
|
||||
DUMMY = $FF
|
||||
FRX = $10 ; CTRL register
|
||||
ECE = $04
|
||||
SS0 = $01 ; SS register
|
||||
WP = $20
|
||||
CD = $40
|
||||
INITED = $80
|
||||
|
||||
|
||||
* signature bytes
|
||||
|
||||
LDX #$20
|
||||
LDY #$00
|
||||
LDX #$03
|
||||
LDY #$FF ; neither 5.25 nor Smartport
|
||||
|
||||
* find slot nr
|
||||
|
||||
DO DEBUG
|
||||
LDA #$04
|
||||
STA SLOT
|
||||
LDA #$C4
|
||||
STA CURSLOT
|
||||
LDA #$40
|
||||
|
||||
ELSE
|
||||
JSR $FF58
|
||||
TSX
|
||||
LDA $0100,X
|
||||
STA CURSLOT ; $Cs
|
||||
AND #$0F
|
||||
STA SLOT ; $0s
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
FIN
|
||||
|
||||
STA SLOT16 ; $s0
|
||||
TAX ; X holds now SLOT16
|
||||
BIT $CFFF
|
||||
JSR CARDDET
|
||||
BCC :INIT
|
||||
LDA #$2F ; no card inserted
|
||||
BRK
|
||||
|
||||
:INIT JSR INIT
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Install SD card driver
|
||||
*
|
||||
********************************
|
||||
|
||||
DO DEBUG
|
||||
|
||||
* see if slot has a driver already
|
||||
|
||||
LDX $BF31 ; get devcnt
|
||||
INSTALL LDA $BF32,X ; get a devnum
|
||||
AND #$70 ; isolate slot
|
||||
CMP SLOT16 ; slot?
|
||||
BEQ :INSOUT ; yes, skip it
|
||||
DEX
|
||||
BPL INSTALL ; keep up the search
|
||||
|
||||
* restore the devnum to the list
|
||||
|
||||
LDX $BF31 ; get devcnt again
|
||||
CPX #$0D ; device table full?
|
||||
BNE :INST2
|
||||
|
||||
JSR $FF3A ; bell
|
||||
JMP :INSOUT ; do something!
|
||||
|
||||
:INST2 LDA $BF32-1,X ; move all entries down
|
||||
STA $BF32,X ; to make room at front
|
||||
DEX ; for a new entry
|
||||
BNE :INST2
|
||||
LDA #$04 ; ProFile type device
|
||||
ORA SLOT16
|
||||
STA $BF32 ; slot, drive 1 at top of list
|
||||
INC $BF31 ; update devcnt
|
||||
|
||||
* now insert the device driver vector
|
||||
|
||||
LDA SLOT
|
||||
ASL
|
||||
TAX
|
||||
LDA #<DRIVER
|
||||
STA $BF10,X ; write to driver table
|
||||
LDA #>DRIVER
|
||||
STA $BF11,X
|
||||
:INSOUT RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Boot from SD card
|
||||
*
|
||||
********************************
|
||||
|
||||
ELSE
|
||||
|
||||
BOOT CMP #0 ; check for error
|
||||
BEQ :BOOT1
|
||||
BRK
|
||||
|
||||
:BOOT1 LDA #$01
|
||||
STA DCMD ; load command
|
||||
LDX SLOT16
|
||||
STA $43 ; slot number
|
||||
STZ BUFFER ; buffer lo
|
||||
LDA #$08
|
||||
STA BUFFER+1 ; buffer hi
|
||||
STZ BLOCK ; block lo
|
||||
STZ BLOCK+1 ; block hi
|
||||
BIT $CFFF
|
||||
JSR READ ; call driver
|
||||
JMP $801 ; goto bootloader
|
||||
|
||||
FIN
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Jump table
|
||||
*
|
||||
********************************
|
||||
|
||||
DRIVER CLD
|
||||
|
||||
DO DEBUG
|
||||
LDA #$04
|
||||
STA SLOT
|
||||
LDA #$C4
|
||||
STA CURSLOT
|
||||
LDA #$40
|
||||
|
||||
ELSE
|
||||
JSR $FF58 ; find slot nr
|
||||
TSX
|
||||
LDA $0100,X
|
||||
STA CURSLOT ; $Cs
|
||||
AND #$0F
|
||||
STA SLOT ; $0s
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
FIN
|
||||
|
||||
STA SLOT16 ; $s0
|
||||
TAX ; X holds now SLOT16
|
||||
BIT $CFFF
|
||||
JSR CARDDET
|
||||
BCC :INITED
|
||||
LDA #$2F ; no card inserted
|
||||
BRA :DONE
|
||||
|
||||
:INITED LDA #INITED ; check for init
|
||||
BIT SS,X
|
||||
BEQ :INIT
|
||||
|
||||
:CMD LDA DCMD ; get command
|
||||
CMP #0
|
||||
BEQ :STATUS
|
||||
CMP #1
|
||||
BEQ :READ
|
||||
CMP #2
|
||||
BEQ :WRITE
|
||||
CMP #3
|
||||
BEQ :FORMAT
|
||||
CMP #$FF
|
||||
BEQ :TEST
|
||||
LDA #1 ; unknown command
|
||||
|
||||
:DONE SEC
|
||||
RTS
|
||||
|
||||
:STATUS JMP STATUS
|
||||
:READ JMP READ
|
||||
:WRITE JMP WRITE
|
||||
:FORMAT JMP FORMAT
|
||||
:TEST JMP TEST ; do device test
|
||||
:INIT JSR INIT
|
||||
BCS :DONE ; init failure
|
||||
BRA :CMD
|
||||
|
||||
|
||||
* Signature bytes
|
||||
|
||||
DS \ ; fill with zeroes
|
||||
DS -4 ; locate to $xxFC
|
||||
DW $FFFF ; 65535 blocks
|
||||
DB $17 ; Status bits
|
||||
DB #<DRIVER ; LSB of driver
|
||||
|
||||
********************************
|
||||
*
|
||||
* Initialize SD card
|
||||
*
|
||||
* C Clear - No error
|
||||
* Set - Error
|
||||
* A $00 - No error
|
||||
* $27 - I/O error - Init failed
|
||||
* $2F - No card inserted
|
||||
*
|
||||
********************************
|
||||
|
||||
INIT CLD
|
||||
LDA #$03 ; set SPI mode 3
|
||||
STA CTRL,X
|
||||
LDA SS,X
|
||||
ORA #SS0 ; set CS high
|
||||
STA SS,X
|
||||
LDA #7
|
||||
STA DIV,X
|
||||
LDY #10
|
||||
LDA #DUMMY
|
||||
|
||||
:LOOP STA DATA,X
|
||||
:WAIT BIT CTRL,X
|
||||
BPL :WAIT
|
||||
DEY
|
||||
BNE :LOOP ; do 10 times
|
||||
LDA SS,X
|
||||
AND #$FF!SS0 ; set CS low
|
||||
STA SS,X
|
||||
|
||||
LDA #<CMD0 ; send CMD0
|
||||
STA CMDLO
|
||||
LDA #>CMD0
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR1 ; get response
|
||||
CMP #$01
|
||||
BNE :ERROR1 ; error!
|
||||
|
||||
LDA #<CMD8 ; send CMD8
|
||||
STA CMDLO
|
||||
LDA #>CMD8
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR3
|
||||
CMP #$01
|
||||
BNE :SDV1 ; may be SD Ver. 1
|
||||
|
||||
* check for $01aa match!
|
||||
:SDV2 LDA #<CMD55
|
||||
STA CMDLO
|
||||
LDA #>CMD55
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR1
|
||||
LDA #<ACMD4140
|
||||
STA CMDLO
|
||||
LDA #>ACMD4140
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ :SDV2 ; wait for ready
|
||||
CMP #$00
|
||||
BNE :ERROR1 ; error!
|
||||
* send CMD58
|
||||
* SD Ver. 2 initialized!
|
||||
JMP :BLOCKSZ
|
||||
|
||||
:ERROR1 JMP :IOERROR ; needed for far jump
|
||||
|
||||
:SDV1 LDA #<CMD55
|
||||
STA CMDLO
|
||||
LDA #>CMD55
|
||||
STA CMDHI
|
||||
JSR CMD ; ignore response
|
||||
LDA #<ACMD410
|
||||
STA CMDLO
|
||||
LDA #>ACMD410
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ :SDV1 ; wait for ready
|
||||
CMP #$00
|
||||
BNE :MMC ; may be MMC card
|
||||
* SD Ver. 1 initialized!
|
||||
JMP :BLOCKSZ
|
||||
|
||||
:MMC LDA #<CMD1
|
||||
STA CMDLO
|
||||
LDA #>CMD1
|
||||
STA CMDHI
|
||||
:LOOP1 JSR CMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ :LOOP1 ; wait for ready
|
||||
CMP #$00
|
||||
BNE :IOERROR ; error!
|
||||
* MMC Ver. 3 initialized!
|
||||
|
||||
:BLOCKSZ LDA #<CMD16
|
||||
STA CMDLO
|
||||
LDA #>CMD16
|
||||
STA CMDHI
|
||||
JSR CMD
|
||||
JSR GETR1
|
||||
CMP #$00
|
||||
BNE :IOERROR ; error!
|
||||
|
||||
:END LDA SS,X
|
||||
ORA #INITED ; initialized
|
||||
STA SS,X
|
||||
LDA CTRL,X
|
||||
ORA #ECE ; enable 7MHz
|
||||
STA CTRL,X
|
||||
CLC ; all ok
|
||||
LDY #0
|
||||
BCC :END1
|
||||
:IOERROR SEC
|
||||
LDY #$27 ; init error
|
||||
:END1 LDA SS,X ; set CS high
|
||||
ORA #SS0
|
||||
STA SS,X
|
||||
LDA #0 ; set div to 2
|
||||
STA DIV,X
|
||||
TYA ; retval in A
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Send SD command
|
||||
* Call with command in CMDHI and CMDLO
|
||||
*
|
||||
********************************
|
||||
|
||||
CMD PHY
|
||||
LDY #0
|
||||
:LOOP LDA (CMDLO),Y
|
||||
STA DATA,X
|
||||
:WAIT BIT CTRL,X ; TC is in N
|
||||
BPL :WAIT
|
||||
INY
|
||||
CPY #6
|
||||
BCC :LOOP
|
||||
PLY
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Get R1
|
||||
* R1 is in A
|
||||
*
|
||||
********************************
|
||||
|
||||
GETR1 LDA #DUMMY
|
||||
STA DATA,X
|
||||
:WAIT BIT CTRL,X
|
||||
BPL :WAIT
|
||||
LDA DATA,X ; get response
|
||||
STA WORK ; save R1
|
||||
AND #$80
|
||||
BNE GETR1 ; wait for MSB=0
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send another dummy
|
||||
LDA WORK ; restore R1
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Get R3
|
||||
* R1 is in A
|
||||
* R3 is in scratchpad ram
|
||||
*
|
||||
********************************
|
||||
|
||||
GETR3 JSR GETR1 ; get R1 first
|
||||
PHA ; save R1
|
||||
PHY ; save Y
|
||||
LDY #04 ; load counter
|
||||
:LOOP LDA #DUMMY ; send dummy
|
||||
STA DATA,X
|
||||
:WAIT BIT CTRL,X
|
||||
BPL :WAIT
|
||||
LDA DATA,X
|
||||
PHA
|
||||
DEY
|
||||
BNE :LOOP ; do 4 times
|
||||
LDY SLOT
|
||||
PLA
|
||||
STA R33,Y ; save R3
|
||||
PLA
|
||||
STA R32,Y
|
||||
PLA
|
||||
STA R31,Y
|
||||
PLA
|
||||
STA R30,Y
|
||||
PLY ; restore Y
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send another dummy
|
||||
PLA ; restore R1
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Calculate block address
|
||||
* Unit number is in $43 DSSS0000
|
||||
* Block no is in $46-47
|
||||
* Address is in R30-R33
|
||||
*
|
||||
********************************
|
||||
|
||||
GETBLOCK PHX ; save X
|
||||
PHY ; save Y
|
||||
LDX SLOT
|
||||
LDA BLOCK ; store block num
|
||||
STA R33,X ; in R30-R33
|
||||
LDA BLOCK+1
|
||||
STA R32,X
|
||||
LDA #0
|
||||
STA R31,X
|
||||
STA R30,X
|
||||
|
||||
LDA #$80 ; drive number
|
||||
BIT $43
|
||||
BEQ :SHIFT ; D1
|
||||
LDA #1 ; D2
|
||||
STA R31,X
|
||||
|
||||
:SHIFT LDY #9 ; ASL can't be used with Y
|
||||
:LOOP ASL R33,X ; mul block num
|
||||
ROL R32,X ; by 512 to get
|
||||
ROL R31,X ; real address
|
||||
ROL R30,X
|
||||
DEY
|
||||
BNE :LOOP
|
||||
PLY ; restore Y
|
||||
PLX ; restore X
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Send SD command
|
||||
* Cmd is in A
|
||||
*
|
||||
********************************
|
||||
|
||||
COMMAND PHY ; save Y
|
||||
LDY SLOT
|
||||
STA DATA,X ; send command
|
||||
LDA R30,Y ; get arg from R30 on
|
||||
STA DATA,X
|
||||
LDA R31,Y
|
||||
STA DATA,X
|
||||
LDA R32,Y
|
||||
STA DATA,X
|
||||
LDA R33,Y
|
||||
STA DATA,X
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; dummy crc
|
||||
JSR GETR1
|
||||
PLY ; restore Y
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Check for card detect
|
||||
*
|
||||
* C Clear - card in slot
|
||||
* Set - no card in slot
|
||||
*
|
||||
********************************
|
||||
|
||||
CARDDET PHA
|
||||
LDA #CD ; 0: card in
|
||||
BIT SS,X ; 1: card out
|
||||
CLC
|
||||
BEQ :DONE ; card is in
|
||||
SEC ; card is out
|
||||
:DONE PLA
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Check for write protect
|
||||
*
|
||||
* C Clear - card not protected
|
||||
* Set - card write protected
|
||||
*
|
||||
********************************
|
||||
|
||||
WRPROT PHA
|
||||
LDA #WP ; 0: write enabled
|
||||
BIT SS,X ; 1: write disabled
|
||||
CLC
|
||||
BEQ :DONE
|
||||
SEC
|
||||
:DONE PLA
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Status request
|
||||
* $43 Unit number DSSS000
|
||||
* $44-45 Unused
|
||||
* $46-47 Unused
|
||||
*
|
||||
* C Clear - No error
|
||||
* Set - Error
|
||||
* A $00 - No error
|
||||
* $2B - Card write protected
|
||||
* $2F - No card inserted
|
||||
* X - Blocks avail (low byte)
|
||||
* Y - Blocks avail (high byte)
|
||||
*
|
||||
********************************
|
||||
|
||||
STATUS LDA #0 ; no error
|
||||
LDX #$FF ; 32 MB partition
|
||||
LDY #$FF
|
||||
|
||||
JSR WRPROT
|
||||
BCC :DONE
|
||||
LDA #$2B ; card write protected
|
||||
|
||||
:DONE RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Read 512 byte block
|
||||
* $43 Unit number DSSS0000
|
||||
* $44-45 Address (LO/HI) of buffer
|
||||
* $46-47 Block number (LO/HI)
|
||||
*
|
||||
* C Clear - No error
|
||||
* Set - Error
|
||||
* A $00 - No error
|
||||
* $27 - Bad block number
|
||||
*
|
||||
********************************
|
||||
|
||||
READ JSR GETBLOCK ; calc block address
|
||||
|
||||
LDA SS,X ; enable /CS
|
||||
AND #$FF!SS0
|
||||
STA SS,X
|
||||
LDA #$51 ; send CMD17
|
||||
JSR COMMAND ; send command
|
||||
|
||||
CMP #0 ; check for error
|
||||
BNE :ERROR
|
||||
|
||||
:GETTOK LDA #DUMMY ; get data token
|
||||
STA DATA,X
|
||||
LDA DATA,X ; get response
|
||||
CMP #$FE
|
||||
BNE :GETTOK ; wait for $FE
|
||||
|
||||
LDY #2 ; read data from card
|
||||
LDA CTRL,X ; enable FRX
|
||||
ORA #FRX
|
||||
STA CTRL,X
|
||||
LDA #DUMMY
|
||||
STA DATA,X
|
||||
:LOOPY STZ WORK
|
||||
:LOOPW LDA DATA,X
|
||||
STA (BUFFER)
|
||||
INC BUFFER
|
||||
BNE :INW
|
||||
INC BUFFER+1 ; inc msb on page boundary
|
||||
:INW INC WORK
|
||||
BNE :LOOPW
|
||||
DEY
|
||||
BNE :LOOPY
|
||||
|
||||
:CRC LDA DATA,X ; read two bytes crc
|
||||
LDA DATA,X ; and ignore
|
||||
LDA DATA,X ; read a dummy byte
|
||||
|
||||
LDA CTRL,X ; disable FRX
|
||||
AND #$FF!FRX
|
||||
STA CTRL,X
|
||||
CLC ; no error
|
||||
LDA #0
|
||||
|
||||
:DONE PHP
|
||||
PHA
|
||||
LDA SS,X
|
||||
ORA #SS0
|
||||
STA SS,X ; disable /CS
|
||||
PLA
|
||||
PLP
|
||||
RTS
|
||||
|
||||
:ERROR SEC ; an error occured
|
||||
LDA #$27
|
||||
BRA :DONE
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Write 512 byte block
|
||||
* $43 Unit number DSSS0000
|
||||
* $44-45 Address (LO/HI) of buffer
|
||||
* $46-47 Block number (LO/HI)
|
||||
*
|
||||
* C Clear - No error
|
||||
* Set - Error
|
||||
* A $00 - No error
|
||||
* $27 - I/O error or bad block number
|
||||
* $2B - Card write protected
|
||||
*
|
||||
********************************
|
||||
|
||||
WRITE JSR WRPROT
|
||||
BCS :WPERROR ; card write protected
|
||||
|
||||
JSR GETBLOCK ; calc block address
|
||||
|
||||
LDA SS,X ; enable /CS
|
||||
AND #$FF!SS0
|
||||
STA SS,X
|
||||
LDA #$58 ; send CMD24
|
||||
JSR COMMAND ; send command
|
||||
|
||||
CMP #0 ; check for error
|
||||
BNE :IOERROR
|
||||
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send dummy
|
||||
LDA #$FE
|
||||
STA DATA,X ; send data token
|
||||
|
||||
LDY #2 ; send data to card
|
||||
:LOOPY STZ WORK
|
||||
:LOOPW LDA (BUFFER)
|
||||
STA DATA,X
|
||||
INC BUFFER
|
||||
BNE :INW
|
||||
INC BUFFER+1 ; inc msb on page boundary
|
||||
:INW INC WORK
|
||||
BNE :LOOPW
|
||||
DEY
|
||||
BNE :LOOPY
|
||||
|
||||
:CRC STA DATA,X ; send 2 dummy crc bytes
|
||||
STA DATA,X
|
||||
|
||||
STA DATA,X ; get data response
|
||||
LDA DATA,X
|
||||
AND #$1F
|
||||
CMP #$05
|
||||
BNE :IOERROR ; check for write error
|
||||
CLC ; no error
|
||||
LDA #0
|
||||
|
||||
:DONE PHP
|
||||
PHA
|
||||
:WAIT LDA #DUMMY
|
||||
STA DATA,X ; wait for write cycle
|
||||
LDA DATA,X ; to complete
|
||||
CMP #$00
|
||||
BEQ :WAIT
|
||||
|
||||
LDA SS,X ; disable /CS
|
||||
ORA #SS0
|
||||
STA SS,X
|
||||
PLA
|
||||
PLP
|
||||
RTS
|
||||
|
||||
:IOERROR SEC ; an error occured
|
||||
LDA #$27
|
||||
BRA :DONE
|
||||
|
||||
:WPERROR SEC
|
||||
LDA #$2B
|
||||
BRA :DONE
|
||||
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Format
|
||||
* not supported!
|
||||
*
|
||||
********************************
|
||||
|
||||
FORMAT SEC
|
||||
LDA #$01 ; invalid command
|
||||
RTS
|
||||
|
||||
|
||||
********************************
|
||||
*
|
||||
* Test routine
|
||||
*
|
||||
********************************
|
||||
|
||||
TEST
|
||||
|
||||
* get buffer
|
||||
LDY SLOT
|
||||
LDA #2 ; get 512 byte buffer
|
||||
JSR $BEF5 ; call GETBUFR
|
||||
BCS :ERROR
|
||||
STA RAM1,Y
|
||||
STA BUFFER+1
|
||||
LDA #0
|
||||
STA RAM0,Y
|
||||
STA BUFFER
|
||||
|
||||
* fill buffer
|
||||
LDY #0
|
||||
:LOOP TYA
|
||||
STA (BUFFER),Y
|
||||
INY
|
||||
BNE :LOOP
|
||||
INC BUFFER+1
|
||||
:LOOP1 TYA
|
||||
STA (BUFFER),Y
|
||||
INY
|
||||
BNE :LOOP1
|
||||
|
||||
* write to card
|
||||
LDA #2 ; write cmd
|
||||
LDY SLOT
|
||||
STA DCMD
|
||||
LDA RAM0 ; buffer address
|
||||
STA BUFFER
|
||||
LDA RAM1,Y
|
||||
STA BUFFER+1
|
||||
STZ BLOCK ; block number
|
||||
STZ BLOCK+1
|
||||
LDX SLOT16
|
||||
JSR DRIVER
|
||||
BCS :ERROR
|
||||
|
||||
* read from card
|
||||
LDA #1 ; read cmd
|
||||
LDY SLOT
|
||||
STA DCMD
|
||||
LDA RAM0,Y ; buffer address
|
||||
STA BUFFER
|
||||
LDA RAM1,Y
|
||||
STA BUFFER+1
|
||||
STZ BLOCK ; block number
|
||||
STZ BLOCK+1
|
||||
LDX SLOT16
|
||||
JSR DRIVER
|
||||
BCS :ERROR
|
||||
|
||||
* check for errors
|
||||
LDY SLOT
|
||||
LDA RAM0,Y ; buffer address
|
||||
STA BUFFER
|
||||
LDA RAM1,Y
|
||||
STA BUFFER+1
|
||||
LDY #0
|
||||
:LOOP2 TYA
|
||||
CMP (BUFFER),Y
|
||||
BNE :ERRCMP ; error in buffer
|
||||
INY
|
||||
BNE :LOOP2
|
||||
INC BUFFER+1
|
||||
:LOOP3 TYA
|
||||
CMP (BUFFER),Y
|
||||
BNE :ERRCMP
|
||||
INY
|
||||
BNE :LOOP3
|
||||
|
||||
* free buffer
|
||||
JSR $BEF8 ; call FREEBUFR
|
||||
CLC
|
||||
LDA #0
|
||||
RTS
|
||||
|
||||
:ERROR BRK
|
||||
:ERRCMP BRK
|
||||
|
||||
|
||||
CMD0 HEX 400000
|
||||
HEX 000095
|
||||
CMD1 HEX 410000
|
||||
HEX 0000F9
|
||||
CMD8 HEX 480000
|
||||
HEX 01AA87
|
||||
CMD16 HEX 500000
|
||||
HEX 0200FF
|
||||
CMD55 HEX 770000
|
||||
HEX 000065
|
||||
ACMD4140 HEX 694000
|
||||
HEX 000077
|
||||
ACMD410 HEX 690000
|
||||
HEX 0000FF
|
||||
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
|
||||
Microsoft Visual Studio Solution File, Format Version 12.00
|
||||
# Visual Studio 14
|
||||
VisualStudioVersion = 14.0.25420.1
|
||||
MinimumVisualStudioVersion = 10.0.40219.1
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "AppleIISd", "Firmware\AppleIISd.vcxproj", "{9EA7EC3D-1771-420F-932F-231A35ED1200}"
|
||||
EndProject
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Flasher", "Software\Flasher.vcxproj", "{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}"
|
||||
EndProject
|
||||
Global
|
||||
GlobalSection(SolutionConfigurationPlatforms) = preSolution
|
||||
Debug|x86 = Debug|x86
|
||||
Release|x86 = Release|x86
|
||||
EndGlobalSection
|
||||
GlobalSection(ProjectConfigurationPlatforms) = postSolution
|
||||
{9EA7EC3D-1771-420F-932F-231A35ED1200}.Debug|x86.ActiveCfg = Debug|Win32
|
||||
{9EA7EC3D-1771-420F-932F-231A35ED1200}.Debug|x86.Build.0 = Debug|Win32
|
||||
{9EA7EC3D-1771-420F-932F-231A35ED1200}.Release|x86.ActiveCfg = Release|Win32
|
||||
{9EA7EC3D-1771-420F-932F-231A35ED1200}.Release|x86.Build.0 = Release|Win32
|
||||
{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}.Debug|x86.ActiveCfg = Debug|Win32
|
||||
{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}.Debug|x86.Build.0 = Debug|Win32
|
||||
{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}.Release|x86.ActiveCfg = Release|Win32
|
||||
{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}.Release|x86.Build.0 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(SolutionProperties) = preSolution
|
||||
HideSolutionNode = FALSE
|
||||
EndGlobalSection
|
||||
EndGlobal
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,14 @@
|
|||
Qty Value Device Package Parts Description
|
||||
1 LEDSQR2X5 LED2X5 LED1 LED
|
||||
1 MA03-1 MA03-1 SV1 PIN HEADER
|
||||
1 MA06-1 MA06-1 SV2 PIN HEADER
|
||||
1 100k GE08R SIL9 RN1 SIL RESISTOR
|
||||
8 100n C-EUC0603K C0603K C1, C2, C4, C5, C6, C7, C8, C9 CAPACITOR, European symbol
|
||||
1 104H-TDA0-R 104H-TDA0-R 104H-TDA0-R U$2 SD Card Socket
|
||||
3 10n C-EUC0603K C0603K C10, C11, C12 CAPACITOR, European symbol
|
||||
2 10u/16V CPOL-EUA/3216-18R A/3216-18R C3, C13 POLARIZED CAPACITOR, European symbol
|
||||
1 28C64ASO 28C64ASO SO28W IC3 CMOS EEPROM
|
||||
1 470 R-EU_R0603 R0603 R4 RESISTOR, European symbol
|
||||
1 74LS245N 74LS245N DIL20 IC1 Octal BUS TRANSCEIVER, 3-state
|
||||
1 LM1117DTX-3.3 LM1117DTX-3.3 TO252 IC2
|
||||
1 XC9572XL XC9572_S44VQFP SQFP-S-10X10-44 IC4
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
:10000000A220A200A203A20078A960853F203F00A1
|
||||
:10001000BABD0001588DF807290F853FA80A0A0AC2
|
||||
:100020000A853EAA2CFFCFA000B907C9F00D0980B0
|
||||
:10003000995007C810F3A9C520A8FC2C61C0100B6B
|
||||
:10004000ADF8073A854164406C40002000C8C90003
|
||||
:10005000D0EEA9088545644464476446206ECAB062
|
||||
:10006000DFA90A854564446447A9018546206ECA14
|
||||
:10007000B0CE4C01081890013808FAA004B93D0030
|
||||
:10008000488810F9863D78A960853F203F00BABDB9
|
||||
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|
||||
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|
||||
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|
||||
:1000C0002047CADAA63F9D7804689DF804989D7879
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:10017000A94D8540A9C98541205FC9208AC9C90008
|
||||
:10018000D014A43FB978042940F048BD83C00910B9
|
||||
:100190009D83C04CE5C84CFAC8A9478540A9C985CC
|
||||
:1001A00041205FC9A9598540A9C98541205FC9205F
|
||||
:1001B00073C9C901F0E3C900D0034CD3C8A9358580
|
||||
:1001C00040A9C98541205FC92073C9C901F0F6C99A
|
||||
:1001D00000D027A9418540A9C98541205FC9207366
|
||||
:1001E000C9C900D015BD83C009809D83C0BD81C031
|
||||
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|
||||
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|
||||
:10021000642076312E322E3220286329323032305B
|
||||
:1002200020466C6F7269616E20526569747A004075
|
||||
:1002300000000000954100000000F948000001AAFC
|
||||
:10024000875000000200FF7700000000FF7A0000E6
|
||||
:100250000000FF6940000000776900000000FF5ABD
|
||||
:10026000A000B1409D80C03C81C010FBC8C006907A
|
||||
:10027000F17A60A9FF9D80C03C81C010FBBD80C0A9
|
||||
:1002800030F148A9FF9D80C068602073C9485AA01A
|
||||
:10029000044C99C9A9FF9D80C03C81C010FBBD8062
|
||||
:1002A000C04888D0EFA43F6899F805689978056838
|
||||
:1002B00099F804689978047AA9FF9D80C06860DA8B
|
||||
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|
||||
:1002D000F8049E78049845432970F005A9029DF81A
|
||||
:1002E0000424431007BDF8041A9DF804A9103983AB
|
||||
:1002F000C0D011A0091EF8053E78053EF8043E78EE
|
||||
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|
||||
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|
||||
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|
||||
:10033000A9403C83C018F00138686048A9203C837C
|
||||
:10034000C018F001386860A542F00CC901F00BC973
|
||||
:1003500002F00AA90138604C60CA4C6ECA4CD7CA78
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:1003C00081C018A9000848BD83C009019D83C06889
|
||||
:1003D000286038A92780EE203BCAB06720BFC9BD7E
|
||||
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|
||||
:1003F000A9FF9D80C0A9FE9D80C0A000B1449D8042
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:10047000AAC8B14885498648A901A642E00AB01A2F
|
||||
:10048000B248DDDECCD027A001B148A43F99780660
|
||||
:100490008A0AAA20B2CBB002A900AAA00068994893
|
||||
:1004A00000C8C00590F78AA002A200C90160A90493
|
||||
:1004B00080E87CE8CC2043CCA43FB97806D018A5CE
|
||||
:1004C0004CF004A9213860A904924AA007B9FBCCDA
|
||||
:1004D000914A88D0F81860A64CF016CAF008CACA2B
|
||||
:1004E000F00FA9213860A901924AA8A900914A18E1
|
||||
:1004F00060A9E8A63E202FCAB0020910203BCA908E
|
||||
:10050000020904924AA001A9FF914AC8914AC8A9C8
|
||||
:1005100000914AA54CF00CA004B9FFCC914AC8C088
|
||||
:100520001990F618602043CCA64CF00FCAF00CCA04
|
||||
:10053000F006CAF00ACAF003A92138A9001860A978
|
||||
:100540001F3860A002B148854AC8B148854BC8B180
|
||||
:1005500048854C60206ECC900160A63EA43F4C6E56
|
||||
:10056000CA206ECC900160A63EA43F4CD7CAB97891
|
||||
:1005700006F044C901F00EC902F00EC903F010C91B
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:1005C0007806F004A9001860A9113860B9780618F7
|
||||
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|
||||
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|
||||
:1005F00025CCCCCCD6CCD6CCDACCDACC4000000B97
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:1007E0000000000000000000000000000000000009
|
||||
:1007F00000000000000000000000000000000000F9
|
||||
:00000001FF
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,18 @@
|
|||
{signal: [
|
||||
['Apple',
|
||||
{name: '7M', wave: 'n........', period: 2 },
|
||||
{name: 'Phi0', wave: 'hl......h......l..', node: '.a......b......c'},
|
||||
{name: 'Q3', wave: 'lh...l..h...l..h..'},
|
||||
{name: 'ADD', wave: '=.x=............x.', node: '...d............e', phase: 0.5},
|
||||
{name: '/DEV_SEL',wave: 'h.......0......1..'},
|
||||
{},
|
||||
{name: 'R/W', wave: 'x..=.........x....', phase: 0.5},
|
||||
{name: 'DATA', wave: 'x........=.......z', node: '.........f.......g', data: 'FromCPU', phase: 0.5},
|
||||
{name: 'DATA', wave: 'x..........=....z.', node: '...........h....i', data: 'ToCPU', phase: 0.5},
|
||||
],
|
||||
|
||||
],
|
||||
edge: [
|
||||
'a<->b 490 ns', 'a-|>d max 100ns', 'b-|>f max 30ns', 'c-|>e min 15ns', 'h|->c min 140ns', 'c-|>g min 30ns', 'c|->i min 10ns'
|
||||
]
|
||||
}
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 37 KiB |
|
|
@ -0,0 +1,21 @@
|
|||
{signal: [
|
||||
['E2 Read',
|
||||
{name: 'ADD', wave: 'x.=......x..', node: '..a......b'},
|
||||
{name: '/CE', wave: '1..0.....1..', node: '...c'},
|
||||
{name: '/OE', wave: '1...0....1..', node: '....d'},
|
||||
{name: 'DATA', wave: 'z......=...z', node: '.......e...f'},
|
||||
],
|
||||
{},
|
||||
['E2 Write',
|
||||
{name: 'ADD', wave: 'x.=..x........=', node: '..g..h'},
|
||||
{name: '/CE', wave: '1.0......1....0', node: '.........i'},
|
||||
{name: '/OE', wave: '0.1......0.....'},
|
||||
{name: '/WE', wave: '1..0....1.....0', node: '...j....k.....l'},
|
||||
{name: 'DATA', wave: 'z....=.....z...', node: '.....m.....n'},
|
||||
],
|
||||
],
|
||||
edge: [
|
||||
'a-|>e max 150ns', 'b-|>f max 50ns', 'c-|>e max 150ns', 'd|->e 10-70ns',
|
||||
'g-|>j min 10ns', 'k|->i min 0ns', 'j-|>h min 50ns', 'j->k min 100ns', 'k|->m min 50ns', 'k-|>n min 10ns'
|
||||
]
|
||||
}
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 37 KiB |
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,101 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Project DefaultTargets="Build" ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
|
||||
<ItemGroup Label="ProjectConfigurations">
|
||||
<ProjectConfiguration Include="Debug|Win32">
|
||||
<Configuration>Debug</Configuration>
|
||||
<Platform>Win32</Platform>
|
||||
</ProjectConfiguration>
|
||||
<ProjectConfiguration Include="Release|Win32">
|
||||
<Configuration>Release</Configuration>
|
||||
<Platform>Win32</Platform>
|
||||
</ProjectConfiguration>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<None Include="..\README.md" />
|
||||
<None Include="AppleIISd.bin.map" />
|
||||
<None Include="makefile" />
|
||||
<None Include="Makefile.options" />
|
||||
<None Include="obj\AppleIISd.lst" />
|
||||
<None Include="src\AppleIISd.cfg" />
|
||||
<None Include="src\AppleIISd.inc" />
|
||||
<None Include="src\AppleIISd.s" />
|
||||
<None Include="src\Helper.s" />
|
||||
<None Include="src\ProDOS.s" />
|
||||
<None Include="src\Smartport.s" />
|
||||
</ItemGroup>
|
||||
<PropertyGroup Label="Globals">
|
||||
<ProjectGuid>{9EA7EC3D-1771-420F-932F-231A35ED1200}</ProjectGuid>
|
||||
<Keyword>MakeFileProj</Keyword>
|
||||
<ProjectName>AppleIISd</ProjectName>
|
||||
</PropertyGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
|
||||
<ConfigurationType>Makefile</ConfigurationType>
|
||||
<UseDebugLibraries>true</UseDebugLibraries>
|
||||
<PlatformToolset>v140</PlatformToolset>
|
||||
</PropertyGroup>
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
|
||||
<ConfigurationType>Makefile</ConfigurationType>
|
||||
<UseDebugLibraries>false</UseDebugLibraries>
|
||||
<PlatformToolset>v140</PlatformToolset>
|
||||
</PropertyGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
|
||||
<ImportGroup Label="ExtensionSettings">
|
||||
</ImportGroup>
|
||||
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
|
||||
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
|
||||
</ImportGroup>
|
||||
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
|
||||
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
|
||||
</ImportGroup>
|
||||
<PropertyGroup Label="UserMacros" />
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
|
||||
<NMakeOutput>
|
||||
</NMakeOutput>
|
||||
<NMakePreprocessorDefinitions>__APPLE2__;__APPLE2ENH__;__fastcall__=__fastcall;_MSC_VER=0;__attribute__</NMakePreprocessorDefinitions>
|
||||
<ExecutablePath>$(PATH);C:\cc65\bin</ExecutablePath>
|
||||
<IncludePath>C:\cc65\include</IncludePath>
|
||||
<LibraryPath>C:\cc65\lib</LibraryPath>
|
||||
<LibraryWPath />
|
||||
<ExcludePath />
|
||||
<NMakeBuildCommandLine>$(MAKE_HOME)\make OPTIONS=mapfile,listing</NMakeBuildCommandLine>
|
||||
<SourcePath>$(ProjectDir)\src</SourcePath>
|
||||
<NMakeReBuildCommandLine>$(MAKE_HOME)\make clean
|
||||
$(MAKE_HOME)\make OPTIONS=mapfile,listing</NMakeReBuildCommandLine>
|
||||
<OutDir>$(SolutionDir)\</OutDir>
|
||||
<NMakeCleanCommandLine>$(MAKE_HOME)\make clean</NMakeCleanCommandLine>
|
||||
<ReferencePath />
|
||||
</PropertyGroup>
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
|
||||
<NMakeOutput>
|
||||
</NMakeOutput>
|
||||
<NMakePreprocessorDefinitions>
|
||||
</NMakePreprocessorDefinitions>
|
||||
<NMakeBuildCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"</NMakeBuildCommandLine>
|
||||
<NMakeReBuildCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make clean -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
$(MAKE_HOME)\make -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"
|
||||
</NMakeReBuildCommandLine>
|
||||
<NMakeCleanCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make clean -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"</NMakeCleanCommandLine>
|
||||
<ExecutablePath>$(PATH);C:\cc65\bin</ExecutablePath>
|
||||
<IncludePath>$(VC_IncludePath);C:\cc65\include</IncludePath>
|
||||
<ReferencePath />
|
||||
<LibraryPath>C:\cc65\lib</LibraryPath>
|
||||
<ExcludePath />
|
||||
<LibraryWPath />
|
||||
<OutDir>$(SolutionDir)$\</OutDir>
|
||||
</PropertyGroup>
|
||||
<ItemDefinitionGroup>
|
||||
</ItemDefinitionGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
|
||||
<ImportGroup Label="ExtensionTargets">
|
||||
</ImportGroup>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
|
||||
<ItemGroup>
|
||||
<None Include="makefile" />
|
||||
<None Include="src\AppleIISd.cfg">
|
||||
<Filter>src</Filter>
|
||||
</None>
|
||||
<None Include="src\AppleIISd.s">
|
||||
<Filter>src</Filter>
|
||||
</None>
|
||||
<None Include="obj\AppleIISd.lst" />
|
||||
<None Include="src\Helper.s">
|
||||
<Filter>src</Filter>
|
||||
</None>
|
||||
<None Include="src\AppleIISd.inc">
|
||||
<Filter>src</Filter>
|
||||
</None>
|
||||
<None Include="src\ProDOS.s">
|
||||
<Filter>src</Filter>
|
||||
</None>
|
||||
<None Include="src\Smartport.s">
|
||||
<Filter>src</Filter>
|
||||
</None>
|
||||
<None Include="Makefile.options" />
|
||||
<None Include="..\README.md" />
|
||||
<None Include="AppleIISd.bin.map" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<Filter Include="src">
|
||||
<UniqueIdentifier>{d301b76d-0aac-4430-a25a-193e6e572e60}</UniqueIdentifier>
|
||||
</Filter>
|
||||
</ItemGroup>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
make clean
|
||||
make OPTIONS=mapfile,listing
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -d ..\Binary\Flasher.dsk appleiisd.bin
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -p ..\Binary\Flasher.dsk appleiisd.bin $00 < AppleIISd.bin
|
||||
copy AppleIISd.bin ..\Binary
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#!/bin/bash
|
||||
|
||||
make clean
|
||||
make OPTIONS=mapfile,listing
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -d ../Binary/Flasher.dsk appleiisd.bin
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -p ../Binary/Flasher.dsk appleiisd.bin $00 < AppleIISd.bin
|
||||
cp AppleIISd.bin ../Binary/
|
||||
|
|
@ -0,0 +1,346 @@
|
|||
###############################################################################
|
||||
### Generic Makefile for cc65 projects - full version with abstract options ###
|
||||
### V1.3.0(w) 2010 - 2013 Oliver Schmidt & Patryk "Silver Dream !" ?ogiewa ###
|
||||
###############################################################################
|
||||
|
||||
###############################################################################
|
||||
### In order to override defaults - values can be assigned to the variables ###
|
||||
###############################################################################
|
||||
|
||||
# Space or comma separated list of cc65 supported target platforms to build for.
|
||||
# Default: c64 (lowercase!)
|
||||
TARGETS := apple2enh
|
||||
|
||||
# Name of the final, single-file executable.
|
||||
# Default: name of the current dir with target name appended
|
||||
PROGRAM := AppleIISd
|
||||
|
||||
# Path(s) to additional libraries required for linking the program
|
||||
# Use only if you don't want to place copies of the libraries in SRCDIR
|
||||
# Default: none
|
||||
LIBS :=
|
||||
|
||||
# Custom linker configuration file
|
||||
# Use only if you don't want to place it in SRCDIR
|
||||
# Default: none
|
||||
CONFIG :=
|
||||
|
||||
# Additional C compiler flags and options.
|
||||
# Default: none
|
||||
CFLAGS =
|
||||
|
||||
# Additional assembler flags and options.
|
||||
# Default: none
|
||||
ASFLAGS =
|
||||
|
||||
# Additional linker flags and options.
|
||||
# Default: none
|
||||
LDFLAGS =
|
||||
|
||||
# Path to the directory containing C and ASM sources.
|
||||
# Default: src
|
||||
SRCDIR :=
|
||||
|
||||
# Path to the directory where object files are to be stored (inside respective target subdirectories).
|
||||
# Default: obj
|
||||
OBJDIR :=
|
||||
|
||||
# Command used to run the emulator.
|
||||
# Default: depending on target platform. For default (c64) target: x64 -kernal kernal -VICIIdsize -autoload
|
||||
EMUCMD :=
|
||||
|
||||
# Optional commands used before starting the emulation process, and after finishing it.
|
||||
# Default: none
|
||||
# Examples
|
||||
#PREEMUCMD := osascript -e "tell application \"System Events\" to set isRunning to (name of processes) contains \"X11.bin\"" -e "if isRunning is true then tell application \"X11\" to activate"
|
||||
#PREEMUCMD := osascript -e "tell application \"X11\" to activate"
|
||||
#POSTEMUCMD := osascript -e "tell application \"System Events\" to tell process \"X11\" to set visible to false"
|
||||
#POSTEMUCMD := osascript -e "tell application \"Terminal\" to activate"
|
||||
PREEMUCMD :=
|
||||
POSTEMUCMD :=
|
||||
|
||||
# On Windows machines VICE emulators may not be available in the PATH by default.
|
||||
# In such case, please set the variable below to point to directory containing
|
||||
# VICE emulators.
|
||||
#VICE_HOME := "C:\Program Files\WinVICE-2.2-x86\"
|
||||
VICE_HOME :=
|
||||
|
||||
# Options state file name. You should not need to change this, but for those
|
||||
# rare cases when you feel you really need to name it differently - here you are
|
||||
STATEFILE := Makefile.options
|
||||
|
||||
###################################################################################
|
||||
#### DO NOT EDIT BELOW THIS LINE, UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! ####
|
||||
###################################################################################
|
||||
|
||||
###################################################################################
|
||||
### Mapping abstract options to the actual compiler, assembler and linker flags ###
|
||||
### Predefined compiler, assembler and linker flags, used with abstract options ###
|
||||
### valid for 2.14.x. Consult the documentation of your cc65 version before use ###
|
||||
###################################################################################
|
||||
|
||||
# Compiler flags used to tell the compiler to optimise for SPEED
|
||||
define _optspeed_
|
||||
CFLAGS += -Oris
|
||||
endef
|
||||
|
||||
# Compiler flags used to tell the compiler to optimise for SIZE
|
||||
define _optsize_
|
||||
CFLAGS += -Or
|
||||
endef
|
||||
|
||||
# Compiler and assembler flags for generating listings
|
||||
define _listing_
|
||||
CFLAGS += --listing $$(@:.o=.lst)
|
||||
ASFLAGS += --listing $$(@:.o=.lst)
|
||||
REMOVES += $(addsuffix .lst,$(basename $(OBJECTS)))
|
||||
endef
|
||||
|
||||
# Linker flags for generating map file
|
||||
define _mapfile_
|
||||
LDFLAGS += --mapfile $$@.map
|
||||
REMOVES += $(PROGRAM).map
|
||||
endef
|
||||
|
||||
# Linker flags for generating VICE label file
|
||||
define _labelfile_
|
||||
LDFLAGS += -Ln $$@.lbl
|
||||
REMOVES += $(PROGRAM).lbl
|
||||
endef
|
||||
|
||||
# Linker flags for generating a debug file
|
||||
define _debugfile_
|
||||
LDFLAGS += -Wl --dbgfile,$$@.dbg
|
||||
REMOVES += $(PROGRAM).dbg
|
||||
endef
|
||||
|
||||
###############################################################################
|
||||
### Defaults to be used if nothing defined in the editable sections above ###
|
||||
###############################################################################
|
||||
|
||||
# Presume the C64 target like the cl65 compile & link utility does.
|
||||
# Set TARGETS to override.
|
||||
ifeq ($(TARGETS),)
|
||||
TARGETS := c64
|
||||
endif
|
||||
|
||||
# Presume we're in a project directory so name the program like the current
|
||||
# directory. Set PROGRAM to override.
|
||||
ifeq ($(PROGRAM),)
|
||||
PROGRAM := $(notdir $(CURDIR))
|
||||
endif
|
||||
|
||||
# Presume the C and asm source files to be located in the subdirectory 'src'.
|
||||
# Set SRCDIR to override.
|
||||
ifeq ($(SRCDIR),)
|
||||
SRCDIR := src
|
||||
endif
|
||||
|
||||
# Presume the object and dependency files to be located in the subdirectory
|
||||
# 'obj' (which will be created). Set OBJDIR to override.
|
||||
ifeq ($(OBJDIR),)
|
||||
OBJDIR := obj
|
||||
endif
|
||||
TARGETOBJDIR := $(OBJDIR)
|
||||
|
||||
# On Windows it is mandatory to have CC65_HOME set. So do not unnecessarily
|
||||
# rely on cl65 being added to the PATH in this scenario.
|
||||
ifdef CC65_HOME
|
||||
CC := $(CC65_HOME)/bin/cl65
|
||||
else
|
||||
CC := cl65
|
||||
endif
|
||||
|
||||
# Default emulator commands and options for particular targets.
|
||||
# Set EMUCMD to override.
|
||||
c64_EMUCMD := $(VICE_HOME)x64 -kernal kernal -VICIIdsize -autoload
|
||||
c128_EMUCMD := $(VICE_HOME)x128 -kernal kernal -VICIIdsize -autoload
|
||||
vic20_EMUCMD := $(VICE_HOME)xvic -kernal kernal -VICdsize -autoload
|
||||
pet_EMUCMD := $(VICE_HOME)xpet -Crtcdsize -autoload
|
||||
plus4_EMUCMD := $(VICE_HOME)xplus4 -TEDdsize -autoload
|
||||
# So far there is no x16 emulator in VICE (why??) so we have to use xplus4 with -memsize option
|
||||
c16_EMUCMD := $(VICE_HOME)xplus4 -ramsize 16 -TEDdsize -autoload
|
||||
cbm510_EMUCMD := $(VICE_HOME)xcbm2 -model 510 -VICIIdsize -autoload
|
||||
cbm610_EMUCMD := $(VICE_HOME)xcbm2 -model 610 -Crtcdsize -autoload
|
||||
atari_EMUCMD := atari800 -windowed -xl -pal -nopatchall -run
|
||||
|
||||
ifeq ($(EMUCMD),)
|
||||
EMUCMD = $($(CC65TARGET)_EMUCMD)
|
||||
endif
|
||||
|
||||
###############################################################################
|
||||
### The magic begins ###
|
||||
###############################################################################
|
||||
|
||||
# The "Native Win32" GNU Make contains quite some workarounds to get along with
|
||||
# cmd.exe as shell. However it does not provide means to determine that it does
|
||||
# actually activate those workarounds. Especially $(SHELL) does NOT contain the
|
||||
# value 'cmd.exe'. So the usual way to determine if cmd.exe is being used is to
|
||||
# execute the command 'echo' without any parameters. Only cmd.exe will return a
|
||||
# non-empty string - saying 'ECHO is on/off'.
|
||||
#
|
||||
# Many "Native Win32" programs accept '/' as directory delimiter just fine. How-
|
||||
# ever the internal commands of cmd.exe generally require '\' to be used.
|
||||
#
|
||||
# cmd.exe has an internal command 'mkdir' that doesn't understand nor require a
|
||||
# '-p' to create parent directories as needed.
|
||||
#
|
||||
# cmd.exe has an internal command 'del' that reports a syntax error if executed
|
||||
# without any file so make sure to call it only if there's an actual argument.
|
||||
ifeq ($(shell echo),)
|
||||
MKDIR = mkdir -p $1
|
||||
RMDIR = rmdir $1
|
||||
RMFILES = $(RM) $1
|
||||
else
|
||||
MKDIR = mkdir $(subst /,\,$1)
|
||||
RMDIR = rmdir $(subst /,\,$1)
|
||||
RMFILES = $(if $1,del /f $(subst /,\,$1))
|
||||
endif
|
||||
COMMA := ,
|
||||
SPACE := $(N/A) $(N/A)
|
||||
define NEWLINE
|
||||
|
||||
|
||||
endef
|
||||
# Note: Do not remove any of the two empty lines above !
|
||||
|
||||
TARGETLIST := $(subst $(COMMA),$(SPACE),$(TARGETS))
|
||||
|
||||
ifeq ($(words $(TARGETLIST)),1)
|
||||
|
||||
# Set PROGRAM to something like 'myprog.c64'.
|
||||
override PROGRAM := $(PROGRAM).bin
|
||||
|
||||
# Set SOURCES to something like 'src/foo.c src/bar.s'.
|
||||
# Use of assembler files with names ending differently than .s is deprecated!
|
||||
SOURCES := $(wildcard $(SRCDIR)/*.c)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.s)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.asm)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.a65)
|
||||
|
||||
# Add to SOURCES something like 'src/c64/me.c src/c64/too.s'.
|
||||
# Use of assembler files with names ending differently than .s is deprecated!
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.c)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.s)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.asm)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.a65)
|
||||
|
||||
# Set OBJECTS to something like 'obj/c64/foo.o obj/c64/bar.o'.
|
||||
OBJECTS := $(addsuffix .o,$(basename $(addprefix $(TARGETOBJDIR)/,$(notdir $(SOURCES)))))
|
||||
|
||||
# Set DEPENDS to something like 'obj/c64/foo.d obj/c64/bar.d'.
|
||||
DEPENDS := $(OBJECTS:.o=.d)
|
||||
|
||||
# Add to LIBS something like 'src/foo.lib src/c64/bar.lib'.
|
||||
LIBS += $(wildcard $(SRCDIR)/*.lib)
|
||||
LIBS += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.lib)
|
||||
|
||||
# Add to CONFIG something like 'src/c64/bar.cfg src/foo.cfg'.
|
||||
CONFIG += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.cfg)
|
||||
CONFIG += $(wildcard $(SRCDIR)/*.cfg)
|
||||
|
||||
# Select CONFIG file to use. Target specific configs have higher priority.
|
||||
ifneq ($(word 2,$(CONFIG)),)
|
||||
CONFIG := $(firstword $(CONFIG))
|
||||
$(info Using config file $(CONFIG) for linking)
|
||||
endif
|
||||
|
||||
.SUFFIXES:
|
||||
.PHONY: all test clean zap love
|
||||
|
||||
all: $(PROGRAM)
|
||||
|
||||
-include $(DEPENDS)
|
||||
-include $(STATEFILE)
|
||||
|
||||
# If OPTIONS are given on the command line then save them to STATEFILE
|
||||
# if (and only if) they have actually changed. But if OPTIONS are not
|
||||
# given on the command line then load them from STATEFILE. Have object
|
||||
# files depend on STATEFILE only if it actually exists.
|
||||
ifeq ($(origin OPTIONS),command line)
|
||||
ifneq ($(OPTIONS),$(_OPTIONS_))
|
||||
ifeq ($(OPTIONS),)
|
||||
$(info Removing OPTIONS)
|
||||
$(shell $(RM) $(STATEFILE))
|
||||
$(eval $(STATEFILE):)
|
||||
else
|
||||
$(info Saving OPTIONS=$(OPTIONS))
|
||||
$(shell echo _OPTIONS_=$(OPTIONS) > $(STATEFILE))
|
||||
endif
|
||||
$(eval $(OBJECTS): $(STATEFILE))
|
||||
endif
|
||||
else
|
||||
ifeq ($(origin _OPTIONS_),file)
|
||||
$(info Using saved OPTIONS=$(_OPTIONS_))
|
||||
OPTIONS = $(_OPTIONS_)
|
||||
$(eval $(OBJECTS): $(STATEFILE))
|
||||
endif
|
||||
endif
|
||||
|
||||
# Transform the abstract OPTIONS to the actual cc65 options.
|
||||
$(foreach o,$(subst $(COMMA),$(SPACE),$(OPTIONS)),$(eval $(_$o_)))
|
||||
|
||||
# Strip potential variant suffix from the actual cc65 target.
|
||||
CC65TARGET := $(firstword $(subst .,$(SPACE),$(TARGETLIST)))
|
||||
|
||||
# The remaining targets.
|
||||
$(TARGETOBJDIR):
|
||||
$(call MKDIR,$@)
|
||||
|
||||
vpath %.c $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.c | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(CFLAGS) -o $@ $<
|
||||
|
||||
vpath %.s $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.s | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
vpath %.asm $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.asm | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
vpath %.a65 $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.a65 | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
$(PROGRAM): $(CONFIG) $(OBJECTS) $(LIBS)
|
||||
$(CC) -t $(CC65TARGET) $(LDFLAGS) -o $@ $(patsubst %.cfg,-C %.cfg,$^)
|
||||
|
||||
test: $(PROGRAM)
|
||||
$(PREEMUCMD)
|
||||
$(EMUCMD) $<
|
||||
$(POSTEMUCMD)
|
||||
|
||||
clean:
|
||||
$(call RMFILES,$(OBJECTS))
|
||||
$(call RMFILES,$(DEPENDS))
|
||||
$(call RMFILES,$(REMOVES))
|
||||
$(call RMFILES,$(PROGRAM))
|
||||
|
||||
else # $(words $(TARGETLIST)),1
|
||||
|
||||
all test clean:
|
||||
$(foreach t,$(TARGETLIST),$(MAKE) TARGETS=$t $@$(NEWLINE))
|
||||
|
||||
endif # $(words $(TARGETLIST)),1
|
||||
|
||||
OBJDIRLIST := $(wildcard $(OBJDIR)/*)
|
||||
|
||||
zap:
|
||||
$(foreach o,$(OBJDIRLIST),-$(call RMFILES,$o/*.o $o/*.d $o/*.lst)$(NEWLINE))
|
||||
$(foreach o,$(OBJDIRLIST),-$(call RMDIR,$o)$(NEWLINE))
|
||||
-$(call RMDIR,$(OBJDIR))
|
||||
-$(call RMFILES,$(basename $(PROGRAM)).* $(STATEFILE))
|
||||
|
||||
love:
|
||||
@echo "Not war, eh?"
|
||||
|
||||
###################################################################
|
||||
### Place your additional targets in the additional Makefiles ###
|
||||
### in the same directory - their names have to end with ".mk"! ###
|
||||
###################################################################
|
||||
-include *.mk
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
# Configuration for assembler programs which don't need a special setup
|
||||
|
||||
FEATURES {
|
||||
STARTADDRESS: default = $0803;
|
||||
}
|
||||
MEMORY {
|
||||
ZP: file = "", start = $0000, size = $00FF;
|
||||
HEADER: file = %O, start = %S - 4, size = $0004;
|
||||
MAIN: file = %O, define = yes, start = %S, size = $C000 - %S;
|
||||
BSS: file = "", start = __MAIN_LAST__, size = $C000 - __MAIN_LAST__;
|
||||
|
||||
SLOTROM: file = %O, fill = yes start = $C700, size = $00FB;
|
||||
SLOTID: file = %O, start = $C7FB, size = $0005;
|
||||
EXTROM: file = %O, fill = yes start = $C800, size = $0700;
|
||||
}
|
||||
SEGMENTS {
|
||||
ZEROPAGE: load = ZP, type = zp, optional = yes;
|
||||
EXEHDR: load = HEADER, type = ro, optional = yes;
|
||||
CODE: load = MAIN, type = rw;
|
||||
RODATA: load = MAIN, type = ro, optional = yes;
|
||||
DATA: load = MAIN, type = rw, optional = yes;
|
||||
BSS: load = BSS, type = bss, optional = yes, define = yes;
|
||||
|
||||
SLOTROM: load = SLOTROM, type = ro;
|
||||
SLOTID: load = SLOTID, type = ro;
|
||||
EXTROM: load = EXTROM, type = ro, optional = yes;
|
||||
}
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2.3
|
||||
; Defines
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
; ZP locations
|
||||
PSAVE := $3D ; P save location
|
||||
SLOT16 := $3E ; $s0 -> slot * 16
|
||||
SLOT := $3F ; $0s
|
||||
CMDLO := $40
|
||||
CMDHI := $41
|
||||
PDZPAREA = PSAVE
|
||||
PDZPSIZE = CMDHI-PDZPAREA+1
|
||||
|
||||
; ProDOS
|
||||
DCMD := $42 ; Command code
|
||||
DSNUMBER := $43 ; drive / slot number
|
||||
BUFFER := $44 ; buffer pointer, two bytes
|
||||
BLOCKNUM := $46 ; block number, two bytes
|
||||
|
||||
; Smartport
|
||||
SMPARAMLIST := $48 ; parameter list, two bytes
|
||||
SMCMDLIST := $4A ; command list, two bytes
|
||||
SMCSCODE := $4C
|
||||
SMZPAREA = SMPARAMLIST
|
||||
SMZPSIZE = SMCSCODE-SMZPAREA+1
|
||||
SMCMD = DCMD
|
||||
|
||||
|
||||
; Ram equates, access with SLOT offset
|
||||
R30 := $0478
|
||||
R31 := $04F8
|
||||
R32 := $0578
|
||||
R33 := $05F8
|
||||
DRVNUM := $0678
|
||||
CURSLOT := $07F8 ; $Cs
|
||||
|
||||
; Rom equates
|
||||
OAPPLE := $C061 ; open apple key
|
||||
DATA := $C080
|
||||
CTRL := DATA+1
|
||||
SS := DATA+3
|
||||
|
||||
; Constants
|
||||
DUMMY = $FF
|
||||
FRX = $10 ; CTRL register
|
||||
ECE = $04
|
||||
SS0 = $01 ; SS register
|
||||
SDHC = $10
|
||||
WP = $20
|
||||
CD = $40
|
||||
CARD_INIT = $80
|
||||
|
||||
SMDRIVERVER = $120B ; Version 1.2 Beta
|
||||
|
||||
; Error codes
|
||||
NO_ERR = $00
|
||||
ERR_BADCMD = $01
|
||||
ERR_BADPCNT = $04
|
||||
ERR_BUSERR = $06
|
||||
ERR_BADUNIT = $11
|
||||
ERR_NOINT = $1F
|
||||
ERR_BADCTL = $21
|
||||
ERR_BADCTLPARM = $22
|
||||
ERR_IOERR = $27
|
||||
ERR_NODRIVE = $28
|
||||
ERR_NOWRITE = $2B
|
||||
ERR_BADBLOCK = $2D
|
||||
ERR_OFFLINE = $2F
|
||||
|
|
@ -0,0 +1,378 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2.3
|
||||
; Main source
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.export INIT
|
||||
|
||||
.import PRODOS
|
||||
.import SMARTPORT
|
||||
.import GETR1
|
||||
.import GETR3
|
||||
.import SDCMD
|
||||
.import CARDDET
|
||||
.import INITED
|
||||
.import READ
|
||||
|
||||
.include "AppleIISd.inc"
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Signature bytes
|
||||
;
|
||||
; 65535 blocks
|
||||
; Removable media
|
||||
; Non-interruptable
|
||||
; 2 drives
|
||||
; Read, write and status allowed
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.segment "SLOTID"
|
||||
.byt $0 ; not extended, no SCSI, no RAM
|
||||
.word $0000 ; use status call
|
||||
.byt $97 ; Status bits
|
||||
.byt <DRIVER ; LSB of driver
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Bootcode
|
||||
;
|
||||
; Is executed on boot or PR#
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.segment "SLOTROM"
|
||||
LDX #$20
|
||||
LDX #$00
|
||||
LDX #$03
|
||||
LDX #$00 ; is Smartport controller
|
||||
;LDX #$3C ; is a disk controller
|
||||
|
||||
SEI ; find slot
|
||||
BIT $CFFF
|
||||
JSR KNOWNRTS
|
||||
TSX
|
||||
LDA $0100,X
|
||||
CLI
|
||||
STA CURSLOT ; $Cs
|
||||
AND #$0F
|
||||
STA SLOT ; $0s
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
STA SLOT16 ; $s0
|
||||
TAX ; X holds now SLOT16
|
||||
|
||||
LDY #0 ; display copyright message
|
||||
@DRAW: LDA TEXT,Y
|
||||
BEQ @OAPPLE ; check for NULL
|
||||
ORA #$80 ; set MSB
|
||||
STA $0750,Y ; put second to last line
|
||||
INY
|
||||
BPL @DRAW
|
||||
|
||||
LDA #197
|
||||
JSR $FCA8 ; wait for 100 ms
|
||||
|
||||
@OAPPLE: LDA OAPPLE ; check for OA key
|
||||
BPL @INIT ; and skip boot if pressed
|
||||
|
||||
@NEXTSLOT: LDA CURSLOT ; skip boot when no card
|
||||
DEC A
|
||||
STA CMDHI ; use CMDHI/LO as pointer
|
||||
STZ CMDLO
|
||||
JMP (CMDLO)
|
||||
|
||||
@INIT: JSR INIT
|
||||
BNE @NEXTSLOT ; init not successful
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Boot from SD card
|
||||
;
|
||||
;*******************************
|
||||
|
||||
; load disk blocks 0 and 1 to $800 and $A00
|
||||
@BOOT: LDA #$08 ; load to $800
|
||||
STA BUFFER+1 ; buffer hi
|
||||
STZ BUFFER ; buffer lo
|
||||
STZ BLOCKNUM+1 ; block hi
|
||||
STZ BLOCKNUM ; block lo
|
||||
LDA SLOT16
|
||||
STA DSNUMBER ; set to current slot
|
||||
JSR READ
|
||||
BCS @NEXTSLOT ; load not successful
|
||||
|
||||
LDA #$0A
|
||||
STA BUFFER+1 ; buffer hi
|
||||
STZ BUFFER ; buffer lo
|
||||
STZ BLOCKNUM+1 ; block hi
|
||||
LDA #$01
|
||||
STA BLOCKNUM ; block lo
|
||||
JSR READ
|
||||
BCS @NEXTSLOT ; load not successful
|
||||
JMP $801 ; goto bootloader
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Jump table
|
||||
;
|
||||
;*******************************
|
||||
|
||||
DRIVER: CLC ; ProDOS entry
|
||||
BCC @PRODOS
|
||||
SEC ; Smartport entry
|
||||
|
||||
@PRODOS: PHP ; transfer P to X
|
||||
PLX
|
||||
LDY #PDZPSIZE-1 ; save zeropage area for ProDOS
|
||||
@SAVEZP: LDA PDZPAREA,Y
|
||||
PHA
|
||||
DEY
|
||||
BPL @SAVEZP
|
||||
STX PSAVE ; save X (P)
|
||||
|
||||
; Has this to be done every time this gets called or only on boot???
|
||||
SEI
|
||||
BIT $CFFF
|
||||
JSR KNOWNRTS
|
||||
TSX
|
||||
LDA $0100,X
|
||||
CLI
|
||||
STA CURSLOT ; $Cs
|
||||
AND #$0F
|
||||
STA SLOT ; $0s
|
||||
TAY ; Y holds now SLOT
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
ASL A
|
||||
STA SLOT16 ; $s0
|
||||
TAX ; X holds now SLOT16
|
||||
|
||||
JSR INITED ; check for init
|
||||
BCC @DISP
|
||||
JSR INIT
|
||||
BCS @END ; Init failed
|
||||
|
||||
@DISP: LDA PSAVE ; get saved P value
|
||||
PHA ; and transfer to P
|
||||
PLP
|
||||
BCS @SMARTPORT ; Smartport dispatcher
|
||||
JSR PRODOS ; ProDOS dispatcher
|
||||
|
||||
@END: PHX
|
||||
LDX SLOT ; X holds $0s
|
||||
STA R30,X ; save A
|
||||
PLA
|
||||
STA R31,X ; save X
|
||||
TYA
|
||||
STA R32,X ; save Y
|
||||
PHP
|
||||
PLA
|
||||
STA R33,X ; save P
|
||||
|
||||
LDY #0
|
||||
@RESTZP: PLA ; restore zeropage area
|
||||
STA PDZPAREA,Y
|
||||
INY
|
||||
CPY #PDZPSIZE
|
||||
BCC @RESTZP
|
||||
|
||||
LDA R33,X ; get retval
|
||||
PHA
|
||||
LDA R32,X
|
||||
PHA
|
||||
LDA R31,X
|
||||
PHA
|
||||
LDA R30,X ; restore A
|
||||
PLX ; restore X
|
||||
PLY ; restore Y
|
||||
PLP ; restore P
|
||||
RTS
|
||||
|
||||
@SMARTPORT: CLC
|
||||
JSR SMARTPORT
|
||||
BRA @END
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Initialize SD card
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $27 - I/O error - Init failed
|
||||
; $2F - No card inserted
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.segment "EXTROM"
|
||||
INIT: STZ CTRL,X ; reset SPI controller
|
||||
LDA #SS0 ; set CS high
|
||||
STA SS,X
|
||||
LDY #10
|
||||
|
||||
@LOOP: LDA #DUMMY
|
||||
STA DATA,X
|
||||
@WAIT: LDA CTRL,X ; wait for TC (bit 7) to get high
|
||||
BPL @WAIT
|
||||
DEY
|
||||
BNE @LOOP ; do 10 times
|
||||
LDA SS,X
|
||||
AND #<~SS0 ; set CS low
|
||||
STA SS,X
|
||||
|
||||
LDA #<CMD0 ; send CMD0
|
||||
STA CMDLO
|
||||
LDA #>CMD0
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR1 ; get response
|
||||
CMP #$01
|
||||
BNE @ERROR1 ; error!
|
||||
|
||||
LDA #<CMD8 ; send CMD8
|
||||
STA CMDLO
|
||||
LDA #>CMD8
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR3 ; R7 is also 1+4 bytes
|
||||
CMP #$01
|
||||
BNE @SDV1 ; may be SD Ver. 1
|
||||
|
||||
LDY SLOT ; check for $aa in R33
|
||||
LDA R33,Y
|
||||
CMP #$AA
|
||||
BNE @ERROR1 ; error!
|
||||
|
||||
@SDV2: LDA #<CMD55
|
||||
STA CMDLO
|
||||
LDA #>CMD55
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR1
|
||||
LDA #<ACMD4140 ; enable SDHC support
|
||||
STA CMDLO
|
||||
LDA #>ACMD4140
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ @SDV2 ; wait for ready
|
||||
CMP #0
|
||||
BNE @ERROR1 ; error!
|
||||
|
||||
; SD Ver. 2 initialized!
|
||||
LDA #<CMD58 ; check for SDHC
|
||||
STA CMDLO
|
||||
LDA #>CMD58
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR3
|
||||
CMP #0
|
||||
BNE @ERROR1 ; error!
|
||||
LDY SLOT
|
||||
LDA R30,Y
|
||||
AND #$40 ; check CCS
|
||||
BEQ @BLOCKSZ
|
||||
|
||||
LDA SS,X ; card is SDHC
|
||||
ORA #SDHC
|
||||
STA SS,X
|
||||
JMP @END
|
||||
|
||||
@ERROR1: JMP @IOERROR ; needed for far jump
|
||||
|
||||
@SDV1: LDA #<CMD55
|
||||
STA CMDLO
|
||||
LDA #>CMD55
|
||||
STA CMDHI
|
||||
JSR SDCMD ; ignore response
|
||||
LDA #<ACMD410
|
||||
STA CMDLO
|
||||
LDA #>ACMD410
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ @SDV1 ; wait for ready
|
||||
CMP #0
|
||||
BNE @MMC ; may be MMC card
|
||||
; SD Ver. 1 initialized!
|
||||
JMP @BLOCKSZ
|
||||
|
||||
@MMC: LDA #<CMD1
|
||||
STA CMDLO
|
||||
LDA #>CMD1
|
||||
STA CMDHI
|
||||
@LOOP1: JSR SDCMD
|
||||
JSR GETR1
|
||||
CMP #$01
|
||||
BEQ @LOOP1 ; wait for ready
|
||||
CMP #0
|
||||
BNE @IOERROR ; error!
|
||||
; MMC Ver. 3 initialized!
|
||||
|
||||
@BLOCKSZ: LDA #<CMD16
|
||||
STA CMDLO
|
||||
LDA #>CMD16
|
||||
STA CMDHI
|
||||
JSR SDCMD
|
||||
JSR GETR1
|
||||
CMP #0
|
||||
BNE @IOERROR ; error!
|
||||
|
||||
@END: LDA SS,X
|
||||
ORA #CARD_INIT ; initialized
|
||||
STA SS,X
|
||||
LDA CTRL,X
|
||||
ORA #ECE ; enable 7MHz
|
||||
STA CTRL,X
|
||||
CLC ; all ok
|
||||
LDY #NO_ERR
|
||||
BCC @END1
|
||||
|
||||
@IOERROR: SEC
|
||||
LDY #ERR_IOERR ; init error
|
||||
@END1: LDA SS,X ; set CS high
|
||||
ORA #SS0
|
||||
STA SS,X
|
||||
TYA ; retval in A
|
||||
KNOWNRTS: RTS
|
||||
|
||||
|
||||
TEXT: .asciiz " Apple][Sd v1.2.2 (c)2021 Florian Reitz"
|
||||
.assert(*-TEXT)=40, error, "TEXT must be 40 bytes long"
|
||||
|
||||
|
||||
CMD0: .byt $40, $00, $00
|
||||
.byt $00, $00, $95
|
||||
CMD1: .byt $41, $00, $00
|
||||
.byt $00, $00, $F9
|
||||
CMD8: .byt $48, $00, $00
|
||||
.byt $01, $AA, $87
|
||||
CMD16: .byt $50, $00, $00
|
||||
.byt $02, $00, $FF
|
||||
CMD55: .byt $77, $00, $00
|
||||
.byt $00, $00, $FF
|
||||
CMD58: .byt $7A, $00, $00
|
||||
.byt $00, $00, $FF
|
||||
ACMD4140: .byt $69, $40, $00
|
||||
.byt $00, $00, $77
|
||||
ACMD410: .byt $69, $00, $00
|
||||
.byt $00, $00, $FF
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2.3
|
||||
; Helper functions
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.export SDCMD
|
||||
.export GETR1
|
||||
.export GETR3
|
||||
.export GETBLOCK
|
||||
.export COMMAND
|
||||
.export CARDDET
|
||||
.export WRPROT
|
||||
.export INITED
|
||||
|
||||
|
||||
.include "AppleIISd.inc"
|
||||
.segment "EXTROM"
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Send SD command
|
||||
; Call with command in CMDHI and CMDLO
|
||||
;
|
||||
;*******************************
|
||||
|
||||
SDCMD: PHY
|
||||
LDY #0
|
||||
@LOOP: LDA (CMDLO),Y
|
||||
STA DATA,X
|
||||
@WAIT: LDA CTRL,X ; TC is in N
|
||||
BPL @WAIT
|
||||
INY
|
||||
CPY #6
|
||||
BCC @LOOP
|
||||
PLY
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Get R1
|
||||
; R1 is in A
|
||||
;
|
||||
;*******************************
|
||||
|
||||
GETR1: LDA #DUMMY
|
||||
STA DATA,X
|
||||
@WAIT: LDA CTRL,X
|
||||
BPL @WAIT
|
||||
LDA DATA,X ; get response
|
||||
BMI GETR1 ; wait for MSB=0
|
||||
PHA
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send another dummy
|
||||
PLA ; restore R1
|
||||
RTS
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Get R3 or R7
|
||||
; R1 is in A
|
||||
; R3 is in scratchpad ram
|
||||
;
|
||||
;*******************************
|
||||
|
||||
GETR3: JSR GETR1 ; get R1 first
|
||||
PHA ; save R1
|
||||
PHY ; save Y
|
||||
LDY #04 ; load counter
|
||||
JMP @WAIT ; first byte is already there
|
||||
@LOOP: LDA #DUMMY ; send dummy
|
||||
STA DATA,X
|
||||
@WAIT: LDA CTRL,X
|
||||
BPL @WAIT
|
||||
LDA DATA,X
|
||||
PHA
|
||||
DEY
|
||||
BNE @LOOP ; do 4 times
|
||||
LDY SLOT
|
||||
PLA
|
||||
STA R33,Y ; save R3
|
||||
PLA
|
||||
STA R32,Y
|
||||
PLA
|
||||
STA R31,Y
|
||||
PLA
|
||||
STA R30,Y ; R30 is MSB
|
||||
PLY ; restore Y
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send another dummy
|
||||
PLA ; restore R1
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Calculate block address
|
||||
; Unit number is in $43 DSSS0000
|
||||
; Block no is in $46-47
|
||||
; Address is in R30-R33
|
||||
;
|
||||
;*******************************
|
||||
|
||||
GETBLOCK: PHX ; save X
|
||||
PHY ; save Y
|
||||
LDX SLOT ; SLOT is now in X
|
||||
LDY SLOT16
|
||||
LDA BLOCKNUM ; store block num
|
||||
STA R33,X ; in R30-R33
|
||||
LDA BLOCKNUM+1
|
||||
STA R32,X
|
||||
STZ R31,X
|
||||
STZ R30,X
|
||||
|
||||
TYA ; get SLOT16
|
||||
EOR DSNUMBER
|
||||
AND #$70 ; check only slot bits
|
||||
BEQ @DRIVE ; it is our slot
|
||||
LDA #2 ; it is a phantom slot
|
||||
STA R31,X
|
||||
|
||||
@DRIVE: LDA DSNUMBER ; drive number
|
||||
BPL @SDHC ; D1
|
||||
LDA R31,X ; D2
|
||||
INC A
|
||||
STA R31,X
|
||||
|
||||
@SDHC: LDA #SDHC
|
||||
AND SS,Y ; if card is SDHC,
|
||||
BNE @END ; use block addressing
|
||||
|
||||
LDY #9 ; ASL can't be used with Y
|
||||
@LOOP: ASL R33,X ; mul block num
|
||||
ROL R32,X ; by 512 to get
|
||||
ROL R31,X ; real address
|
||||
ROL R30,X
|
||||
DEY
|
||||
BNE @LOOP
|
||||
|
||||
@END: PLY ; restore Y
|
||||
PLX ; restore X
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Send SD command
|
||||
; Cmd is in A
|
||||
;
|
||||
;*******************************
|
||||
|
||||
COMMAND: PHY ; save Y
|
||||
LDY SLOT
|
||||
STA DATA,X ; send command
|
||||
LDA R30,Y ; get arg from R30 on
|
||||
STA DATA,X
|
||||
LDA R31,Y
|
||||
STA DATA,X
|
||||
LDA R32,Y
|
||||
STA DATA,X
|
||||
LDA R33,Y
|
||||
STA DATA,X
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; dummy crc
|
||||
JSR GETR1
|
||||
PLY ; restore Y
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Check for card detect
|
||||
; X must contain SLOT16
|
||||
;
|
||||
; C Clear - card in slot
|
||||
; Set - no card in slot
|
||||
;
|
||||
;*******************************
|
||||
|
||||
CARDDET: PHA
|
||||
LDA #CD ; 0: card in
|
||||
BIT SS,X ; 1: card out
|
||||
CLC
|
||||
BEQ @DONE ; card is in
|
||||
SEC ; card is out
|
||||
@DONE: PLA
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Check for write protect
|
||||
; X must contain SLOT16
|
||||
;
|
||||
; C Clear - card not protected
|
||||
; Set - card write protected
|
||||
;
|
||||
;*******************************
|
||||
|
||||
WRPROT: PHA
|
||||
LDA #WP ; 0: write enabled
|
||||
BIT SS,X ; 1: write disabled
|
||||
CLC
|
||||
BEQ @DONE
|
||||
SEC
|
||||
@DONE: PLA
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Check if card is initialized
|
||||
; X must contain SLOT16
|
||||
;
|
||||
; C Clear - card initialized
|
||||
; Set - card not initialized
|
||||
;
|
||||
;*******************************
|
||||
|
||||
INITED: PHA
|
||||
LDA #CARD_INIT ; 0: card not initialized
|
||||
BIT SS,X ; 1: card initialized
|
||||
CLC
|
||||
BNE @DONE
|
||||
SEC
|
||||
@DONE: PLA
|
||||
RTS
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2.3
|
||||
; ProDOS functions
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.export PRODOS
|
||||
.export STATUS
|
||||
.export READ
|
||||
.export WRITE
|
||||
|
||||
.import COMMAND
|
||||
.import SDCMD
|
||||
.import GETBLOCK
|
||||
.import CARDDET
|
||||
.import INITED
|
||||
.import INIT
|
||||
.import WRPROT
|
||||
.import GETR1
|
||||
.import GETR3
|
||||
|
||||
.include "AppleIISd.inc"
|
||||
.segment "EXTROM"
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; ProDOS command dispatcher
|
||||
;
|
||||
; $42-$47 MLI input locations
|
||||
; X Slot*16
|
||||
; Y Slot
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $01 - Unknown command
|
||||
;
|
||||
;*******************************
|
||||
|
||||
PRODOS: LDA DCMD ; get command
|
||||
BEQ @STATUS ; branch if cmd is 0
|
||||
CMP #1
|
||||
BEQ @READ
|
||||
CMP #2
|
||||
BEQ @WRITE
|
||||
LDA #ERR_BADCMD ; unknown command
|
||||
SEC
|
||||
RTS
|
||||
|
||||
@STATUS: JMP STATUS
|
||||
@READ: JMP READ
|
||||
@WRITE: JMP WRITE
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Status request
|
||||
; $43 Unit number DSSS000
|
||||
; $44-45 Unused
|
||||
; $46-47 Unused
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $28 - No card inserted
|
||||
; $2B - Card write protected
|
||||
; X - Blocks avail (low byte)
|
||||
; Y - Blocks avail (high byte)
|
||||
;
|
||||
;*******************************
|
||||
|
||||
STATUS: LDA #NO_ERR ; Thanks for this one, Antoine!
|
||||
JSR CARDDET
|
||||
BCC @WRPROT
|
||||
LDA #ERR_NODRIVE; no card inserted
|
||||
BNE @DONE
|
||||
|
||||
@WRPROT: JSR WRPROT
|
||||
BCC @DONE
|
||||
LDA #ERR_NOWRITE; card write protected
|
||||
|
||||
@DONE: LDX #$FF ; 32 MB partition
|
||||
LDY #$FF
|
||||
RTS
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Read 512 byte block
|
||||
; $43 Unit number DSSS0000
|
||||
; $44-45 Address (LO/HI) of buffer
|
||||
; $46-47 Block number (LO/HI)
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $27 - Bad block number
|
||||
; $28 - No card inserted
|
||||
;
|
||||
;*******************************
|
||||
|
||||
READ: JSR CARDDET ; check for card
|
||||
BCS @NDERROR ; no card
|
||||
|
||||
JSR INITED ; check for initialization
|
||||
BCC @GETBLOCK
|
||||
|
||||
JSR INIT ; initialize card
|
||||
BCS @NDERROR ; init failed
|
||||
|
||||
@GETBLOCK: JSR GETBLOCK ; calc block address
|
||||
|
||||
LDA SS,X ; enable /CS
|
||||
AND #<~SS0
|
||||
STA SS,X
|
||||
LDA #$51 ; send CMD17
|
||||
JSR COMMAND ; send command
|
||||
CMP #0
|
||||
BNE @IOERROR ; check for error
|
||||
|
||||
@GETTOK: LDA #DUMMY ; get data token
|
||||
STA DATA,X
|
||||
LDA DATA,X ; get response
|
||||
CMP #$FE
|
||||
BNE @GETTOK ; wait for $FE
|
||||
|
||||
LDA CTRL,X ; enable FRX
|
||||
ORA #FRX
|
||||
STA CTRL,X
|
||||
LDA #DUMMY
|
||||
STA DATA,X
|
||||
|
||||
LDY #0
|
||||
@LOOP1: LDA DATA,X ; read data from card
|
||||
STA (BUFFER),Y
|
||||
INY
|
||||
BNE @LOOP1
|
||||
INC BUFFER+1 ; inc msb on page boundary
|
||||
@LOOP2: LDA DATA,X
|
||||
STA (BUFFER),Y
|
||||
INY
|
||||
BNE @LOOP2
|
||||
DEC BUFFER+1
|
||||
|
||||
@CRC: LDA DATA,X ; read two bytes crc
|
||||
LDA DATA,X ; and ignore
|
||||
LDA DATA,X ; read a dummy byte
|
||||
|
||||
LDA CTRL,X ; disable FRX
|
||||
AND #<~FRX
|
||||
STA CTRL,X
|
||||
CLC ; no error
|
||||
LDA #NO_ERR
|
||||
|
||||
@DONE: PHP
|
||||
PHA
|
||||
LDA SS,X
|
||||
ORA #SS0
|
||||
STA SS,X ; disable /CS
|
||||
PLA
|
||||
PLP
|
||||
RTS
|
||||
|
||||
@IOERROR: SEC ; an error occured
|
||||
LDA #ERR_IOERR
|
||||
BRA @DONE
|
||||
|
||||
@NDERROR: SEC ; an error occured
|
||||
LDA #ERR_NODRIVE
|
||||
BRA @DONE
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Write 512 byte block
|
||||
; $43 Unit number DSSS0000
|
||||
; $44-45 Address (LO/HI) of buffer
|
||||
; $46-47 Block number (LO/HI)
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $27 - I/O error or bad block number
|
||||
; $2B - Card write protected
|
||||
;
|
||||
;*******************************
|
||||
|
||||
WRITE: JSR WRPROT
|
||||
BCS @WPERROR ; card write protected
|
||||
|
||||
JSR GETBLOCK ; calc block address
|
||||
|
||||
LDA SS,X ; enable /CS
|
||||
AND #<~SS0
|
||||
STA SS,X
|
||||
LDA #$58 ; send CMD24
|
||||
JSR COMMAND ; send command
|
||||
CMP #0
|
||||
BNE @IOERROR ; check for error
|
||||
|
||||
LDA #DUMMY
|
||||
STA DATA,X ; send dummy
|
||||
LDA #$FE
|
||||
STA DATA,X ; send data token
|
||||
|
||||
LDY #0
|
||||
@LOOP1: LDA (BUFFER),Y
|
||||
STA DATA,X
|
||||
INY
|
||||
BNE @LOOP1
|
||||
INC BUFFER+1
|
||||
@LOOP2: LDA (BUFFER),Y
|
||||
STA DATA,X
|
||||
INY
|
||||
BNE @LOOP2
|
||||
DEC BUFFER+1
|
||||
|
||||
@CRC: LDA #DUMMY
|
||||
STA DATA,X ; send 2 dummy crc bytes
|
||||
STA DATA,X
|
||||
|
||||
STA DATA,X ; get data response
|
||||
LDA DATA,X
|
||||
AND #$1F
|
||||
CMP #$05
|
||||
BNE @IOERROR ; check for write error
|
||||
CLC ; no error
|
||||
LDA #NO_ERR
|
||||
|
||||
@DONE: PHP
|
||||
PHA
|
||||
@WAIT: LDA #DUMMY
|
||||
STA DATA,X ; wait for write cycle
|
||||
LDA DATA,X ; to complete
|
||||
BEQ @WAIT
|
||||
|
||||
LDA SS,X ; disable /CS
|
||||
ORA #SS0
|
||||
STA SS,X
|
||||
PLA
|
||||
PLP
|
||||
RTS
|
||||
|
||||
@IOERROR: SEC ; an error occured
|
||||
LDA #ERR_IOERR
|
||||
BRA @DONE
|
||||
|
||||
@WPERROR: SEC
|
||||
LDA #ERR_NOWRITE
|
||||
BRA @DONE
|
||||
|
|
@ -0,0 +1,418 @@
|
|||
;*******************************
|
||||
;
|
||||
; Apple][Sd Firmware
|
||||
; Version 1.2.3
|
||||
; Smartport functions
|
||||
;
|
||||
; (c) Florian Reitz, 2017 - 2021
|
||||
;
|
||||
; X register usually contains SLOT16
|
||||
; Y register is used for counting or SLOT
|
||||
;
|
||||
;*******************************
|
||||
|
||||
.export SMARTPORT
|
||||
|
||||
.import READ
|
||||
.import WRITE
|
||||
.import CARDDET
|
||||
.import WRPROT
|
||||
|
||||
.include "AppleIISd.inc"
|
||||
.segment "EXTROM"
|
||||
|
||||
|
||||
;*******************************
|
||||
;
|
||||
; Smartport command dispatcher
|
||||
;
|
||||
; $42-$47 MLI input locations
|
||||
; X Slot*16
|
||||
; Y Slot
|
||||
;
|
||||
; C Clear - No error
|
||||
; Set - Error
|
||||
; A $00 - No error
|
||||
; $01 - Unknown command
|
||||
;
|
||||
;*******************************
|
||||
|
||||
SMARTPORT: LDY #SMZPSIZE-1 ; save zeropage area for Smarport
|
||||
@SAVEZP: LDA SMZPAREA,Y
|
||||
PHA
|
||||
DEY
|
||||
BPL @SAVEZP
|
||||
|
||||
TSX ; get call address
|
||||
LDA $103+PDZPSIZE+SMZPSIZE,X
|
||||
STA SMPARAMLIST ; store temporarily
|
||||
CLC
|
||||
ADC #3 ; adjust return address
|
||||
STA $103+PDZPSIZE+SMZPSIZE,X
|
||||
LDA $104+PDZPSIZE+SMZPSIZE,X
|
||||
STA SMPARAMLIST+1
|
||||
ADC #0
|
||||
STA $104+PDZPSIZE+SMZPSIZE,X
|
||||
|
||||
LDY #1 ; get command code
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA SMCMD
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
TAX
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA SMPARAMLIST+1 ; is now parameter list
|
||||
STX SMPARAMLIST
|
||||
|
||||
LDA #ERR_BADCMD ; suspect bad command
|
||||
LDX SMCMD
|
||||
CPX #$09+1 ; command too large
|
||||
BCS @END
|
||||
|
||||
LDA (SMPARAMLIST) ; parameter count
|
||||
CMP REQPARAMCOUNT,X
|
||||
BNE @COUNTMISMATCH
|
||||
|
||||
LDY #1 ; get drive number
|
||||
LDA (SMPARAMLIST),Y
|
||||
LDY SLOT
|
||||
STA DRVNUM,Y
|
||||
|
||||
TXA ; SMCMD
|
||||
ASL A ; shift for use of word addresses
|
||||
TAX
|
||||
JSR @JMPSPCOMMAND ; Y holds SLOT
|
||||
BCS @END ; jump on error
|
||||
LDA #NO_ERR
|
||||
|
||||
@END: TAX ; save retval
|
||||
LDY #0 ; restore zeropage
|
||||
@RESTZP: PLA
|
||||
STA SMZPAREA,Y
|
||||
INY
|
||||
CPY #SMZPSIZE
|
||||
BCC @RESTZP
|
||||
|
||||
TXA
|
||||
;warum feste anzahl an bytes f<>r return wert?
|
||||
LDY #2 ; highbyte of # bytes transferred
|
||||
LDX #0 ; low byte of # bytes transferred
|
||||
;warum wird mit #1 verglichen?
|
||||
CMP #1 ; C=1 if A != NO_ERR
|
||||
RTS
|
||||
|
||||
@COUNTMISMATCH:
|
||||
LDA #ERR_BADPCNT
|
||||
BRA @END
|
||||
|
||||
@JMPSPCOMMAND: ; use offset from cmd*2
|
||||
JMP (SPDISPATCH,X)
|
||||
|
||||
|
||||
|
||||
; Smartport Status command
|
||||
;
|
||||
SMSTATUS: JSR GETCSLIST
|
||||
LDY SLOT
|
||||
LDA DRVNUM,Y
|
||||
BNE @PARTITION ; status call for a partition
|
||||
|
||||
LDA SMCSCODE
|
||||
BEQ @STATUS00 ; status call 0 for the bus
|
||||
LDA #ERR_BADCTL ; calls other than 0 are not allowed
|
||||
SEC
|
||||
RTS
|
||||
|
||||
; TODO support partitions based on card size
|
||||
@STATUS00: LDA #4 ; support 4 partitions
|
||||
STA (SMCMDLIST)
|
||||
|
||||
LDY #7
|
||||
@LOOP00: LDA STATUS00DATA-1,Y
|
||||
STA (SMCMDLIST),Y
|
||||
DEY
|
||||
BNE @LOOP00
|
||||
CLC
|
||||
RTS
|
||||
|
||||
@PARTITION: LDX SMCSCODE
|
||||
BEQ @STATUS03 ; 0: device status
|
||||
DEX
|
||||
BEQ @GETDCB ; 1: get DCB
|
||||
DEX
|
||||
DEX
|
||||
BEQ @STATUS03 ; 3: get DIB
|
||||
LDA #ERR_BADCTL
|
||||
SEC
|
||||
RTS
|
||||
|
||||
@GETDCB: LDA #1 ; return 'empty' DCB, one byte
|
||||
STA (SMCMDLIST)
|
||||
TAY
|
||||
LDA #NO_ERR
|
||||
STA (SMCMDLIST),Y
|
||||
CLC
|
||||
RTS
|
||||
|
||||
@STATUS03: LDA #$E8 ; block device, read, write, format,
|
||||
; not online, no write-protect
|
||||
LDX SLOT16
|
||||
JSR CARDDET
|
||||
BCS @WRPROT
|
||||
ORA #$10 ; card inserted
|
||||
@WRPROT: JSR WRPROT
|
||||
BCC @STATUSBYTE
|
||||
ORA #$04 ; SD card write-protected
|
||||
@STATUSBYTE:STA (SMCMDLIST)
|
||||
|
||||
LDY #1 ; block count, always $00FFFF
|
||||
LDA #$FF
|
||||
STA (SMCMDLIST),Y
|
||||
INY
|
||||
STA (SMCMDLIST),Y
|
||||
INY
|
||||
LDA #0
|
||||
STA (SMCMDLIST),Y
|
||||
|
||||
LDA SMCSCODE
|
||||
BEQ @DONE ; done if code 0, else get DIB, 21 bytes
|
||||
|
||||
LDY #4
|
||||
@LOOP: LDA STATUS3DATA-4,Y
|
||||
STA (SMCMDLIST),Y
|
||||
INY
|
||||
CPY #21+4
|
||||
BCC @LOOP
|
||||
|
||||
@DONE: CLC
|
||||
RTS
|
||||
|
||||
|
||||
; Smartport Control command
|
||||
;
|
||||
; no controls supported, yet
|
||||
;
|
||||
SMCONTROL: JSR GETCSLIST
|
||||
LDX SMCSCODE
|
||||
BEQ @RESET ; 0: Reset
|
||||
DEX
|
||||
BEQ @SETDCB ; 1: SetDCB
|
||||
DEX
|
||||
BEQ @NEWLINE ; 2: SetNewLine
|
||||
DEX
|
||||
BEQ @IRQ ; 3: ServiceInterrupt
|
||||
DEX
|
||||
BEQ @EJECT ; 4: Eject
|
||||
|
||||
@NEWLINE: LDA #ERR_BADCTL
|
||||
SEC
|
||||
@RESET:
|
||||
@SETDCB:
|
||||
@EJECT: LDA #NO_ERR ; only return OK
|
||||
CLC
|
||||
RTS
|
||||
|
||||
@IRQ: LDA #ERR_NOINT ; interrupts not supported
|
||||
SEC
|
||||
RTS
|
||||
|
||||
|
||||
; Get control/status list pointer and code
|
||||
;
|
||||
GETCSLIST: LDY #2
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA SMCMDLIST ; get buffer pointer
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA SMCMDLIST+1
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA SMCSCODE ; get status/control code
|
||||
RTS
|
||||
|
||||
|
||||
; Smartport Read Block command
|
||||
;
|
||||
; reads a 512-byte block using the ProDOS function
|
||||
;
|
||||
SMREADBLOCK:
|
||||
JSR TRANSLATE
|
||||
BCC @READ
|
||||
RTS
|
||||
|
||||
@READ: LDX SLOT16
|
||||
LDY SLOT
|
||||
JMP READ ; call ProDOS read
|
||||
|
||||
|
||||
|
||||
; Smartport Write Block command
|
||||
;
|
||||
; writes a 512-byte block using the ProDOS function
|
||||
;
|
||||
SMWRITEBLOCK:
|
||||
JSR TRANSLATE
|
||||
BCC @WRITE
|
||||
RTS
|
||||
|
||||
@WRITE: LDX SLOT16
|
||||
LDY SLOT
|
||||
JMP WRITE ; call ProDOS write
|
||||
|
||||
|
||||
; Translates the Smartport unit number to a ProDOS device
|
||||
; and prepares the block number
|
||||
;
|
||||
; Unit 0: entire chain, not supported
|
||||
; Unit 1: this slot, drive 0
|
||||
; Unit 2: this slot, drive 1
|
||||
; Unit 3: phantom slot, drive 0
|
||||
; Unit 4: phantom slot, drive 1
|
||||
;
|
||||
TRANSLATE: LDA DRVNUM,Y
|
||||
BEQ @BADUNIT ; not supportd for unit 0
|
||||
CMP #1
|
||||
BEQ @UNIT1
|
||||
CMP #2
|
||||
BEQ @UNIT2
|
||||
CMP #3
|
||||
BEQ @UNIT3
|
||||
CMP #4
|
||||
BEQ @UNIT4
|
||||
BRA @BADUNIT ; only 4 partitions are supported
|
||||
|
||||
@UNIT1: LDA SLOT16 ; this slot
|
||||
BRA @STORE
|
||||
@UNIT2: LDA SLOT16
|
||||
ORA #$80 ; drive 1
|
||||
BRA @STORE
|
||||
@UNIT3: LDA SLOT16
|
||||
DEC A ; phantom slot
|
||||
BRA @STORE
|
||||
@UNIT4: LDA SLOT16
|
||||
DEC A ; phantom slot
|
||||
ORA #$80 ; drive 1
|
||||
|
||||
@STORE: STA DSNUMBER ; store in ProDOS variable
|
||||
|
||||
LDY #2 ; get buffer pointer
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA BUFFER
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA BUFFER+1
|
||||
|
||||
INY ; get block number
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA BLOCKNUM
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
STA BLOCKNUM+1
|
||||
INY
|
||||
LDA (SMPARAMLIST),Y
|
||||
BNE @BADBLOCK ; bit 23-16 need to be 0
|
||||
|
||||
CLC
|
||||
RTS
|
||||
|
||||
@BADUNIT: LDA #ERR_BADUNIT
|
||||
SEC
|
||||
RTS
|
||||
|
||||
@BADBLOCK: LDA #ERR_BADBLOCK
|
||||
SEC
|
||||
RTS
|
||||
|
||||
|
||||
; Smartport Format command
|
||||
;
|
||||
; supported, but doesn't do anything
|
||||
; unit number must not be 0
|
||||
;
|
||||
SMFORMAT: LDA DRVNUM,Y
|
||||
BEQ @ERROR
|
||||
LDA #NO_ERR
|
||||
CLC
|
||||
RTS
|
||||
|
||||
@ERROR: LDA #ERR_BADUNIT
|
||||
SEC
|
||||
RTS
|
||||
|
||||
|
||||
; Smartport Init comand
|
||||
;
|
||||
; supported, but doesn't do anything
|
||||
; unit number must be 0
|
||||
;
|
||||
SMINIT: LDA DRVNUM,Y
|
||||
CLC
|
||||
BEQ @END ; error if not 0
|
||||
LDA #ERR_BADUNIT
|
||||
SEC
|
||||
@END: RTS
|
||||
|
||||
|
||||
; Smartport Open and Close commands
|
||||
;
|
||||
; supported for character devices, only
|
||||
;
|
||||
SMOPEN:
|
||||
SMCLOSE: LDA #ERR_BADCMD
|
||||
SEC
|
||||
RTS
|
||||
|
||||
|
||||
; Smartport Read Character and Write Character
|
||||
;
|
||||
; only 512-byte block operations are supported
|
||||
;
|
||||
SMREADCHAR:
|
||||
SMWRITECHAR:
|
||||
LDA #ERR_IOERR
|
||||
SEC
|
||||
RTS
|
||||
|
||||
|
||||
; Required parameter counts for the commands
|
||||
REQPARAMCOUNT:
|
||||
.byt 3 ; 0 = status
|
||||
.byt 3 ; 1 = read block
|
||||
.byt 3 ; 2 = write block
|
||||
.byt 1 ; 3 = format
|
||||
.byt 3 ; 4 = control
|
||||
.byt 1 ; 5 = init
|
||||
.byt 1 ; 6 = open
|
||||
.byt 1 ; 7 = close
|
||||
.byt 4 ; 8 = read char
|
||||
.byt 4 ; 9 = write char
|
||||
|
||||
; Command jump table
|
||||
SPDISPATCH:
|
||||
.word SMSTATUS
|
||||
.word SMREADBLOCK
|
||||
.word SMWRITEBLOCK
|
||||
.word SMFORMAT
|
||||
.word SMCONTROL
|
||||
.word SMINIT
|
||||
.word SMOPEN
|
||||
.word SMCLOSE
|
||||
.word SMREADCHAR
|
||||
.word SMWRITECHAR
|
||||
|
||||
; Status 00 command data
|
||||
STATUS00DATA:
|
||||
.byt $40 ; no interrupts
|
||||
.word $0000 ; unknown vendor
|
||||
.word SMDRIVERVER ; driver version
|
||||
.byt $00, $00 ; reserved
|
||||
.assert(*-STATUS00DATA)=7, error, "STATUS00DATA must be 7 bytes long"
|
||||
|
||||
; Status 3 command data
|
||||
STATUS3DATA:
|
||||
.byt 16, "APPLE][SD " ; ID length and string, padded
|
||||
.byt $02 ; hard disk
|
||||
.byt $00 ; removable hard disk
|
||||
.word SMDRIVERVER ; driver version
|
||||
.assert (*-STATUS3DATA)=21, error, "STATUS3DATA must be 21 bytes long"
|
||||
Binary file not shown.
|
|
@ -1,280 +0,0 @@
|
|||
G75*
|
||||
%MOIN*%
|
||||
%OFA0B0*%
|
||||
%FSLAX25Y25*%
|
||||
%IPPOS*%
|
||||
%LPD*%
|
||||
%AMOC8*
|
||||
5,1,8,0,0,1.08239X$1,22.5*
|
||||
%
|
||||
%ADD10C,0.01000*%
|
||||
%ADD11C,0.00000*%
|
||||
D10*
|
||||
X0306900Y0070642D02*
|
||||
X0306900Y0345445D01*
|
||||
X0701388Y0345445D01*
|
||||
X0701388Y0070642D01*
|
||||
X0663987Y0070642D01*
|
||||
X0663987Y0041902D01*
|
||||
X0661624Y0039540D01*
|
||||
X0407294Y0039540D01*
|
||||
X0404931Y0041902D01*
|
||||
X0404931Y0070642D01*
|
||||
X0306900Y0070642D01*
|
||||
D11*
|
||||
X0674203Y0122886D02*
|
||||
X0674205Y0123047D01*
|
||||
X0674211Y0123207D01*
|
||||
X0674221Y0123368D01*
|
||||
X0674235Y0123528D01*
|
||||
X0674253Y0123688D01*
|
||||
X0674274Y0123847D01*
|
||||
X0674300Y0124006D01*
|
||||
X0674330Y0124164D01*
|
||||
X0674363Y0124321D01*
|
||||
X0674401Y0124478D01*
|
||||
X0674442Y0124633D01*
|
||||
X0674487Y0124787D01*
|
||||
X0674536Y0124940D01*
|
||||
X0674589Y0125092D01*
|
||||
X0674645Y0125243D01*
|
||||
X0674706Y0125392D01*
|
||||
X0674769Y0125540D01*
|
||||
X0674837Y0125686D01*
|
||||
X0674908Y0125830D01*
|
||||
X0674982Y0125972D01*
|
||||
X0675060Y0126113D01*
|
||||
X0675142Y0126251D01*
|
||||
X0675227Y0126388D01*
|
||||
X0675315Y0126522D01*
|
||||
X0675407Y0126654D01*
|
||||
X0675502Y0126784D01*
|
||||
X0675600Y0126912D01*
|
||||
X0675701Y0127037D01*
|
||||
X0675805Y0127159D01*
|
||||
X0675912Y0127279D01*
|
||||
X0676022Y0127396D01*
|
||||
X0676135Y0127511D01*
|
||||
X0676251Y0127622D01*
|
||||
X0676370Y0127731D01*
|
||||
X0676491Y0127836D01*
|
||||
X0676615Y0127939D01*
|
||||
X0676741Y0128039D01*
|
||||
X0676869Y0128135D01*
|
||||
X0677000Y0128228D01*
|
||||
X0677134Y0128318D01*
|
||||
X0677269Y0128405D01*
|
||||
X0677407Y0128488D01*
|
||||
X0677546Y0128568D01*
|
||||
X0677688Y0128644D01*
|
||||
X0677831Y0128717D01*
|
||||
X0677976Y0128786D01*
|
||||
X0678123Y0128852D01*
|
||||
X0678271Y0128914D01*
|
||||
X0678421Y0128972D01*
|
||||
X0678572Y0129027D01*
|
||||
X0678725Y0129078D01*
|
||||
X0678879Y0129125D01*
|
||||
X0679034Y0129168D01*
|
||||
X0679190Y0129207D01*
|
||||
X0679346Y0129243D01*
|
||||
X0679504Y0129274D01*
|
||||
X0679662Y0129302D01*
|
||||
X0679821Y0129326D01*
|
||||
X0679981Y0129346D01*
|
||||
X0680141Y0129362D01*
|
||||
X0680301Y0129374D01*
|
||||
X0680462Y0129382D01*
|
||||
X0680623Y0129386D01*
|
||||
X0680783Y0129386D01*
|
||||
X0680944Y0129382D01*
|
||||
X0681105Y0129374D01*
|
||||
X0681265Y0129362D01*
|
||||
X0681425Y0129346D01*
|
||||
X0681585Y0129326D01*
|
||||
X0681744Y0129302D01*
|
||||
X0681902Y0129274D01*
|
||||
X0682060Y0129243D01*
|
||||
X0682216Y0129207D01*
|
||||
X0682372Y0129168D01*
|
||||
X0682527Y0129125D01*
|
||||
X0682681Y0129078D01*
|
||||
X0682834Y0129027D01*
|
||||
X0682985Y0128972D01*
|
||||
X0683135Y0128914D01*
|
||||
X0683283Y0128852D01*
|
||||
X0683430Y0128786D01*
|
||||
X0683575Y0128717D01*
|
||||
X0683718Y0128644D01*
|
||||
X0683860Y0128568D01*
|
||||
X0683999Y0128488D01*
|
||||
X0684137Y0128405D01*
|
||||
X0684272Y0128318D01*
|
||||
X0684406Y0128228D01*
|
||||
X0684537Y0128135D01*
|
||||
X0684665Y0128039D01*
|
||||
X0684791Y0127939D01*
|
||||
X0684915Y0127836D01*
|
||||
X0685036Y0127731D01*
|
||||
X0685155Y0127622D01*
|
||||
X0685271Y0127511D01*
|
||||
X0685384Y0127396D01*
|
||||
X0685494Y0127279D01*
|
||||
X0685601Y0127159D01*
|
||||
X0685705Y0127037D01*
|
||||
X0685806Y0126912D01*
|
||||
X0685904Y0126784D01*
|
||||
X0685999Y0126654D01*
|
||||
X0686091Y0126522D01*
|
||||
X0686179Y0126388D01*
|
||||
X0686264Y0126251D01*
|
||||
X0686346Y0126113D01*
|
||||
X0686424Y0125972D01*
|
||||
X0686498Y0125830D01*
|
||||
X0686569Y0125686D01*
|
||||
X0686637Y0125540D01*
|
||||
X0686700Y0125392D01*
|
||||
X0686761Y0125243D01*
|
||||
X0686817Y0125092D01*
|
||||
X0686870Y0124940D01*
|
||||
X0686919Y0124787D01*
|
||||
X0686964Y0124633D01*
|
||||
X0687005Y0124478D01*
|
||||
X0687043Y0124321D01*
|
||||
X0687076Y0124164D01*
|
||||
X0687106Y0124006D01*
|
||||
X0687132Y0123847D01*
|
||||
X0687153Y0123688D01*
|
||||
X0687171Y0123528D01*
|
||||
X0687185Y0123368D01*
|
||||
X0687195Y0123207D01*
|
||||
X0687201Y0123047D01*
|
||||
X0687203Y0122886D01*
|
||||
X0687201Y0122725D01*
|
||||
X0687195Y0122565D01*
|
||||
X0687185Y0122404D01*
|
||||
X0687171Y0122244D01*
|
||||
X0687153Y0122084D01*
|
||||
X0687132Y0121925D01*
|
||||
X0687106Y0121766D01*
|
||||
X0687076Y0121608D01*
|
||||
X0687043Y0121451D01*
|
||||
X0687005Y0121294D01*
|
||||
X0686964Y0121139D01*
|
||||
X0686919Y0120985D01*
|
||||
X0686870Y0120832D01*
|
||||
X0686817Y0120680D01*
|
||||
X0686761Y0120529D01*
|
||||
X0686700Y0120380D01*
|
||||
X0686637Y0120232D01*
|
||||
X0686569Y0120086D01*
|
||||
X0686498Y0119942D01*
|
||||
X0686424Y0119800D01*
|
||||
X0686346Y0119659D01*
|
||||
X0686264Y0119521D01*
|
||||
X0686179Y0119384D01*
|
||||
X0686091Y0119250D01*
|
||||
X0685999Y0119118D01*
|
||||
X0685904Y0118988D01*
|
||||
X0685806Y0118860D01*
|
||||
X0685705Y0118735D01*
|
||||
X0685601Y0118613D01*
|
||||
X0685494Y0118493D01*
|
||||
X0685384Y0118376D01*
|
||||
X0685271Y0118261D01*
|
||||
X0685155Y0118150D01*
|
||||
X0685036Y0118041D01*
|
||||
X0684915Y0117936D01*
|
||||
X0684791Y0117833D01*
|
||||
X0684665Y0117733D01*
|
||||
X0684537Y0117637D01*
|
||||
X0684406Y0117544D01*
|
||||
X0684272Y0117454D01*
|
||||
X0684137Y0117367D01*
|
||||
X0683999Y0117284D01*
|
||||
X0683860Y0117204D01*
|
||||
X0683718Y0117128D01*
|
||||
X0683575Y0117055D01*
|
||||
X0683430Y0116986D01*
|
||||
X0683283Y0116920D01*
|
||||
X0683135Y0116858D01*
|
||||
X0682985Y0116800D01*
|
||||
X0682834Y0116745D01*
|
||||
X0682681Y0116694D01*
|
||||
X0682527Y0116647D01*
|
||||
X0682372Y0116604D01*
|
||||
X0682216Y0116565D01*
|
||||
X0682060Y0116529D01*
|
||||
X0681902Y0116498D01*
|
||||
X0681744Y0116470D01*
|
||||
X0681585Y0116446D01*
|
||||
X0681425Y0116426D01*
|
||||
X0681265Y0116410D01*
|
||||
X0681105Y0116398D01*
|
||||
X0680944Y0116390D01*
|
||||
X0680783Y0116386D01*
|
||||
X0680623Y0116386D01*
|
||||
X0680462Y0116390D01*
|
||||
X0680301Y0116398D01*
|
||||
X0680141Y0116410D01*
|
||||
X0679981Y0116426D01*
|
||||
X0679821Y0116446D01*
|
||||
X0679662Y0116470D01*
|
||||
X0679504Y0116498D01*
|
||||
X0679346Y0116529D01*
|
||||
X0679190Y0116565D01*
|
||||
X0679034Y0116604D01*
|
||||
X0678879Y0116647D01*
|
||||
X0678725Y0116694D01*
|
||||
X0678572Y0116745D01*
|
||||
X0678421Y0116800D01*
|
||||
X0678271Y0116858D01*
|
||||
X0678123Y0116920D01*
|
||||
X0677976Y0116986D01*
|
||||
X0677831Y0117055D01*
|
||||
X0677688Y0117128D01*
|
||||
X0677546Y0117204D01*
|
||||
X0677407Y0117284D01*
|
||||
X0677269Y0117367D01*
|
||||
X0677134Y0117454D01*
|
||||
X0677000Y0117544D01*
|
||||
X0676869Y0117637D01*
|
||||
X0676741Y0117733D01*
|
||||
X0676615Y0117833D01*
|
||||
X0676491Y0117936D01*
|
||||
X0676370Y0118041D01*
|
||||
X0676251Y0118150D01*
|
||||
X0676135Y0118261D01*
|
||||
X0676022Y0118376D01*
|
||||
X0675912Y0118493D01*
|
||||
X0675805Y0118613D01*
|
||||
X0675701Y0118735D01*
|
||||
X0675600Y0118860D01*
|
||||
X0675502Y0118988D01*
|
||||
X0675407Y0119118D01*
|
||||
X0675315Y0119250D01*
|
||||
X0675227Y0119384D01*
|
||||
X0675142Y0119521D01*
|
||||
X0675060Y0119659D01*
|
||||
X0674982Y0119800D01*
|
||||
X0674908Y0119942D01*
|
||||
X0674837Y0120086D01*
|
||||
X0674769Y0120232D01*
|
||||
X0674706Y0120380D01*
|
||||
X0674645Y0120529D01*
|
||||
X0674589Y0120680D01*
|
||||
X0674536Y0120832D01*
|
||||
X0674487Y0120985D01*
|
||||
X0674442Y0121139D01*
|
||||
X0674401Y0121294D01*
|
||||
X0674363Y0121451D01*
|
||||
X0674330Y0121608D01*
|
||||
X0674300Y0121766D01*
|
||||
X0674274Y0121925D01*
|
||||
X0674253Y0122084D01*
|
||||
X0674235Y0122244D01*
|
||||
X0674221Y0122404D01*
|
||||
X0674211Y0122565D01*
|
||||
X0674205Y0122725D01*
|
||||
X0674203Y0122886D01*
|
||||
M02*
|
||||
|
|
@ -1,738 +0,0 @@
|
|||
G75*
|
||||
%MOIN*%
|
||||
%OFA0B0*%
|
||||
%FSLAX25Y25*%
|
||||
%IPPOS*%
|
||||
%LPD*%
|
||||
%AMOC8*
|
||||
5,1,8,0,0,1.08239X$1,22.5*
|
||||
%
|
||||
%ADD10R,0.06000X0.25500*%
|
||||
%ADD11C,0.04775*%
|
||||
%ADD12OC8,0.04775*%
|
||||
%ADD13C,0.04775*%
|
||||
%ADD14C,0.05575*%
|
||||
%ADD15OC8,0.06300*%
|
||||
%ADD16C,0.06300*%
|
||||
%ADD17R,0.03937X0.04331*%
|
||||
%ADD18R,0.04331X0.03937*%
|
||||
%ADD19R,0.03937X0.06299*%
|
||||
%ADD20C,0.07874*%
|
||||
%ADD21R,0.06890X0.04724*%
|
||||
%ADD22R,0.06890X0.03937*%
|
||||
%ADD23R,0.04134X0.04252*%
|
||||
%ADD24C,0.01575*%
|
||||
%ADD25C,0.02559*%
|
||||
%ADD26C,0.02362*%
|
||||
D10*
|
||||
X0414400Y0057433D03*
|
||||
X0424400Y0057433D03*
|
||||
X0434400Y0057433D03*
|
||||
X0444400Y0057433D03*
|
||||
X0454400Y0057433D03*
|
||||
X0464400Y0057433D03*
|
||||
X0474400Y0057433D03*
|
||||
X0484400Y0057433D03*
|
||||
X0494400Y0057433D03*
|
||||
X0504400Y0057433D03*
|
||||
X0514400Y0057433D03*
|
||||
X0524400Y0057433D03*
|
||||
X0534400Y0057433D03*
|
||||
X0544400Y0057433D03*
|
||||
X0554400Y0057433D03*
|
||||
X0564400Y0057433D03*
|
||||
X0574400Y0057433D03*
|
||||
X0584400Y0057433D03*
|
||||
X0594400Y0057433D03*
|
||||
X0604400Y0057433D03*
|
||||
X0614400Y0057433D03*
|
||||
X0624400Y0057433D03*
|
||||
X0634400Y0057433D03*
|
||||
X0644400Y0057433D03*
|
||||
X0654400Y0057433D03*
|
||||
D11*
|
||||
X0456821Y0317729D03*
|
||||
D12*
|
||||
X0446821Y0317729D03*
|
||||
X0436821Y0317729D03*
|
||||
X0426821Y0317729D03*
|
||||
X0416821Y0317729D03*
|
||||
X0416821Y0307729D03*
|
||||
X0426821Y0307729D03*
|
||||
X0426821Y0297729D03*
|
||||
X0416821Y0297729D03*
|
||||
X0416821Y0287729D03*
|
||||
X0426821Y0287729D03*
|
||||
X0426821Y0277729D03*
|
||||
X0416821Y0277729D03*
|
||||
X0416821Y0267729D03*
|
||||
X0426821Y0267729D03*
|
||||
X0436821Y0267729D03*
|
||||
X0446821Y0267729D03*
|
||||
X0456821Y0267729D03*
|
||||
X0466821Y0267729D03*
|
||||
X0476821Y0267729D03*
|
||||
X0486821Y0267729D03*
|
||||
X0486821Y0277729D03*
|
||||
X0476821Y0277729D03*
|
||||
X0476821Y0287729D03*
|
||||
X0486821Y0287729D03*
|
||||
X0486821Y0297729D03*
|
||||
X0476821Y0297729D03*
|
||||
X0476821Y0307729D03*
|
||||
X0486821Y0307729D03*
|
||||
X0486821Y0317729D03*
|
||||
X0476821Y0317729D03*
|
||||
X0466821Y0317729D03*
|
||||
X0466821Y0327729D03*
|
||||
X0476821Y0327729D03*
|
||||
X0456821Y0327729D03*
|
||||
X0446821Y0327729D03*
|
||||
X0436821Y0327729D03*
|
||||
X0426821Y0327729D03*
|
||||
X0531743Y0331548D03*
|
||||
X0531743Y0321548D03*
|
||||
X0476821Y0257729D03*
|
||||
X0466821Y0257729D03*
|
||||
X0456821Y0257729D03*
|
||||
X0446821Y0257729D03*
|
||||
X0436821Y0257729D03*
|
||||
X0426821Y0257729D03*
|
||||
D13*
|
||||
X0429144Y0219722D02*
|
||||
X0429144Y0214948D01*
|
||||
X0419144Y0214948D02*
|
||||
X0419144Y0219722D01*
|
||||
X0409144Y0219722D02*
|
||||
X0409144Y0214948D01*
|
||||
X0399144Y0214948D02*
|
||||
X0399144Y0219722D01*
|
||||
X0389144Y0219722D02*
|
||||
X0389144Y0214948D01*
|
||||
X0379144Y0214948D02*
|
||||
X0379144Y0219722D01*
|
||||
X0439144Y0219722D02*
|
||||
X0439144Y0214948D01*
|
||||
X0449144Y0214948D02*
|
||||
X0449144Y0219722D01*
|
||||
X0459144Y0219722D02*
|
||||
X0459144Y0214948D01*
|
||||
X0469144Y0214948D02*
|
||||
X0469144Y0219722D01*
|
||||
X0479144Y0219722D02*
|
||||
X0479144Y0214948D01*
|
||||
X0489144Y0214948D02*
|
||||
X0489144Y0219722D01*
|
||||
X0489144Y0159722D02*
|
||||
X0489144Y0154948D01*
|
||||
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|
||||
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|
||||
X0469144Y0159722D02*
|
||||
X0469144Y0154948D01*
|
||||
X0459144Y0154948D02*
|
||||
X0459144Y0159722D01*
|
||||
X0449144Y0159722D02*
|
||||
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|
||||
X0439144Y0154948D02*
|
||||
X0439144Y0159722D01*
|
||||
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|
||||
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|
||||
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|
||||
X0419144Y0159722D01*
|
||||
X0409144Y0159722D02*
|
||||
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|
||||
X0399144Y0154948D02*
|
||||
X0399144Y0159722D01*
|
||||
X0389144Y0159722D02*
|
||||
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|
||||
X0379144Y0154948D02*
|
||||
X0379144Y0159722D01*
|
||||
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|
||||
X0419302Y0122822D01*
|
||||
X0429302Y0122822D02*
|
||||
X0429302Y0127596D01*
|
||||
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|
||||
X0439302Y0122822D01*
|
||||
X0449302Y0122822D02*
|
||||
X0449302Y0127596D01*
|
||||
X0459302Y0127596D02*
|
||||
X0459302Y0122822D01*
|
||||
X0469302Y0122822D02*
|
||||
X0469302Y0127596D01*
|
||||
X0479302Y0127596D02*
|
||||
X0479302Y0122822D01*
|
||||
X0489302Y0122822D02*
|
||||
X0489302Y0127596D01*
|
||||
X0499302Y0127596D02*
|
||||
X0499302Y0122822D01*
|
||||
X0509302Y0122822D02*
|
||||
X0509302Y0127596D01*
|
||||
X0509302Y0097596D02*
|
||||
X0509302Y0092822D01*
|
||||
X0499302Y0092822D02*
|
||||
X0499302Y0097596D01*
|
||||
X0489302Y0097596D02*
|
||||
X0489302Y0092822D01*
|
||||
X0479302Y0092822D02*
|
||||
X0479302Y0097596D01*
|
||||
X0469302Y0097596D02*
|
||||
X0469302Y0092822D01*
|
||||
X0459302Y0092822D02*
|
||||
X0459302Y0097596D01*
|
||||
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|
||||
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|
||||
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|
||||
X0439302Y0097596D01*
|
||||
X0429302Y0097596D02*
|
||||
X0429302Y0092822D01*
|
||||
X0419302Y0092822D02*
|
||||
X0419302Y0097596D01*
|
||||
D14*
|
||||
X0618916Y0112886D02*
|
||||
X0624491Y0112886D01*
|
||||
X0624491Y0122886D02*
|
||||
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|
||||
X0618916Y0132886D02*
|
||||
X0624491Y0132886D01*
|
||||
X0498987Y0230059D02*
|
||||
X0498987Y0235634D01*
|
||||
X0488987Y0235634D02*
|
||||
X0488987Y0230059D01*
|
||||
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|
||||
X0478987Y0235634D01*
|
||||
X0367758Y0282650D02*
|
||||
X0362183Y0282650D01*
|
||||
X0362183Y0292650D02*
|
||||
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|
||||
X0367758Y0302650D02*
|
||||
X0362183Y0302650D01*
|
||||
X0362183Y0312650D02*
|
||||
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|
||||
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|
||||
X0362183Y0322650D01*
|
||||
X0362183Y0332650D02*
|
||||
X0367758Y0332650D01*
|
||||
D15*
|
||||
X0598858Y0122689D03*
|
||||
D16*
|
||||
X0608858Y0122689D03*
|
||||
D17*
|
||||
X0609420Y0149264D03*
|
||||
X0602727Y0149264D03*
|
||||
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|
||||
X0625168Y0149146D03*
|
||||
X0613396Y0096036D03*
|
||||
X0606703Y0096036D03*
|
||||
D18*
|
||||
X0605128Y0180288D03*
|
||||
X0595286Y0180288D03*
|
||||
X0595286Y0186981D03*
|
||||
X0605128Y0186981D03*
|
||||
X0614971Y0186981D03*
|
||||
X0614971Y0180288D03*
|
||||
X0663396Y0180327D03*
|
||||
X0663396Y0187020D03*
|
||||
X0673042Y0186981D03*
|
||||
X0673042Y0180288D03*
|
||||
X0694695Y0251154D03*
|
||||
X0694695Y0257847D03*
|
||||
X0694695Y0264933D03*
|
||||
X0694695Y0271626D03*
|
||||
X0531624Y0304343D03*
|
||||
X0531624Y0311036D03*
|
||||
D19*
|
||||
X0594794Y0199382D03*
|
||||
X0604636Y0199382D03*
|
||||
X0614479Y0199382D03*
|
||||
X0624321Y0199382D03*
|
||||
X0634164Y0199382D03*
|
||||
X0644006Y0199382D03*
|
||||
X0653849Y0199382D03*
|
||||
X0663691Y0199382D03*
|
||||
X0670187Y0199382D03*
|
||||
D20*
|
||||
X0684459Y0294658D03*
|
||||
X0574420Y0294658D03*
|
||||
D21*
|
||||
X0683376Y0243870D03*
|
||||
D22*
|
||||
X0683376Y0278516D03*
|
||||
X0683376Y0283634D03*
|
||||
D23*
|
||||
X0613494Y0104894D03*
|
||||
X0606605Y0104894D03*
|
||||
D24*
|
||||
X0607097Y0105386D01*
|
||||
X0607097Y0112768D01*
|
||||
X0598858Y0121007D01*
|
||||
X0598858Y0122689D01*
|
||||
X0599223Y0123054D01*
|
||||
X0599223Y0133437D01*
|
||||
X0602727Y0136941D01*
|
||||
X0602727Y0149264D01*
|
||||
X0609420Y0149264D02*
|
||||
X0618357Y0149264D01*
|
||||
X0618475Y0149146D01*
|
||||
X0618475Y0142729D01*
|
||||
X0621861Y0139343D01*
|
||||
X0621861Y0133044D01*
|
||||
X0621703Y0132886D01*
|
||||
X0629026Y0122886D02*
|
||||
X0634459Y0128319D01*
|
||||
X0634459Y0149308D01*
|
||||
X0634297Y0149146D01*
|
||||
X0625168Y0149146D01*
|
||||
X0634459Y0149308D02*
|
||||
X0634459Y0180449D01*
|
||||
X0634621Y0180288D01*
|
||||
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|
||||
X0554931Y0092099D03*
|
||||
X0559853Y0092099D03*
|
||||
X0613987Y0089146D03*
|
||||
X0530325Y0157059D03*
|
||||
X0624813Y0193477D03*
|
||||
X0654341Y0193477D03*
|
||||
X0663199Y0230878D03*
|
||||
X0633672Y0237768D03*
|
||||
X0633672Y0247610D03*
|
||||
X0559853Y0227925D03*
|
||||
X0554931Y0231862D03*
|
||||
X0531309Y0240721D03*
|
||||
X0509302Y0232847D03*
|
||||
X0500798Y0240721D03*
|
||||
X0496861Y0243673D03*
|
||||
X0520483Y0261390D03*
|
||||
X0545089Y0279107D03*
|
||||
X0472254Y0262374D03*
|
||||
X0441743Y0262374D03*
|
||||
X0419105Y0262374D03*
|
||||
X0441743Y0242689D03*
|
||||
X0454538Y0224973D03*
|
||||
X0440758Y0293870D03*
|
||||
X0451585Y0301744D03*
|
||||
X0447648Y0306666D03*
|
||||
X0379735Y0297807D03*
|
||||
D26*
|
||||
X0517530Y0249579D03*
|
||||
X0546073Y0240721D03*
|
||||
X0548042Y0243673D03*
|
||||
X0551979Y0237768D03*
|
||||
X0547057Y0234815D03*
|
||||
X0404341Y0117689D03*
|
||||
X0394498Y0114736D03*
|
||||
X0384656Y0111784D03*
|
||||
X0517530Y0091114D03*
|
||||
X0520483Y0083240D03*
|
||||
X0634656Y0074382D03*
|
||||
X0644498Y0074382D03*
|
||||
M02*
|
||||
|
|
@ -1,171 +0,0 @@
|
|||
%
|
||||
M48
|
||||
M72
|
||||
T01C0.01181
|
||||
T02C0.01378
|
||||
T03C0.03200
|
||||
T04C0.04000
|
||||
T05C0.06299
|
||||
T06C0.13000
|
||||
%
|
||||
T01
|
||||
X384656Y111784
|
||||
X394498Y114736
|
||||
X404341Y117689
|
||||
X517530Y91114
|
||||
X520483Y83240
|
||||
X634656Y74382
|
||||
X644498Y74382
|
||||
X547057Y234815
|
||||
X551979Y237768
|
||||
X546073Y240721
|
||||
X548042Y243673
|
||||
X517530Y249579
|
||||
T02
|
||||
X373829Y166902
|
||||
X414183Y174776
|
||||
X428947Y174776
|
||||
X428947Y132453
|
||||
X499813Y135406
|
||||
X533278Y125563
|
||||
X530325Y95051
|
||||
X533278Y90130
|
||||
X533278Y79303
|
||||
X554931Y92099
|
||||
X559853Y92099
|
||||
X613987Y89146
|
||||
X530325Y157059
|
||||
X624813Y193477
|
||||
X654341Y193477
|
||||
X663199Y230878
|
||||
X633672Y237768
|
||||
X633672Y247610
|
||||
X559853Y227925
|
||||
X554931Y231862
|
||||
X531309Y240721
|
||||
X509302Y232847
|
||||
X500798Y240721
|
||||
X496861Y243673
|
||||
X520483Y261390
|
||||
X545089Y279107
|
||||
X472254Y262374
|
||||
X441743Y262374
|
||||
X419105Y262374
|
||||
X441743Y242689
|
||||
X454538Y224973
|
||||
X440758Y293870
|
||||
X451585Y301744
|
||||
X447648Y306666
|
||||
X379735Y297807
|
||||
T03
|
||||
X416821Y297729
|
||||
X426821Y297729
|
||||
X426821Y307729
|
||||
X416821Y307729
|
||||
X416821Y317729
|
||||
X426821Y317729
|
||||
X436821Y317729
|
||||
X446821Y317729
|
||||
X456821Y317729
|
||||
X466821Y317729
|
||||
X476821Y317729
|
||||
X486821Y317729
|
||||
X486821Y307729
|
||||
X476821Y307729
|
||||
X476821Y297729
|
||||
X486821Y297729
|
||||
X486821Y287729
|
||||
X476821Y287729
|
||||
X476821Y277729
|
||||
X486821Y277729
|
||||
X486821Y267729
|
||||
X476821Y267729
|
||||
X466821Y267729
|
||||
X456821Y267729
|
||||
X446821Y267729
|
||||
X436821Y267729
|
||||
X426821Y267729
|
||||
X426821Y277729
|
||||
X416821Y277729
|
||||
X416821Y267729
|
||||
X426821Y257729
|
||||
X436821Y257729
|
||||
X446821Y257729
|
||||
X456821Y257729
|
||||
X466821Y257729
|
||||
X476821Y257729
|
||||
X426821Y287729
|
||||
X416821Y287729
|
||||
X426821Y327729
|
||||
X436821Y327729
|
||||
X446821Y327729
|
||||
X456821Y327729
|
||||
X466821Y327729
|
||||
X476821Y327729
|
||||
X531743Y331548
|
||||
X531743Y321548
|
||||
X489144Y217335
|
||||
X479144Y217335
|
||||
X469144Y217335
|
||||
X459144Y217335
|
||||
X449144Y217335
|
||||
X439144Y217335
|
||||
X429144Y217335
|
||||
X419144Y217335
|
||||
X409144Y217335
|
||||
X399144Y217335
|
||||
X389144Y217335
|
||||
X379144Y217335
|
||||
X379144Y157335
|
||||
X389144Y157335
|
||||
X399144Y157335
|
||||
X409144Y157335
|
||||
X419144Y157335
|
||||
X429144Y157335
|
||||
X439144Y157335
|
||||
X449144Y157335
|
||||
X459144Y157335
|
||||
X469144Y157335
|
||||
X479144Y157335
|
||||
X489144Y157335
|
||||
X489302Y125209
|
||||
X499302Y125209
|
||||
X509302Y125209
|
||||
X479302Y125209
|
||||
X469302Y125209
|
||||
X459302Y125209
|
||||
X449302Y125209
|
||||
X439302Y125209
|
||||
X429302Y125209
|
||||
X419302Y125209
|
||||
X419302Y95209
|
||||
X429302Y95209
|
||||
X439302Y95209
|
||||
X449302Y95209
|
||||
X459302Y95209
|
||||
X469302Y95209
|
||||
X479302Y95209
|
||||
X489302Y95209
|
||||
X499302Y95209
|
||||
X509302Y95209
|
||||
X598858Y122689
|
||||
X608858Y122689
|
||||
T04
|
||||
X621703Y122886
|
||||
X621703Y112886
|
||||
X621703Y132886
|
||||
X498987Y232847
|
||||
X488987Y232847
|
||||
X478987Y232847
|
||||
X364971Y282650
|
||||
X364971Y292650
|
||||
X364971Y302650
|
||||
X364971Y312650
|
||||
X364971Y322650
|
||||
X364971Y332650
|
||||
T05
|
||||
X574420Y294658
|
||||
X684459Y294658
|
||||
T06
|
||||
X680703Y122886
|
||||
M30
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
Generated by EAGLE CAM Processor 7.7.0
|
||||
|
||||
Drill Station Info File: //LUDWIG-FS/Vertrieb/TEMP/RZF/AppleIISd/SD_A2.dri
|
||||
|
||||
Date : 18.07.2017 10:20
|
||||
Drills : generated
|
||||
Device : Excellon drill station, coordinate format 2.5 inch
|
||||
|
||||
Parameter settings:
|
||||
|
||||
Tolerance Drill + : 2.50 %
|
||||
Tolerance Drill - : 2.50 %
|
||||
Rotate : no
|
||||
Mirror : no
|
||||
Optimize : yes
|
||||
Auto fit : yes
|
||||
OffsetX : 0inch
|
||||
OffsetY : 0inch
|
||||
Layers : Drills Holes
|
||||
|
||||
Drill File Info:
|
||||
|
||||
Data Mode : Absolute
|
||||
Units : 1/100000 Inch
|
||||
|
||||
Drills used:
|
||||
|
||||
Code Size used
|
||||
|
||||
T01 0.0118inch 12
|
||||
T02 0.0138inch 35
|
||||
T03 0.0320inch 92
|
||||
T04 0.0400inch 12
|
||||
T05 0.0630inch 2
|
||||
T06 0.1300inch 1
|
||||
|
||||
Total number of drills: 154
|
||||
|
||||
Plotfiles:
|
||||
|
||||
//LUDWIG-FS/Vertrieb/TEMP/RZF/AppleIISd/SD_A2.drd
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
Generated by EAGLE CAM Processor 7.7.0
|
||||
|
||||
Photoplotter Info File: //LUDWIG-FS/Vertrieb/TEMP/RZF/AppleIISd/SD_A2.gpi
|
||||
|
||||
Date : 18.07.2017 10:20
|
||||
Plotfile : //LUDWIG-FS/Vertrieb/TEMP/RZF/AppleIISd/SD_A2.sts
|
||||
Apertures : generated:
|
||||
Device : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
|
||||
|
||||
Parameter settings:
|
||||
|
||||
Emulate Apertures : no
|
||||
Tolerance Draw + : 0.00 %
|
||||
Tolerance Draw - : 0.00 %
|
||||
Tolerance Flash + : 0.00 %
|
||||
Tolerance Flash - : 0.00 %
|
||||
Rotate : no
|
||||
Mirror : no
|
||||
Optimize : yes
|
||||
Auto fit : yes
|
||||
OffsetX : 0inch
|
||||
OffsetY : 0inch
|
||||
|
||||
Plotfile Info:
|
||||
|
||||
Coordinate Format : 2.5
|
||||
Coordinate Units : Inch
|
||||
Data Mode : Absolute
|
||||
Zero Suppression : None
|
||||
End Of Block : *
|
||||
|
||||
Apertures used:
|
||||
|
||||
Code Shape Size used
|
||||
|
||||
D10 rectangle 0.0659inch x 0.2609inch 25
|
||||
D11 round 0.0537inch 1
|
||||
D12 octagon 0.0537inch 45
|
||||
D13 draw 0.0537inch 44
|
||||
D14 draw 0.0617inch 12
|
||||
D15 round 0.1359inch 1
|
||||
D16 octagon 0.0689inch 1
|
||||
D17 round 0.0689inch 1
|
||||
D18 round 0.0846inch 2
|
||||
D19 rectangle 0.0472inch x 0.0484inch 4
|
||||
D20 rectangle 0.0484inch x 0.0472inch 12
|
||||
D21 round 0.0315inch 35
|
||||
D22 round 0.0295inch 12
|
||||
|
||||
|
||||
Layers:
|
||||
|
||||
*.cmp Top Layer
|
||||
*.sol Bottom Layer
|
||||
*.M1 Board Outline
|
||||
*.stc Top Soldermask
|
||||
*.sts Bottom Soldermask
|
||||
*.plc Top Silk
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,315 +0,0 @@
|
|||
G75*
|
||||
%MOIN*%
|
||||
%OFA0B0*%
|
||||
%FSLAX25Y25*%
|
||||
%IPPOS*%
|
||||
%LPD*%
|
||||
%AMOC8*
|
||||
5,1,8,0,0,1.08239X$1,22.5*
|
||||
%
|
||||
%ADD10R,0.06591X0.26091*%
|
||||
%ADD11C,0.05365*%
|
||||
%ADD12OC8,0.05365*%
|
||||
%ADD13C,0.05365*%
|
||||
%ADD14C,0.06165*%
|
||||
%ADD15C,0.13591*%
|
||||
%ADD16OC8,0.06891*%
|
||||
%ADD17C,0.06891*%
|
||||
%ADD18R,0.04528X0.04921*%
|
||||
%ADD19R,0.04921X0.04528*%
|
||||
%ADD20R,0.04528X0.06890*%
|
||||
%ADD21C,0.08465*%
|
||||
%ADD22R,0.07480X0.05315*%
|
||||
%ADD23R,0.07480X0.04528*%
|
||||
%ADD24R,0.04724X0.04843*%
|
||||
%ADD25C,0.03150*%
|
||||
%ADD26C,0.02953*%
|
||||
D10*
|
||||
X0414400Y0057433D03*
|
||||
X0424400Y0057433D03*
|
||||
X0434400Y0057433D03*
|
||||
X0444400Y0057433D03*
|
||||
X0454400Y0057433D03*
|
||||
X0464400Y0057433D03*
|
||||
X0474400Y0057433D03*
|
||||
X0484400Y0057433D03*
|
||||
X0494400Y0057433D03*
|
||||
X0504400Y0057433D03*
|
||||
X0514400Y0057433D03*
|
||||
X0524400Y0057433D03*
|
||||
X0534400Y0057433D03*
|
||||
X0544400Y0057433D03*
|
||||
X0554400Y0057433D03*
|
||||
X0564400Y0057433D03*
|
||||
X0574400Y0057433D03*
|
||||
X0584400Y0057433D03*
|
||||
X0594400Y0057433D03*
|
||||
X0604400Y0057433D03*
|
||||
X0614400Y0057433D03*
|
||||
X0624400Y0057433D03*
|
||||
X0634400Y0057433D03*
|
||||
X0644400Y0057433D03*
|
||||
X0654400Y0057433D03*
|
||||
D11*
|
||||
X0456821Y0317729D03*
|
||||
D12*
|
||||
X0446821Y0317729D03*
|
||||
X0436821Y0317729D03*
|
||||
X0426821Y0317729D03*
|
||||
X0416821Y0317729D03*
|
||||
X0416821Y0307729D03*
|
||||
X0426821Y0307729D03*
|
||||
X0426821Y0297729D03*
|
||||
X0416821Y0297729D03*
|
||||
X0416821Y0287729D03*
|
||||
X0426821Y0287729D03*
|
||||
X0426821Y0277729D03*
|
||||
X0416821Y0277729D03*
|
||||
X0416821Y0267729D03*
|
||||
X0426821Y0267729D03*
|
||||
X0436821Y0267729D03*
|
||||
X0446821Y0267729D03*
|
||||
X0456821Y0267729D03*
|
||||
X0466821Y0267729D03*
|
||||
X0476821Y0267729D03*
|
||||
X0486821Y0267729D03*
|
||||
X0486821Y0277729D03*
|
||||
X0476821Y0277729D03*
|
||||
X0476821Y0287729D03*
|
||||
X0486821Y0287729D03*
|
||||
X0486821Y0297729D03*
|
||||
X0476821Y0297729D03*
|
||||
X0476821Y0307729D03*
|
||||
X0486821Y0307729D03*
|
||||
X0486821Y0317729D03*
|
||||
X0476821Y0317729D03*
|
||||
X0466821Y0317729D03*
|
||||
X0466821Y0327729D03*
|
||||
X0476821Y0327729D03*
|
||||
X0456821Y0327729D03*
|
||||
X0446821Y0327729D03*
|
||||
X0436821Y0327729D03*
|
||||
X0426821Y0327729D03*
|
||||
X0531743Y0331548D03*
|
||||
X0531743Y0321548D03*
|
||||
X0476821Y0257729D03*
|
||||
X0466821Y0257729D03*
|
||||
X0456821Y0257729D03*
|
||||
X0446821Y0257729D03*
|
||||
X0436821Y0257729D03*
|
||||
X0426821Y0257729D03*
|
||||
D13*
|
||||
X0429144Y0219722D02*
|
||||
X0429144Y0214948D01*
|
||||
X0419144Y0214948D02*
|
||||
X0419144Y0219722D01*
|
||||
X0409144Y0219722D02*
|
||||
X0409144Y0214948D01*
|
||||
X0399144Y0214948D02*
|
||||
X0399144Y0219722D01*
|
||||
X0389144Y0219722D02*
|
||||
X0389144Y0214948D01*
|
||||
X0379144Y0214948D02*
|
||||
X0379144Y0219722D01*
|
||||
X0439144Y0219722D02*
|
||||
X0439144Y0214948D01*
|
||||
X0449144Y0214948D02*
|
||||
X0449144Y0219722D01*
|
||||
X0459144Y0219722D02*
|
||||
X0459144Y0214948D01*
|
||||
X0469144Y0214948D02*
|
||||
X0469144Y0219722D01*
|
||||
X0479144Y0219722D02*
|
||||
X0479144Y0214948D01*
|
||||
X0489144Y0214948D02*
|
||||
X0489144Y0219722D01*
|
||||
X0489144Y0159722D02*
|
||||
X0489144Y0154948D01*
|
||||
X0479144Y0154948D02*
|
||||
X0479144Y0159722D01*
|
||||
X0469144Y0159722D02*
|
||||
X0469144Y0154948D01*
|
||||
X0459144Y0154948D02*
|
||||
X0459144Y0159722D01*
|
||||
X0449144Y0159722D02*
|
||||
X0449144Y0154948D01*
|
||||
X0439144Y0154948D02*
|
||||
X0439144Y0159722D01*
|
||||
X0429144Y0159722D02*
|
||||
X0429144Y0154948D01*
|
||||
X0419144Y0154948D02*
|
||||
X0419144Y0159722D01*
|
||||
X0409144Y0159722D02*
|
||||
X0409144Y0154948D01*
|
||||
X0399144Y0154948D02*
|
||||
X0399144Y0159722D01*
|
||||
X0389144Y0159722D02*
|
||||
X0389144Y0154948D01*
|
||||
X0379144Y0154948D02*
|
||||
X0379144Y0159722D01*
|
||||
X0419302Y0127596D02*
|
||||
X0419302Y0122822D01*
|
||||
X0429302Y0122822D02*
|
||||
X0429302Y0127596D01*
|
||||
X0439302Y0127596D02*
|
||||
X0439302Y0122822D01*
|
||||
X0449302Y0122822D02*
|
||||
X0449302Y0127596D01*
|
||||
X0459302Y0127596D02*
|
||||
X0459302Y0122822D01*
|
||||
X0469302Y0122822D02*
|
||||
X0469302Y0127596D01*
|
||||
X0479302Y0127596D02*
|
||||
X0479302Y0122822D01*
|
||||
X0489302Y0122822D02*
|
||||
X0489302Y0127596D01*
|
||||
X0499302Y0127596D02*
|
||||
X0499302Y0122822D01*
|
||||
X0509302Y0122822D02*
|
||||
X0509302Y0127596D01*
|
||||
X0509302Y0097596D02*
|
||||
X0509302Y0092822D01*
|
||||
X0499302Y0092822D02*
|
||||
X0499302Y0097596D01*
|
||||
X0489302Y0097596D02*
|
||||
X0489302Y0092822D01*
|
||||
X0479302Y0092822D02*
|
||||
X0479302Y0097596D01*
|
||||
X0469302Y0097596D02*
|
||||
X0469302Y0092822D01*
|
||||
X0459302Y0092822D02*
|
||||
X0459302Y0097596D01*
|
||||
X0449302Y0097596D02*
|
||||
X0449302Y0092822D01*
|
||||
X0439302Y0092822D02*
|
||||
X0439302Y0097596D01*
|
||||
X0429302Y0097596D02*
|
||||
X0429302Y0092822D01*
|
||||
X0419302Y0092822D02*
|
||||
X0419302Y0097596D01*
|
||||
D14*
|
||||
X0618916Y0112886D02*
|
||||
X0624491Y0112886D01*
|
||||
X0624491Y0122886D02*
|
||||
X0618916Y0122886D01*
|
||||
X0618916Y0132886D02*
|
||||
X0624491Y0132886D01*
|
||||
X0498987Y0230059D02*
|
||||
X0498987Y0235634D01*
|
||||
X0488987Y0235634D02*
|
||||
X0488987Y0230059D01*
|
||||
X0478987Y0230059D02*
|
||||
X0478987Y0235634D01*
|
||||
X0367758Y0282650D02*
|
||||
X0362183Y0282650D01*
|
||||
X0362183Y0292650D02*
|
||||
X0367758Y0292650D01*
|
||||
X0367758Y0302650D02*
|
||||
X0362183Y0302650D01*
|
||||
X0362183Y0312650D02*
|
||||
X0367758Y0312650D01*
|
||||
X0367758Y0322650D02*
|
||||
X0362183Y0322650D01*
|
||||
X0362183Y0332650D02*
|
||||
X0367758Y0332650D01*
|
||||
D15*
|
||||
X0680703Y0122886D03*
|
||||
D16*
|
||||
X0598858Y0122689D03*
|
||||
D17*
|
||||
X0608858Y0122689D03*
|
||||
D18*
|
||||
X0609420Y0149264D03*
|
||||
X0602727Y0149264D03*
|
||||
X0618475Y0149146D03*
|
||||
X0625168Y0149146D03*
|
||||
X0613396Y0096036D03*
|
||||
X0606703Y0096036D03*
|
||||
D19*
|
||||
X0605128Y0180288D03*
|
||||
X0595286Y0180288D03*
|
||||
X0595286Y0186981D03*
|
||||
X0605128Y0186981D03*
|
||||
X0614971Y0186981D03*
|
||||
X0614971Y0180288D03*
|
||||
X0663396Y0180327D03*
|
||||
X0663396Y0187020D03*
|
||||
X0673042Y0186981D03*
|
||||
X0673042Y0180288D03*
|
||||
X0694695Y0251154D03*
|
||||
X0694695Y0257847D03*
|
||||
X0694695Y0264933D03*
|
||||
X0694695Y0271626D03*
|
||||
X0531624Y0304343D03*
|
||||
X0531624Y0311036D03*
|
||||
D20*
|
||||
X0594794Y0199382D03*
|
||||
X0604636Y0199382D03*
|
||||
X0614479Y0199382D03*
|
||||
X0624321Y0199382D03*
|
||||
X0634164Y0199382D03*
|
||||
X0644006Y0199382D03*
|
||||
X0653849Y0199382D03*
|
||||
X0663691Y0199382D03*
|
||||
X0670187Y0199382D03*
|
||||
D21*
|
||||
X0684459Y0294658D03*
|
||||
X0574420Y0294658D03*
|
||||
D22*
|
||||
X0683376Y0243870D03*
|
||||
D23*
|
||||
X0683376Y0278516D03*
|
||||
X0683376Y0283634D03*
|
||||
D24*
|
||||
X0613494Y0104894D03*
|
||||
X0606605Y0104894D03*
|
||||
D25*
|
||||
X0373829Y0166902D03*
|
||||
X0414183Y0174776D03*
|
||||
X0428947Y0174776D03*
|
||||
X0428947Y0132453D03*
|
||||
X0499813Y0135406D03*
|
||||
X0533278Y0125563D03*
|
||||
X0530325Y0095051D03*
|
||||
X0533278Y0090130D03*
|
||||
X0533278Y0079303D03*
|
||||
X0554931Y0092099D03*
|
||||
X0559853Y0092099D03*
|
||||
X0613987Y0089146D03*
|
||||
X0530325Y0157059D03*
|
||||
X0624813Y0193477D03*
|
||||
X0654341Y0193477D03*
|
||||
X0663199Y0230878D03*
|
||||
X0633672Y0237768D03*
|
||||
X0633672Y0247610D03*
|
||||
X0559853Y0227925D03*
|
||||
X0554931Y0231862D03*
|
||||
X0531309Y0240721D03*
|
||||
X0509302Y0232847D03*
|
||||
X0500798Y0240721D03*
|
||||
X0496861Y0243673D03*
|
||||
X0520483Y0261390D03*
|
||||
X0545089Y0279107D03*
|
||||
X0472254Y0262374D03*
|
||||
X0441743Y0262374D03*
|
||||
X0419105Y0262374D03*
|
||||
X0441743Y0242689D03*
|
||||
X0454538Y0224973D03*
|
||||
X0440758Y0293870D03*
|
||||
X0451585Y0301744D03*
|
||||
X0447648Y0306666D03*
|
||||
X0379735Y0297807D03*
|
||||
D26*
|
||||
X0517530Y0249579D03*
|
||||
X0546073Y0240721D03*
|
||||
X0548042Y0243673D03*
|
||||
X0551979Y0237768D03*
|
||||
X0547057Y0234815D03*
|
||||
X0404341Y0117689D03*
|
||||
X0394498Y0114736D03*
|
||||
X0384656Y0111784D03*
|
||||
X0517530Y0091114D03*
|
||||
X0520483Y0083240D03*
|
||||
X0634656Y0074382D03*
|
||||
X0644498Y0074382D03*
|
||||
M02*
|
||||
|
|
@ -1,287 +0,0 @@
|
|||
G75*
|
||||
%MOIN*%
|
||||
%OFA0B0*%
|
||||
%FSLAX25Y25*%
|
||||
%IPPOS*%
|
||||
%LPD*%
|
||||
%AMOC8*
|
||||
5,1,8,0,0,1.08239X$1,22.5*
|
||||
%
|
||||
%ADD10R,0.06591X0.26091*%
|
||||
%ADD11C,0.05365*%
|
||||
%ADD12OC8,0.05365*%
|
||||
%ADD13C,0.05365*%
|
||||
%ADD14C,0.06165*%
|
||||
%ADD15C,0.13591*%
|
||||
%ADD16OC8,0.06891*%
|
||||
%ADD17C,0.06891*%
|
||||
%ADD18C,0.08465*%
|
||||
%ADD19R,0.04724X0.04843*%
|
||||
%ADD20R,0.04843X0.04724*%
|
||||
%ADD21C,0.03150*%
|
||||
%ADD22C,0.02953*%
|
||||
D10*
|
||||
X0414400Y0057433D03*
|
||||
X0424400Y0057433D03*
|
||||
X0434400Y0057433D03*
|
||||
X0444400Y0057433D03*
|
||||
X0454400Y0057433D03*
|
||||
X0464400Y0057433D03*
|
||||
X0474400Y0057433D03*
|
||||
X0484400Y0057433D03*
|
||||
X0494400Y0057433D03*
|
||||
X0504400Y0057433D03*
|
||||
X0514400Y0057433D03*
|
||||
X0524400Y0057433D03*
|
||||
X0534400Y0057433D03*
|
||||
X0544400Y0057433D03*
|
||||
X0554400Y0057433D03*
|
||||
X0564400Y0057433D03*
|
||||
X0574400Y0057433D03*
|
||||
X0584400Y0057433D03*
|
||||
X0594400Y0057433D03*
|
||||
X0604400Y0057433D03*
|
||||
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|
||||
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|
||||
X0634400Y0057433D03*
|
||||
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|
||||
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|
||||
D11*
|
||||
X0456821Y0317729D03*
|
||||
D12*
|
||||
X0446821Y0317729D03*
|
||||
X0436821Y0317729D03*
|
||||
X0426821Y0317729D03*
|
||||
X0416821Y0317729D03*
|
||||
X0416821Y0307729D03*
|
||||
X0426821Y0307729D03*
|
||||
X0426821Y0297729D03*
|
||||
X0416821Y0297729D03*
|
||||
X0416821Y0287729D03*
|
||||
X0426821Y0287729D03*
|
||||
X0426821Y0277729D03*
|
||||
X0416821Y0277729D03*
|
||||
X0416821Y0267729D03*
|
||||
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|
||||
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|
||||
X0446821Y0267729D03*
|
||||
X0456821Y0267729D03*
|
||||
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|
||||
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|
||||
X0486821Y0267729D03*
|
||||
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|
||||
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|
||||
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|
||||
X0486821Y0287729D03*
|
||||
X0486821Y0297729D03*
|
||||
X0476821Y0297729D03*
|
||||
X0476821Y0307729D03*
|
||||
X0486821Y0307729D03*
|
||||
X0486821Y0317729D03*
|
||||
X0476821Y0317729D03*
|
||||
X0466821Y0317729D03*
|
||||
X0466821Y0327729D03*
|
||||
X0476821Y0327729D03*
|
||||
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|
||||
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|
||||
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|
||||
X0426821Y0327729D03*
|
||||
X0531743Y0331548D03*
|
||||
X0531743Y0321548D03*
|
||||
X0476821Y0257729D03*
|
||||
X0466821Y0257729D03*
|
||||
X0456821Y0257729D03*
|
||||
X0446821Y0257729D03*
|
||||
X0436821Y0257729D03*
|
||||
X0426821Y0257729D03*
|
||||
D13*
|
||||
X0429144Y0219722D02*
|
||||
X0429144Y0214948D01*
|
||||
X0419144Y0214948D02*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X0399144Y0219722D01*
|
||||
X0389144Y0219722D02*
|
||||
X0389144Y0214948D01*
|
||||
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|
||||
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|
||||
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|
||||
X0439144Y0214948D01*
|
||||
X0449144Y0214948D02*
|
||||
X0449144Y0219722D01*
|
||||
X0459144Y0219722D02*
|
||||
X0459144Y0214948D01*
|
||||
X0469144Y0214948D02*
|
||||
X0469144Y0219722D01*
|
||||
X0479144Y0219722D02*
|
||||
X0479144Y0214948D01*
|
||||
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|
||||
X0489144Y0219722D01*
|
||||
X0489144Y0159722D02*
|
||||
X0489144Y0154948D01*
|
||||
X0479144Y0154948D02*
|
||||
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|
||||
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|
||||
X0469144Y0154948D01*
|
||||
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|
||||
X0459144Y0159722D01*
|
||||
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|
||||
X0449144Y0154948D01*
|
||||
X0439144Y0154948D02*
|
||||
X0439144Y0159722D01*
|
||||
X0429144Y0159722D02*
|
||||
X0429144Y0154948D01*
|
||||
X0419144Y0154948D02*
|
||||
X0419144Y0159722D01*
|
||||
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|
||||
X0409144Y0154948D01*
|
||||
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|
||||
X0399144Y0159722D01*
|
||||
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|
||||
X0389144Y0154948D01*
|
||||
X0379144Y0154948D02*
|
||||
X0379144Y0159722D01*
|
||||
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|
||||
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|
||||
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|
||||
X0429302Y0127596D01*
|
||||
X0439302Y0127596D02*
|
||||
X0439302Y0122822D01*
|
||||
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|
||||
X0449302Y0127596D01*
|
||||
X0459302Y0127596D02*
|
||||
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|
||||
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|
||||
X0469302Y0127596D01*
|
||||
X0479302Y0127596D02*
|
||||
X0479302Y0122822D01*
|
||||
X0489302Y0122822D02*
|
||||
X0489302Y0127596D01*
|
||||
X0499302Y0127596D02*
|
||||
X0499302Y0122822D01*
|
||||
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|
||||
X0509302Y0127596D01*
|
||||
X0509302Y0097596D02*
|
||||
X0509302Y0092822D01*
|
||||
X0499302Y0092822D02*
|
||||
X0499302Y0097596D01*
|
||||
X0489302Y0097596D02*
|
||||
X0489302Y0092822D01*
|
||||
X0479302Y0092822D02*
|
||||
X0479302Y0097596D01*
|
||||
X0469302Y0097596D02*
|
||||
X0469302Y0092822D01*
|
||||
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|
||||
X0459302Y0097596D01*
|
||||
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|
||||
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|
||||
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|
||||
X0439302Y0097596D01*
|
||||
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|
||||
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|
||||
X0419302Y0092822D02*
|
||||
X0419302Y0097596D01*
|
||||
D14*
|
||||
X0618916Y0112886D02*
|
||||
X0624491Y0112886D01*
|
||||
X0624491Y0122886D02*
|
||||
X0618916Y0122886D01*
|
||||
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|
||||
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|
||||
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|
||||
X0498987Y0235634D01*
|
||||
X0488987Y0235634D02*
|
||||
X0488987Y0230059D01*
|
||||
X0478987Y0230059D02*
|
||||
X0478987Y0235634D01*
|
||||
X0367758Y0282650D02*
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
X0362183Y0302650D01*
|
||||
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|
||||
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|
||||
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|
||||
X0362183Y0322650D01*
|
||||
X0362183Y0332650D02*
|
||||
X0367758Y0332650D01*
|
||||
D15*
|
||||
X0680703Y0122886D03*
|
||||
D16*
|
||||
X0598858Y0122689D03*
|
||||
D17*
|
||||
X0608858Y0122689D03*
|
||||
D18*
|
||||
X0574420Y0294658D03*
|
||||
X0684459Y0294658D03*
|
||||
D19*
|
||||
X0490463Y0325366D03*
|
||||
X0483573Y0325366D03*
|
||||
X0483573Y0331272D03*
|
||||
X0490463Y0331272D03*
|
||||
D20*
|
||||
X0460443Y0306173D03*
|
||||
X0460443Y0299284D03*
|
||||
X0467333Y0299284D03*
|
||||
X0467333Y0292394D03*
|
||||
X0431900Y0249087D03*
|
||||
X0425994Y0249087D03*
|
||||
X0425994Y0242197D03*
|
||||
X0431900Y0242197D03*
|
||||
X0500798Y0169362D03*
|
||||
X0500798Y0162473D03*
|
||||
X0519498Y0107355D03*
|
||||
X0519498Y0100465D03*
|
||||
D21*
|
||||
X0373829Y0166902D03*
|
||||
X0414183Y0174776D03*
|
||||
X0428947Y0174776D03*
|
||||
X0428947Y0132453D03*
|
||||
X0499813Y0135406D03*
|
||||
X0533278Y0125563D03*
|
||||
X0530325Y0095051D03*
|
||||
X0533278Y0090130D03*
|
||||
X0533278Y0079303D03*
|
||||
X0554931Y0092099D03*
|
||||
X0559853Y0092099D03*
|
||||
X0613987Y0089146D03*
|
||||
X0530325Y0157059D03*
|
||||
X0624813Y0193477D03*
|
||||
X0654341Y0193477D03*
|
||||
X0663199Y0230878D03*
|
||||
X0633672Y0237768D03*
|
||||
X0633672Y0247610D03*
|
||||
X0559853Y0227925D03*
|
||||
X0554931Y0231862D03*
|
||||
X0531309Y0240721D03*
|
||||
X0509302Y0232847D03*
|
||||
X0500798Y0240721D03*
|
||||
X0496861Y0243673D03*
|
||||
X0520483Y0261390D03*
|
||||
X0545089Y0279107D03*
|
||||
X0472254Y0262374D03*
|
||||
X0441743Y0262374D03*
|
||||
X0419105Y0262374D03*
|
||||
X0441743Y0242689D03*
|
||||
X0454538Y0224973D03*
|
||||
X0440758Y0293870D03*
|
||||
X0451585Y0301744D03*
|
||||
X0447648Y0306666D03*
|
||||
X0379735Y0297807D03*
|
||||
D22*
|
||||
X0517530Y0249579D03*
|
||||
X0546073Y0240721D03*
|
||||
X0548042Y0243673D03*
|
||||
X0551979Y0237768D03*
|
||||
X0547057Y0234815D03*
|
||||
X0404341Y0117689D03*
|
||||
X0394498Y0114736D03*
|
||||
X0384656Y0111784D03*
|
||||
X0517530Y0091114D03*
|
||||
X0520483Y0083240D03*
|
||||
X0634656Y0074382D03*
|
||||
X0644498Y0074382D03*
|
||||
M02*
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,280 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.1">
|
||||
<drawing>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
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||||
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
</symbol>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="TC2050-IDC" prefix="TC">
|
||||
<description>Tag-Connect In Circuit Programming & Debug Cable 10 Pin
|
||||
http://www.tag-connect.com</description>
|
||||
<gates>
|
||||
<gate name="A" symbol="TC2050-IDC" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="TC2050-IDC">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="10" pad="10"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
<connect gate="A" pin="7" pad="7"/>
|
||||
<connect gate="A" pin="8" pad="8"/>
|
||||
<connect gate="A" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="-NL" package="TC2050-IDC-NL">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="10" pad="10"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
<connect gate="A" pin="7" pad="7"/>
|
||||
<connect gate="A" pin="8" pad="8"/>
|
||||
<connect gate="A" pin="9" pad="9"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
<deviceset name="TC2030-IDC" prefix="TC">
|
||||
<description>Tag-Connect In Circuit Programming & Debug Cable 6 Pin
|
||||
http://www.tag-connect.com</description>
|
||||
<gates>
|
||||
<gate name="A" symbol="TC2030-IDC" x="0" y="0"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="" package="TC2030-IDC">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="-NL" package="TC2030-IDC-NL">
|
||||
<connects>
|
||||
<connect gate="A" pin="1" pad="1"/>
|
||||
<connect gate="A" pin="2" pad="2"/>
|
||||
<connect gate="A" pin="3" pad="3"/>
|
||||
<connect gate="A" pin="4" pad="4"/>
|
||||
<connect gate="A" pin="5" pad="5"/>
|
||||
<connect gate="A" pin="6" pad="6"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
</eagle>
|
||||
|
|
@ -1,12 +1,12 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="8.2.2">
|
||||
<eagle version="7.2.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<grid distance="25" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
|
|
@ -161,56 +161,56 @@ Dimensions taken from Tech Note #28</description>
|
|||
<wire x1="-25.4" y1="2.54" x2="-25.4" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-105.41" y1="-3.81" x2="-16.51" y2="-3.81" width="1.016" layer="33"/>
|
||||
<wire x1="-0.127" y1="77.597" x2="-0.127" y2="7.778" width="0.2032" layer="49"/>
|
||||
<smd name="26" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="27" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="28" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="29" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="30" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="31" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="32" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="33" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="34" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="35" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="36" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="37" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="38" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="39" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="40" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="41" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="42" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="43" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="44" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="45" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="46" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="47" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="48" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="49" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="50" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="16" cream="no"/>
|
||||
<smd name="25" x="-12.065" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="24" x="-14.605" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="23" x="-17.145" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="22" x="-19.685" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="21" x="-22.225" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="20" x="-24.765" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="19" x="-27.305" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="18" x="-29.845" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="17" x="-32.385" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="16" x="-34.925" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="15" x="-37.465" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="14" x="-40.005" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="13" x="-42.545" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="12" x="-45.085" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="11" x="-47.625" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="10" x="-50.165" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="09" x="-52.705" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="08" x="-55.245" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="07" x="-57.785" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="06" x="-60.325" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="05" x="-62.865" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="04" x="-65.405" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="03" x="-67.945" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="02" x="-70.485" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="01" x="-73.025" y="4.445" dx="1.524" dy="6.477" layer="1" cream="no"/>
|
||||
<smd name="26" x="-12.065" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="27" x="-14.605" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="28" x="-17.145" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="29" x="-19.685" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="30" x="-22.225" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="31" x="-24.765" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="32" x="-27.305" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="33" x="-29.845" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="34" x="-32.385" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="35" x="-34.925" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="36" x="-37.465" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="37" x="-40.005" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="38" x="-42.545" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="39" x="-45.085" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="40" x="-47.625" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="41" x="-50.165" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="42" x="-52.705" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="43" x="-55.245" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="44" x="-57.785" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="45" x="-60.325" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="46" x="-62.865" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="47" x="-65.405" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="48" x="-67.945" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="49" x="-70.485" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="50" x="-73.025" y="4.064" dx="1.524" dy="7.239" layer="16" cream="no"/>
|
||||
<smd name="25" x="-12.065" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="24" x="-14.605" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="23" x="-17.145" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="22" x="-19.685" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="21" x="-22.225" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="20" x="-24.765" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="19" x="-27.305" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="18" x="-29.845" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="17" x="-32.385" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="16" x="-34.925" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="15" x="-37.465" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="14" x="-40.005" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="13" x="-42.545" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="12" x="-45.085" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="11" x="-47.625" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="10" x="-50.165" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="09" x="-52.705" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="08" x="-55.245" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="07" x="-57.785" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="06" x="-60.325" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="05" x="-62.865" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="04" x="-65.405" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="03" x="-67.945" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="02" x="-70.485" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<smd name="01" x="-73.025" y="4.064" dx="1.524" dy="7.239" layer="1" cream="no"/>
|
||||
<text x="-5.715" y="3.175" size="1.778" layer="25">>NAME</text>
|
||||
<text x="-94.5134" y="2.9718" size="1.778" layer="48">7,87 mm</text>
|
||||
<text x="-40.8432" y="-9.2964" size="1.778" layer="48">74.93 mm
|
||||
|
|
@ -478,7 +478,7 @@ Dimensions taken from Tech Note #28</description>
|
|||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="A2-50PIN" prefix="ST" uservalue="yes">
|
||||
<deviceset name="A2-50PIN">
|
||||
<description><B>Apple ][ Peripheral Card Connector</B>
|
||||
<br />
|
||||
This is the, default, 50-pin connector for slot #1 to #7
|
||||
|
|
@ -494,23 +494,23 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<gate name="_D5" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
|
||||
<gate name="_D6" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
|
||||
<gate name="_D7" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
|
||||
<gate name="_DEVSELECT\" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
|
||||
<gate name="_00" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
|
||||
<gate name="_!DEVSELECT" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
|
||||
<gate name="_PHI0" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
|
||||
<gate name="_USER1" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
|
||||
<gate name="_01" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
|
||||
<gate name="_PHI1" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
|
||||
<gate name="_Q3" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
|
||||
<gate name="_7M" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
|
||||
<gate name="_NC@2" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
|
||||
<gate name="_-5V" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
|
||||
<gate name="_-12V" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
|
||||
<gate name="_INH\" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
|
||||
<gate name="_RES\" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
|
||||
<gate name="_IRQ\" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
|
||||
<gate name="_NMI\" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
|
||||
<gate name="_!INH" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
|
||||
<gate name="_!RES" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
|
||||
<gate name="_!IRQ" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
|
||||
<gate name="_!NMI" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
|
||||
<gate name="_INT_IN" symbol="ATPIN" x="-5.08" y="17.78" addlevel="always"/>
|
||||
<gate name="_DMA_IN" symbol="ATPIN" x="-5.08" y="20.32" addlevel="always"/>
|
||||
<gate name="_GND" symbol="ATPIN" x="-5.08" y="22.86" addlevel="always"/>
|
||||
<gate name="_IOSELECT\" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
|
||||
<gate name="_!IOSELECT" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
|
||||
<gate name="_A00" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
|
||||
<gate name="_A01" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
|
||||
<gate name="_A02" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
|
||||
|
|
@ -527,11 +527,11 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<gate name="_A13" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
|
||||
<gate name="_A14" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
|
||||
<gate name="_A15" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
|
||||
<gate name="_RW" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
|
||||
<gate name="_R!W" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
|
||||
<gate name="_NC@1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
|
||||
<gate name="_IOSTR\" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
|
||||
<gate name="_!IOSTR" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
|
||||
<gate name="_RDY" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
|
||||
<gate name="_DMA\" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
|
||||
<gate name="_!DMA" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
|
||||
<gate name="_INT_OUT" symbol="ATPIN" x="27.94" y="17.78" addlevel="always"/>
|
||||
<gate name="_DMA_OUT" symbol="ATPIN" x="27.94" y="20.32" addlevel="always"/>
|
||||
<gate name="_+5V" symbol="ATPIN" x="27.94" y="22.86" addlevel="always"/>
|
||||
|
|
@ -539,12 +539,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<devices>
|
||||
<device name="SLOT1-3" package="A2-50PIN-SL1-3">
|
||||
<connects>
|
||||
<connect gate="_!DEVSELECT" pin="P" pad="41"/>
|
||||
<connect gate="_!DMA" pin="P" pad="22"/>
|
||||
<connect gate="_!INH" pin="P" pad="32"/>
|
||||
<connect gate="_!IOSELECT" pin="P" pad="01"/>
|
||||
<connect gate="_!IOSTR" pin="P" pad="20"/>
|
||||
<connect gate="_!IRQ" pin="P" pad="30"/>
|
||||
<connect gate="_!NMI" pin="P" pad="29"/>
|
||||
<connect gate="_!RES" pin="P" pad="31"/>
|
||||
<connect gate="_+12V" pin="P" pad="50"/>
|
||||
<connect gate="_+5V" pin="P" pad="25"/>
|
||||
<connect gate="_-12V" pin="P" pad="33"/>
|
||||
<connect gate="_-5V" pin="P" pad="34"/>
|
||||
<connect gate="_00" pin="P" pad="40"/>
|
||||
<connect gate="_01" pin="P" pad="38"/>
|
||||
<connect gate="_7M" pin="P" pad="36"/>
|
||||
<connect gate="_A00" pin="P" pad="02"/>
|
||||
<connect gate="_A01" pin="P" pad="03"/>
|
||||
|
|
@ -570,24 +576,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<connect gate="_D5" pin="P" pad="44"/>
|
||||
<connect gate="_D6" pin="P" pad="43"/>
|
||||
<connect gate="_D7" pin="P" pad="42"/>
|
||||
<connect gate="_DEVSELECT\" pin="P" pad="41"/>
|
||||
<connect gate="_DMA\" pin="P" pad="22"/>
|
||||
<connect gate="_DMA_IN" pin="P" pad="27"/>
|
||||
<connect gate="_DMA_OUT" pin="P" pad="24"/>
|
||||
<connect gate="_GND" pin="P" pad="26"/>
|
||||
<connect gate="_INH\" pin="P" pad="32"/>
|
||||
<connect gate="_INT_IN" pin="P" pad="28"/>
|
||||
<connect gate="_INT_OUT" pin="P" pad="23"/>
|
||||
<connect gate="_IOSELECT\" pin="P" pad="01"/>
|
||||
<connect gate="_IOSTR\" pin="P" pad="20"/>
|
||||
<connect gate="_IRQ\" pin="P" pad="30"/>
|
||||
<connect gate="_NC@1" pin="P" pad="19"/>
|
||||
<connect gate="_NC@2" pin="P" pad="35"/>
|
||||
<connect gate="_NMI\" pin="P" pad="29"/>
|
||||
<connect gate="_PHI0" pin="P" pad="40"/>
|
||||
<connect gate="_PHI1" pin="P" pad="38"/>
|
||||
<connect gate="_Q3" pin="P" pad="37"/>
|
||||
<connect gate="_R!W" pin="P" pad="18"/>
|
||||
<connect gate="_RDY" pin="P" pad="21"/>
|
||||
<connect gate="_RES\" pin="P" pad="31"/>
|
||||
<connect gate="_RW" pin="P" pad="18"/>
|
||||
<connect gate="_USER1" pin="P" pad="39"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
|
|
@ -596,12 +596,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
</device>
|
||||
<device name="SLOT4-7" package="A2-50PIN-SL4-7">
|
||||
<connects>
|
||||
<connect gate="_!DEVSELECT" pin="P" pad="41"/>
|
||||
<connect gate="_!DMA" pin="P" pad="22"/>
|
||||
<connect gate="_!INH" pin="P" pad="32"/>
|
||||
<connect gate="_!IOSELECT" pin="P" pad="01"/>
|
||||
<connect gate="_!IOSTR" pin="P" pad="20"/>
|
||||
<connect gate="_!IRQ" pin="P" pad="30"/>
|
||||
<connect gate="_!NMI" pin="P" pad="29"/>
|
||||
<connect gate="_!RES" pin="P" pad="31"/>
|
||||
<connect gate="_+12V" pin="P" pad="50"/>
|
||||
<connect gate="_+5V" pin="P" pad="25"/>
|
||||
<connect gate="_-12V" pin="P" pad="33"/>
|
||||
<connect gate="_-5V" pin="P" pad="34"/>
|
||||
<connect gate="_00" pin="P" pad="40"/>
|
||||
<connect gate="_01" pin="P" pad="38"/>
|
||||
<connect gate="_7M" pin="P" pad="36"/>
|
||||
<connect gate="_A00" pin="P" pad="02"/>
|
||||
<connect gate="_A01" pin="P" pad="03"/>
|
||||
|
|
@ -627,24 +633,18 @@ Pins are laid out as seen from the top of the slot</description>
|
|||
<connect gate="_D5" pin="P" pad="44"/>
|
||||
<connect gate="_D6" pin="P" pad="43"/>
|
||||
<connect gate="_D7" pin="P" pad="42"/>
|
||||
<connect gate="_DEVSELECT\" pin="P" pad="41"/>
|
||||
<connect gate="_DMA\" pin="P" pad="22"/>
|
||||
<connect gate="_DMA_IN" pin="P" pad="27"/>
|
||||
<connect gate="_DMA_OUT" pin="P" pad="24"/>
|
||||
<connect gate="_GND" pin="P" pad="26"/>
|
||||
<connect gate="_INH\" pin="P" pad="32"/>
|
||||
<connect gate="_INT_IN" pin="P" pad="28"/>
|
||||
<connect gate="_INT_OUT" pin="P" pad="23"/>
|
||||
<connect gate="_IOSELECT\" pin="P" pad="01"/>
|
||||
<connect gate="_IOSTR\" pin="P" pad="20"/>
|
||||
<connect gate="_IRQ\" pin="P" pad="30"/>
|
||||
<connect gate="_NC@1" pin="P" pad="19"/>
|
||||
<connect gate="_NC@2" pin="P" pad="35"/>
|
||||
<connect gate="_NMI\" pin="P" pad="29"/>
|
||||
<connect gate="_PHI0" pin="P" pad="40"/>
|
||||
<connect gate="_PHI1" pin="P" pad="38"/>
|
||||
<connect gate="_Q3" pin="P" pad="37"/>
|
||||
<connect gate="_R!W" pin="P" pad="18"/>
|
||||
<connect gate="_RDY" pin="P" pad="21"/>
|
||||
<connect gate="_RES\" pin="P" pad="31"/>
|
||||
<connect gate="_RW" pin="P" pad="18"/>
|
||||
<connect gate="_USER1" pin="P" pad="39"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -0,0 +1,688 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="8.2.2">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
<setting verticaltext="up"/>
|
||||
</settings>
|
||||
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
|
||||
<layers>
|
||||
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
|
||||
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
|
||||
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
|
||||
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
|
||||
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
|
||||
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
|
||||
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
|
||||
<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
|
||||
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
|
||||
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="50" name="dxf" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="53" name="tGND_GNDA" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="54" name="bGND_GNDA" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="56" name="wert" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="100" name="Release" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="101" name="Heatsink" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="102" name="tMarkings" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="103" name="bMarkings" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="104" name="Name" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="105" name="Beschreib" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="106" name="BGA-Top" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="107" name="BD-Top" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="116" name="Patch_BOT" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="121" name="_layer121" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="122" name="_bplace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="150" name="References" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="200" name="200bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="201" name="201bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="202" name="202bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="203" name="203bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="204" name="204bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="205" name="205bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="206" name="206bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="207" name="207bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="208" name="208bmp" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="231" name="Eagle3D_PG1" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="232" name="Eagle3D_PG2" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="233" name="Eagle3D_PG3" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="250" name="Descript" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="251" name="SMDround" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="254" name="OrgLBR" color="7" fill="1" visible="yes" active="yes"/>
|
||||
</layers>
|
||||
<library>
|
||||
<packages>
|
||||
<package name="S44">
|
||||
<description><b>PLCC SOCKET</b></description>
|
||||
<circle x="-2.54" y="2.54" radius="1.27" width="0.1524" layer="21"/>
|
||||
<circle x="2.54" y="2.54" radius="1.27" width="0.1524" layer="21"/>
|
||||
<circle x="-2.54" y="-2.54" radius="1.27" width="0.1524" layer="21"/>
|
||||
<circle x="2.54" y="-2.54" radius="1.27" width="0.1524" layer="21"/>
|
||||
<wire x1="-10.16" y1="11.684" x2="-11.684" y2="10.16" width="0.1524" layer="21"/>
|
||||
<wire x1="-11.684" y1="10.16" x2="-11.684" y2="-11.049" width="0.1524" layer="21"/>
|
||||
<wire x1="-8.255" y1="6.985" x2="-6.985" y2="8.255" width="0.1524" layer="21"/>
|
||||
<wire x1="-9.398" y1="-10.414" x2="-7.239" y2="-8.255" width="0.1524" layer="21"/>
|
||||
<wire x1="-9.398" y1="-10.414" x2="-10.414" y2="-9.398" width="0.1524" layer="21"/>
|
||||
<wire x1="-10.414" y1="-9.398" x2="-8.255" y2="-7.239" width="0.1524" layer="21"/>
|
||||
<wire x1="-8.255" y1="-7.239" x2="-8.255" y2="-6.985" width="0.1524" layer="21"/>
|
||||
<wire x1="-7.239" y1="-8.255" x2="-6.985" y2="-8.255" width="0.1524" layer="21"/>
|
||||
<wire x1="-5.461" y1="-9.398" x2="-5.461" y2="-8.255" width="0.1524" layer="51"/>
|
||||
<wire x1="-5.461" y1="-9.398" x2="-5.461" y2="-10.414" width="0.1524" layer="21"/>
|
||||
<wire x1="-5.461" y1="-10.414" x2="-4.699" y2="-10.414" width="0.1524" layer="21"/>
|
||||
<wire x1="-4.699" y1="-10.414" x2="-4.699" y2="-9.398" width="0.1524" layer="21"/>
|
||||
<wire x1="-4.699" y1="-8.255" x2="-4.699" y2="-9.398" width="0.1524" layer="51"/>
|
||||
<wire x1="-4.699" y1="-8.255" x2="-4.191" y2="-8.255" width="0.1524" layer="51"/>
|
||||
<wire x1="-3.429" y1="-8.255" x2="-2.921" y2="-8.255" width="0.1524" layer="51"/>
|
||||
<wire x1="-2.921" y1="-9.525" x2="-2.921" y2="-8.255" width="0.1524" layer="51"/>
|
||||
<wire x1="-2.921" y1="-9.525" x2="-2.921" y2="-10.414" width="0.1524" layer="21"/>
|
||||
<wire x1="-2.921" y1="-10.414" x2="-2.159" y2="-10.414" width="0.1524" layer="21"/>
|
||||
<wire x1="-2.159" y1="-10.414" x2="-2.159" y2="-9.525" width="0.1524" layer="21"/>
|
||||
<wire x1="-2.159" y1="-8.255" x2="-2.159" y2="-9.525" width="0.1524" layer="51"/>
|
||||
<wire x1="-2.159" y1="-8.255" x2="-1.651" y2="-8.255" width="0.1524" layer="51"/>
|
||||
<wire x1="-0.889" y1="-8.255" x2="-0.381" y2="-8.255" width="0.1524" layer="51"/>
|
||||
<wire x1="-0.381" y1="-9.525" x2="-0.381" y2="-8.255" width="0.1524" layer="51"/>
|
||||
<wire x1="-0.381" y1="-9.525" x2="-0.381" y2="-10.414" width="0.1524" layer="21"/>
|
||||
<wire x1="-0.381" y1="-10.414" x2="0.381" y2="-10.414" width="0.1524" layer="21"/>
|
||||
<wire x1="0.381" y1="-10.414" x2="0.381" y2="-9.525" width="0.1524" layer="21"/>
|
||||
<wire x1="0.381" y1="-8.255" x2="0.381" y2="-9.525" width="0.1524" layer="51"/>
|
||||
<wire x1="0.381" y1="-8.255" x2="0.889" y2="-8.255" width="0.1524" layer="51"/>
|
||||
<wire x1="10.414" y1="9.398" x2="8.255" y2="7.239" width="0.1524" layer="21"/>
|
||||
<wire x1="10.414" y1="9.398" x2="9.398" y2="10.414" width="0.1524" layer="21"/>
|
||||
<wire x1="9.398" y1="10.414" x2="7.239" y2="8.255" width="0.1524" layer="21"/>
|
||||
<wire x1="8.255" y1="7.239" x2="8.255" y2="6.985" width="0.1524" layer="21"/>
|
||||
<wire x1="8.255" y1="5.969" x2="8.255" y2="5.461" width="0.1524" layer="51"/>
|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<pad name="25" x="1.27" y="-6.35" drill="0.8128" shape="octagon"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<pad name="40" x="6.35" y="8.89" drill="0.8128" shape="octagon"/>
|
||||
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|
||||
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|
||||
<pad name="43" x="3.81" y="6.35" drill="0.8128" shape="octagon"/>
|
||||
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|
||||
<text x="-2.54" y="11.938" size="1.27" layer="27" ratio="10">>VALUE</text>
|
||||
<text x="-10.16" y="11.938" size="1.27" layer="25" ratio="10">>NAME</text>
|
||||
<text x="8.255" y="-10.795" size="1.27" layer="21" ratio="10">44</text>
|
||||
</package>
|
||||
<package name="SQFP-S-10X10-44">
|
||||
<description><b>QFP44</b><p>
|
||||
shrink quad flat pack, square</description>
|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<smd name="16" x="6" y="-0.8" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="17" x="6" y="0" dx="1.8" dy="0.5" layer="1"/>
|
||||
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|
||||
<smd name="19" x="6" y="1.6" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="20" x="6" y="2.4" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="21" x="6" y="3.2" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="22" x="6" y="4" dx="1.8" dy="0.5" layer="1"/>
|
||||
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|
||||
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|
||||
<smd name="25" x="2.4" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
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|
||||
<smd name="27" x="0.8" y="6" dx="0.5" dy="1.8" layer="1"/>
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||||
<smd name="28" x="0" y="6" dx="0.5" dy="1.8" layer="1"/>
|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
<smd name="42" x="-6" y="-2.4" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="43" x="-6" y="-3.2" dx="1.8" dy="0.5" layer="1"/>
|
||||
<smd name="44" x="-6" y="-4" dx="1.8" dy="0.5" layer="1"/>
|
||||
<text x="-3.81" y="-2.175" size="1.27" layer="25">>NAME</text>
|
||||
<text x="-3.81" y="1.905" size="1.27" layer="27">>VALUE</text>
|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<rectangle x1="4.95" y1="-3.4201" x2="6.7201" y2="-2.9799" layer="51"/>
|
||||
<rectangle x1="4.95" y1="-2.62" x2="6.7201" y2="-2.1801" layer="51"/>
|
||||
<rectangle x1="4.95" y1="-1.8199" x2="6.7201" y2="-1.38" layer="51"/>
|
||||
<rectangle x1="4.95" y1="-1.0201" x2="6.7201" y2="-0.5799" layer="51"/>
|
||||
<rectangle x1="4.95" y1="-0.22" x2="6.7201" y2="0.22" layer="51"/>
|
||||
<rectangle x1="4.95" y1="0.5799" x2="6.7201" y2="1.0201" layer="51"/>
|
||||
<rectangle x1="4.95" y1="1.38" x2="6.7201" y2="1.8199" layer="51"/>
|
||||
<rectangle x1="4.95" y1="2.1801" x2="6.7201" y2="2.62" layer="51"/>
|
||||
<rectangle x1="4.95" y1="2.9799" x2="6.7201" y2="3.4201" layer="51"/>
|
||||
<rectangle x1="4.95" y1="3.78" x2="6.7201" y2="4.22" layer="51"/>
|
||||
<rectangle x1="3.78" y1="4.95" x2="4.22" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="2.9799" y1="4.95" x2="3.4201" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="2.1801" y1="4.95" x2="2.62" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="1.38" y1="4.95" x2="1.8199" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="0.5799" y1="4.95" x2="1.0201" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="-0.22" y1="4.95" x2="0.22" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="-1.0201" y1="4.95" x2="-0.5799" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="-1.8199" y1="4.95" x2="-1.38" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="-2.62" y1="4.95" x2="-2.1801" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="-3.4201" y1="4.95" x2="-2.9799" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="-4.22" y1="4.95" x2="-3.78" y2="6.7201" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="3.78" x2="-4.95" y2="4.22" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="2.9799" x2="-4.95" y2="3.4201" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="2.1801" x2="-4.95" y2="2.62" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="1.38" x2="-4.95" y2="1.8199" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="0.5799" x2="-4.95" y2="1.0201" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-0.22" x2="-4.95" y2="0.22" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-1.0201" x2="-4.95" y2="-0.5799" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-1.8199" x2="-4.95" y2="-1.38" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-2.62" x2="-4.95" y2="-2.1801" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-3.4201" x2="-4.95" y2="-2.9799" layer="51"/>
|
||||
<rectangle x1="-6.7201" y1="-4.22" x2="-4.95" y2="-3.78" layer="51"/>
|
||||
</package>
|
||||
</packages>
|
||||
<symbols>
|
||||
<symbol name="SUPPLY">
|
||||
<pin name="GND@0" x="-5.08" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
|
||||
<pin name="GND@1" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
|
||||
<pin name="GND@2" x="5.08" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
|
||||
<pin name="VCCINT@0" x="-5.08" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
|
||||
<pin name="VCCINT@1" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
|
||||
<pin name="VCCIO" x="5.08" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
|
||||
<text x="-0.635" y="-0.635" size="1.778" layer="95">>NAME</text>
|
||||
<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
|
||||
<text x="1.905" y="2.54" size="1.27" layer="95" rot="R90">VCCINT</text>
|
||||
<text x="-3.175" y="2.54" size="1.27" layer="95" rot="R90">VCCINT</text>
|
||||
<text x="6.985" y="2.54" size="1.27" layer="95" rot="R90">VCCIO</text>
|
||||
<text x="-3.175" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
|
||||
<text x="6.985" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
|
||||
</symbol>
|
||||
<symbol name="XC9572_PC44">
|
||||
<wire x1="-25.4" y1="-25.4" x2="25.4" y2="-25.4" width="0.254" layer="94"/>
|
||||
<wire x1="25.4" y1="-25.4" x2="25.4" y2="25.4" width="0.254" layer="94"/>
|
||||
<wire x1="25.4" y1="25.4" x2="-25.4" y2="25.4" width="0.254" layer="94"/>
|
||||
<wire x1="-25.4" y1="25.4" x2="-25.4" y2="-25.4" width="0.254" layer="94"/>
|
||||
<pin name="FB01/02" x="-30.48" y="12.7" length="middle"/>
|
||||
<pin name="FB01/05" x="-30.48" y="10.16" length="middle"/>
|
||||
<pin name="FB01/06" x="-30.48" y="7.62" length="middle"/>
|
||||
<pin name="FB01/08" x="-30.48" y="5.08" length="middle"/>
|
||||
<pin name="FB01/09" x="-30.48" y="2.54" length="middle"/>
|
||||
<pin name="FB01/11" x="-30.48" y="0" length="middle"/>
|
||||
<pin name="FB01/14" x="-30.48" y="-2.54" length="middle"/>
|
||||
<pin name="FB01/15" x="-30.48" y="-5.08" length="middle"/>
|
||||
<pin name="FB01/17" x="-30.48" y="-7.62" length="middle"/>
|
||||
<pin name="FB02/02" x="10.16" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/05" x="7.62" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/06" x="5.08" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/08" x="2.54" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/09" x="0" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/11" x="-2.54" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/14" x="-5.08" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/15" x="-7.62" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB02/17" x="-10.16" y="30.48" length="middle" rot="R270"/>
|
||||
<pin name="FB03/02" x="-10.16" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/05" x="-7.62" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/08" x="-5.08" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/09" x="-2.54" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/11" x="0" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/14" x="2.54" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/15" x="5.08" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/16" x="7.62" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB03/17" x="10.16" y="-30.48" length="middle" rot="R90"/>
|
||||
<pin name="FB04/02" x="30.48" y="-2.54" length="middle" rot="R180"/>
|
||||
<pin name="FB04/05" x="30.48" y="0" length="middle" rot="R180"/>
|
||||
<pin name="FB04/08" x="30.48" y="2.54" length="middle" rot="R180"/>
|
||||
<pin name="FB04/11" x="30.48" y="5.08" length="middle" rot="R180"/>
|
||||
<pin name="FB04/14" x="30.48" y="7.62" length="middle" rot="R180"/>
|
||||
<pin name="FB04/15" x="30.48" y="10.16" length="middle" rot="R180"/>
|
||||
<pin name="FB04/17" x="30.48" y="12.7" length="middle" rot="R180"/>
|
||||
<pin name="TCK" x="30.48" y="-10.16" length="middle" direction="in" rot="R180"/>
|
||||
<pin name="TDI" x="30.48" y="-15.24" length="middle" direction="in" rot="R180"/>
|
||||
<pin name="TDO" x="30.48" y="-12.7" length="middle" direction="out" rot="R180"/>
|
||||
<pin name="TMS" x="30.48" y="-17.78" length="middle" direction="in" rot="R180"/>
|
||||
<text x="-5.08" y="1.27" size="1.778" layer="95">>NAME</text>
|
||||
<text x="-5.08" y="-2.54" size="1.778" layer="96">>VALUE</text>
|
||||
</symbol>
|
||||
</symbols>
|
||||
<devicesets>
|
||||
<deviceset name="XC9572_S44">
|
||||
<gates>
|
||||
<gate name="G$1" symbol="XC9572_PC44" x="0" y="0"/>
|
||||
<gate name="SUPPLY" symbol="SUPPLY" x="58.42" y="-2.54" addlevel="request"/>
|
||||
</gates>
|
||||
<devices>
|
||||
<device name="PLCC" package="S44">
|
||||
<connects>
|
||||
<connect gate="G$1" pin="FB01/02" pad="1"/>
|
||||
<connect gate="G$1" pin="FB01/05" pad="2"/>
|
||||
<connect gate="G$1" pin="FB01/06" pad="3"/>
|
||||
<connect gate="G$1" pin="FB01/08" pad="4"/>
|
||||
<connect gate="G$1" pin="FB01/09" pad="5"/>
|
||||
<connect gate="G$1" pin="FB01/11" pad="6"/>
|
||||
<connect gate="G$1" pin="FB01/14" pad="7"/>
|
||||
<connect gate="G$1" pin="FB01/15" pad="8"/>
|
||||
<connect gate="G$1" pin="FB01/17" pad="9"/>
|
||||
<connect gate="G$1" pin="FB02/02" pad="35"/>
|
||||
<connect gate="G$1" pin="FB02/05" pad="36"/>
|
||||
<connect gate="G$1" pin="FB02/06" pad="37"/>
|
||||
<connect gate="G$1" pin="FB02/08" pad="38"/>
|
||||
<connect gate="G$1" pin="FB02/09" pad="39"/>
|
||||
<connect gate="G$1" pin="FB02/11" pad="40"/>
|
||||
<connect gate="G$1" pin="FB02/14" pad="42"/>
|
||||
<connect gate="G$1" pin="FB02/15" pad="43"/>
|
||||
<connect gate="G$1" pin="FB02/17" pad="44"/>
|
||||
<connect gate="G$1" pin="FB03/02" pad="11"/>
|
||||
<connect gate="G$1" pin="FB03/05" pad="12"/>
|
||||
<connect gate="G$1" pin="FB03/08" pad="13"/>
|
||||
<connect gate="G$1" pin="FB03/09" pad="14"/>
|
||||
<connect gate="G$1" pin="FB03/11" pad="18"/>
|
||||
<connect gate="G$1" pin="FB03/14" pad="19"/>
|
||||
<connect gate="G$1" pin="FB03/15" pad="20"/>
|
||||
<connect gate="G$1" pin="FB03/16" pad="24"/>
|
||||
<connect gate="G$1" pin="FB03/17" pad="22"/>
|
||||
<connect gate="G$1" pin="FB04/02" pad="25"/>
|
||||
<connect gate="G$1" pin="FB04/05" pad="26"/>
|
||||
<connect gate="G$1" pin="FB04/08" pad="27"/>
|
||||
<connect gate="G$1" pin="FB04/11" pad="28"/>
|
||||
<connect gate="G$1" pin="FB04/14" pad="29"/>
|
||||
<connect gate="G$1" pin="FB04/15" pad="33"/>
|
||||
<connect gate="G$1" pin="FB04/17" pad="34"/>
|
||||
<connect gate="G$1" pin="TCK" pad="17"/>
|
||||
<connect gate="G$1" pin="TDI" pad="15"/>
|
||||
<connect gate="G$1" pin="TDO" pad="30"/>
|
||||
<connect gate="G$1" pin="TMS" pad="16"/>
|
||||
<connect gate="SUPPLY" pin="GND@0" pad="10"/>
|
||||
<connect gate="SUPPLY" pin="GND@1" pad="23"/>
|
||||
<connect gate="SUPPLY" pin="GND@2" pad="31"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@0" pad="21"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@1" pad="41"/>
|
||||
<connect gate="SUPPLY" pin="VCCIO" pad="32"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
<device name="VQFP" package="SQFP-S-10X10-44">
|
||||
<connects>
|
||||
<connect gate="G$1" pin="FB01/02" pad="39"/>
|
||||
<connect gate="G$1" pin="FB01/05" pad="40"/>
|
||||
<connect gate="G$1" pin="FB01/06" pad="41"/>
|
||||
<connect gate="G$1" pin="FB01/08" pad="42"/>
|
||||
<connect gate="G$1" pin="FB01/09" pad="43"/>
|
||||
<connect gate="G$1" pin="FB01/11" pad="44"/>
|
||||
<connect gate="G$1" pin="FB01/14" pad="1"/>
|
||||
<connect gate="G$1" pin="FB01/15" pad="2"/>
|
||||
<connect gate="G$1" pin="FB01/17" pad="3"/>
|
||||
<connect gate="G$1" pin="FB02/02" pad="29"/>
|
||||
<connect gate="G$1" pin="FB02/05" pad="30"/>
|
||||
<connect gate="G$1" pin="FB02/06" pad="31"/>
|
||||
<connect gate="G$1" pin="FB02/08" pad="32"/>
|
||||
<connect gate="G$1" pin="FB02/09" pad="33"/>
|
||||
<connect gate="G$1" pin="FB02/11" pad="34"/>
|
||||
<connect gate="G$1" pin="FB02/14" pad="36"/>
|
||||
<connect gate="G$1" pin="FB02/15" pad="37"/>
|
||||
<connect gate="G$1" pin="FB02/17" pad="38"/>
|
||||
<connect gate="G$1" pin="FB03/02" pad="5"/>
|
||||
<connect gate="G$1" pin="FB03/05" pad="6"/>
|
||||
<connect gate="G$1" pin="FB03/08" pad="7"/>
|
||||
<connect gate="G$1" pin="FB03/09" pad="8"/>
|
||||
<connect gate="G$1" pin="FB03/11" pad="12"/>
|
||||
<connect gate="G$1" pin="FB03/14" pad="13"/>
|
||||
<connect gate="G$1" pin="FB03/15" pad="14"/>
|
||||
<connect gate="G$1" pin="FB03/16" pad="18"/>
|
||||
<connect gate="G$1" pin="FB03/17" pad="16"/>
|
||||
<connect gate="G$1" pin="FB04/02" pad="19"/>
|
||||
<connect gate="G$1" pin="FB04/05" pad="20"/>
|
||||
<connect gate="G$1" pin="FB04/08" pad="21"/>
|
||||
<connect gate="G$1" pin="FB04/11" pad="22"/>
|
||||
<connect gate="G$1" pin="FB04/14" pad="23"/>
|
||||
<connect gate="G$1" pin="FB04/15" pad="27"/>
|
||||
<connect gate="G$1" pin="FB04/17" pad="28"/>
|
||||
<connect gate="G$1" pin="TCK" pad="11"/>
|
||||
<connect gate="G$1" pin="TDI" pad="9"/>
|
||||
<connect gate="G$1" pin="TDO" pad="24"/>
|
||||
<connect gate="G$1" pin="TMS" pad="10"/>
|
||||
<connect gate="SUPPLY" pin="GND@0" pad="4"/>
|
||||
<connect gate="SUPPLY" pin="GND@1" pad="17"/>
|
||||
<connect gate="SUPPLY" pin="GND@2" pad="25"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@0" pad="15"/>
|
||||
<connect gate="SUPPLY" pin="VCCINT@1" pad="35"/>
|
||||
<connect gate="SUPPLY" pin="VCCIO" pad="26"/>
|
||||
</connects>
|
||||
<technologies>
|
||||
<technology name=""/>
|
||||
</technologies>
|
||||
</device>
|
||||
</devices>
|
||||
</deviceset>
|
||||
</devicesets>
|
||||
</library>
|
||||
</drawing>
|
||||
</eagle>
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 572 KiB |
103
README.md
103
README.md
|
|
@ -1,23 +1,68 @@
|
|||
# Apple][Sd
|
||||
SD card based ProFile replacement for enhanced Apple IIe computers
|
||||
# AppleIISd
|
||||
SD card based ProFile replacement for enhanced Apple IIe and IIgs computers
|
||||
|
||||
The **Apple][Sd** is a SD card based replaced for the ProFile harddrive. In contrast to other SD card based devices, this card does not replace a Disk II drive. Data is saved directly onto the SD card, not via images on a FAT system, like on other cards. The SD card is accessable with [CiderPress](http://a2ciderpress.com/).
|
||||
The **AppleIISd** is a SD card based replaced for the ProFile harddrive. In contrast to other SD card based devices, this card does not replace a Disk II drive. Data is saved directly onto the SD card, not via images on a FAT system, like on other cards. The SD card is accessable with [CiderPress](http://a2ciderpress.com/).
|
||||
|
||||
A Xilinx CPLD is used as a SPI controller and translates, together with the ROM driver, SD card data to/from the Apple IIe. The VHDL source is based on [SPI65/B](http://www.6502.org/users/andre/spi65b) by André Fachat.
|
||||
|
||||
The assembler sources were written in Merlin-8. The [schematics](AppleIISd.pdf) are available as PDF.
|
||||
The assembler sources are written for CC65. The [schematics](Binary/AppleIISd.pdf) are available as PDF.
|
||||
|
||||
## Features
|
||||
* up to 64MB storage space (2x 65535 blocks)
|
||||
* ProDOS driver in ROM
|
||||
* works with ProDOS and GS/OS
|
||||
* up to 128MB storage space (4x 65535 blocks)
|
||||
* ProDOS and Smartport driver in ROM
|
||||
* Firmware update from ProDOS
|
||||
* Auto boot
|
||||
* Access LED
|
||||
* Card detect and write protect sensing
|
||||
* Skip boot when Open-Apple key is pressed
|
||||
|
||||
## Requirements
|
||||
The Apple][Sd requires and has been tested on an enhanced IIe computer. The ROM code uses some 65c02 opcodes and will therefore not work on a II, II+ or unenhanced IIe. ProDOS versions 1.1 to 2.4.1 seem to work.
|
||||
The AppleIISd requires an enhanced IIe or IIgs computer. The ROM code uses some 65c02 opcodes and will therefore not work on a II, II+ or unenhanced IIe. It has been tested in the following combinations:
|
||||
* Apple IIgs Rom 01, GS/OS 6.0.4
|
||||
* Apple IIgs Rom 01, Prodos 2.4.1
|
||||
* Apple IIgs Rom 01, Prodos 1.9
|
||||
* Apple IIe enhanced, 128k, Prodos 2.4.1
|
||||
* Apple IIe enhanced, 128k, Prodos 1.9
|
||||
* Apple IIe enhanced, 64k, Prodos 1.9
|
||||
|
||||
When a 2732 type ROM is used, the binary image has to be programmed at offset 0x800, because A11 is always high for compatibility with 2716 type ROMs.
|
||||
## Binary distribution
|
||||
The following files in [Binary/](Binary) have been provided to eliminate the need to compile assembler or VHDL sources.
|
||||
|
||||
| File | Purpose |
|
||||
| ---- | ------- |
|
||||
| AppleIISd_xx44.jed | CPLD bitfiles for PC44 and VQ44 formfactors |
|
||||
| AppleIISd.bin | 2k Firmware binary for EPROM |
|
||||
| AppleIISd.hex | Same as above in INTEL-HEX format |
|
||||
| AppleIISd.bom.txt | BOM for the board |
|
||||
| AppleIISd.pdf | Schematic and layout |
|
||||
| Flasher.bin | Flasher program ProDOS binary |
|
||||
| Flasher.dsk | Complete ProDOS disk image with Flasher.bin and AppleIISd.bin |
|
||||
| Gerber_Vx.x.zip | Gerber files for different hw revisions |
|
||||
|
||||
## Smartport drive remapping
|
||||
The AppleIISd features Smartport drivers in ROM to provide more than two drives in both GS/OS and ProDOS.
|
||||
|
||||
As ProDOS supports only two drives per slot, additional drives on a Smartport device are mapped to 'phantom slots'. Version prior to version 2 supported only the remapping of drives when the card was in slot 5. Starting with version 2, the remapping seems to work on all slots. The following list shows the assignments as slot/drive, when no other devices are attached:
|
||||
|
||||
* Slot 7: 7/1, 7/2, 4/1, 4/2
|
||||
* Slot 6: 6/1, 6/2, 4/1, 4/1
|
||||
* Slot 5: 5/1, 5/2, 2/1, 2/1
|
||||
* Slot 4: 4/1, 4/2, 1/1, 1/2
|
||||
* Slot 3: 80 col HW, not usable
|
||||
* Slot 2: 2/1, 2/2, 4/1, 4/2
|
||||
* Slot 1: 1/1, 1/2, 4/1, 4/2
|
||||
|
||||
When more devices are connected, things get a little confusing ;-)
|
||||
|
||||
## Building the sources
|
||||
Be sure to have the newest version of CC65 (V2.16) and some kind of Make instaled, then type one of the following comands:
|
||||
```
|
||||
make # generate binaries
|
||||
make OPTIONS=mapfile,listing # generate mapfile and listing, too
|
||||
make clean # delete binaries
|
||||
```
|
||||
Alternatively use the VisualStudio solution.
|
||||
|
||||
## Timing
|
||||
The clock of the SPI bus *SCK* may be derived from either *Phi0* or the *7M* clock. Additionally, the divisor may be 2 to 8.
|
||||
|
|
@ -53,15 +98,47 @@ LDA $C0C0
|
|||
```
|
||||
|
||||
|
||||
## Registers
|
||||
The control registers of the *AppleIISd* are mapped to the usual I/O space at **$C0n0 - $C0n3**, where n is slot+8. All registers and bits are read/write, except where noted.
|
||||
|
||||
| Address | Function | Default value |
|
||||
| ------- | --------------- | ------------- |
|
||||
| $C0n0 | DATA | - |
|
||||
| $C0n1 | **0:** PGMEN<br>**1:** -<br>**2:** ECE<br>**3:** -<br>**4:** FRX<br>**5:** BSY (R)<br>**6:** -<br>**7:** TC (R) | 0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br> |
|
||||
| $C0n2 | unused | $00 |
|
||||
| $C0n3 | **0:** /SS<br>**1:** -<br>**2:** -<br>**3:** -<br>**4:** SDHC<br>**5:** WP (R)<br>**6:** CD (R)<br>**7:** INIT | 1<br>0<br>0<br>0<br>0<br>-<br>-<br>0 |
|
||||
|
||||
**DATA** SPI data register - Is used for both input and output. When the register is written to, the controller will output the byte on the SPI bus. When it is read from, it reflects the data that was received over the SPI bus.
|
||||
|
||||
**PGMEN** Program Enable - Enable programing of the internal firmware eeprom. Should be reset immediately after writing to the device.
|
||||
|
||||
**ECE** External Clock Enable - This bit enables the the external clock input to the SPI controller. In the *AppleIISd*, this effectively switches the SPI clock between 500kHz (ECE = 0) and 3.5MHz (ECE = 1).
|
||||
|
||||
**FRX** Fast Receive mode - When set to 1, fast receive mode triggers shifting upon reading or writing the SPI Data register. When set to 0, shifting is only triggered by writing the SPI data register.
|
||||
|
||||
**BSY** Busy - This bit is 1 as long as data is shifted out on the SPI bus. *BSY* is read-only.
|
||||
|
||||
**TC** Transfer Complete - This flag is set when the last bit has been shifted out onto the SPI bus and is cleared when *SPI data* is read.
|
||||
|
||||
**/SS** Slave select - Write 0 to this bit to select the SD card.
|
||||
|
||||
**SDHC** This bit is used by the initialization routine in firmware to signalize when a SDHC card was found. Do not write to manually.
|
||||
|
||||
**WP** Write Protect - This read-only bit is 0 when writing to the card is enabled by the switch on the card.
|
||||
|
||||
**CD** Card Detect - This read-only bit is 0 when a card is inserted.
|
||||
|
||||
**INIT** Initialized - This bit is set to 1 when the SD card has been initialized by the firmware. Do not write manually.
|
||||
|
||||
## TODOs
|
||||
* Much more testing
|
||||
* SRAM option (may never work, though)
|
||||
* Find a use for the IRQ pin
|
||||
* Use 28 pin socket to support other EPROMS than 2716 and 2732
|
||||
* Enable more than 4 volumes under GS/OS
|
||||
* Support for 6502 CPUs
|
||||
* Support for CP/M
|
||||
|
||||
## Known Bugs
|
||||
* Does not always boot in slot 7 (may be a faulty connector, though)
|
||||
* Does not work, when a Z80 card is present
|
||||
* Programs not startable from partitions 3 and 4 under ProDOS
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,100 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Project DefaultTargets="Build" ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
|
||||
<ItemGroup Label="ProjectConfigurations">
|
||||
<ProjectConfiguration Include="Debug|Win32">
|
||||
<Configuration>Debug</Configuration>
|
||||
<Platform>Win32</Platform>
|
||||
</ProjectConfiguration>
|
||||
<ProjectConfiguration Include="Release|Win32">
|
||||
<Configuration>Release</Configuration>
|
||||
<Platform>Win32</Platform>
|
||||
</ProjectConfiguration>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<None Include="Flasher.bin.map" />
|
||||
<None Include="makefile" />
|
||||
<None Include="Makefile.options" />
|
||||
<None Include="obj\Flasher.lst" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="src\Flasher.c" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="src\AppleIISd.h" />
|
||||
</ItemGroup>
|
||||
<PropertyGroup Label="Globals">
|
||||
<ProjectGuid>{B2CF2E9D-62A7-4A68-9477-9B15A8707E78}</ProjectGuid>
|
||||
<Keyword>MakeFileProj</Keyword>
|
||||
<ProjectName>Flasher</ProjectName>
|
||||
</PropertyGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
|
||||
<ConfigurationType>Makefile</ConfigurationType>
|
||||
<UseDebugLibraries>true</UseDebugLibraries>
|
||||
<PlatformToolset>v140</PlatformToolset>
|
||||
</PropertyGroup>
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
|
||||
<ConfigurationType>Makefile</ConfigurationType>
|
||||
<UseDebugLibraries>false</UseDebugLibraries>
|
||||
<PlatformToolset>v140</PlatformToolset>
|
||||
</PropertyGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
|
||||
<ImportGroup Label="ExtensionSettings">
|
||||
</ImportGroup>
|
||||
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
|
||||
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
|
||||
</ImportGroup>
|
||||
<ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
|
||||
<Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
|
||||
</ImportGroup>
|
||||
<PropertyGroup Label="UserMacros" />
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
|
||||
<NMakeOutput>
|
||||
</NMakeOutput>
|
||||
<NMakePreprocessorDefinitions>__APPLE2__;__APPLE2ENH__;__fastcall__=__fastcall;_MSC_VER=0;__attribute__</NMakePreprocessorDefinitions>
|
||||
<ExecutablePath>$(PATH);C:\cc65\bin</ExecutablePath>
|
||||
<IncludePath>C:\cc65\include</IncludePath>
|
||||
<LibraryPath>C:\cc65\lib</LibraryPath>
|
||||
<LibraryWPath />
|
||||
<ExcludePath />
|
||||
<NMakeBuildCommandLine>$(MAKE_HOME)\make OPTIONS=mapfile,listing</NMakeBuildCommandLine>
|
||||
<SourcePath>$(ProjectDir)\src</SourcePath>
|
||||
<NMakeReBuildCommandLine>$(MAKE_HOME)\make clean
|
||||
$(MAKE_HOME)\make OPTIONS=mapfile,listing</NMakeReBuildCommandLine>
|
||||
<OutDir>$(SolutionDir)\</OutDir>
|
||||
<NMakeCleanCommandLine>$(MAKE_HOME)\make clean</NMakeCleanCommandLine>
|
||||
<ReferencePath />
|
||||
</PropertyGroup>
|
||||
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
|
||||
<NMakeOutput>
|
||||
</NMakeOutput>
|
||||
<NMakePreprocessorDefinitions>
|
||||
</NMakePreprocessorDefinitions>
|
||||
<NMakeBuildCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"</NMakeBuildCommandLine>
|
||||
<NMakeReBuildCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make clean -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
$(MAKE_HOME)\make -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"
|
||||
</NMakeReBuildCommandLine>
|
||||
<NMakeCleanCommandLine>del /S /Q "$(ProjectDir)makefile.options
|
||||
$(MAKE_HOME)\make clean -C "$(ProjectDir)\" PROGRAM="$(ProjectDir)$(Configuration)\$(ProjectName)"
|
||||
rmdir /S /Q "$(ProjectDir)obj\Win32"
|
||||
rmdir /S /Q "$(SolutionDir)Release"</NMakeCleanCommandLine>
|
||||
<ExecutablePath>$(PATH);C:\cc65\bin</ExecutablePath>
|
||||
<IncludePath>$(VC_IncludePath);C:\cc65\include</IncludePath>
|
||||
<ReferencePath />
|
||||
<LibraryPath>C:\cc65\lib</LibraryPath>
|
||||
<ExcludePath />
|
||||
<LibraryWPath />
|
||||
<OutDir>$(SolutionDir)$\</OutDir>
|
||||
</PropertyGroup>
|
||||
<ItemDefinitionGroup>
|
||||
</ItemDefinitionGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
|
||||
<ImportGroup Label="ExtensionTargets">
|
||||
</ImportGroup>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
|
||||
<ItemGroup>
|
||||
<None Include="makefile" />
|
||||
<None Include="Makefile.options" />
|
||||
<None Include="Flasher.bin.map" />
|
||||
<None Include="obj\Flasher.lst" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClCompile Include="src\Flasher.c" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="src\AppleIISd.h" />
|
||||
</ItemGroup>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
# Configuration for ProDOS 8 system programs (allowing for 3KB in LC)
|
||||
|
||||
SYMBOLS {
|
||||
__EXEHDR__: type = import;
|
||||
__FILETYPE__: type = weak, value = $00FF; # ProDOS file type
|
||||
__STACKSIZE__: type = weak, value = $0800; # 2k stack
|
||||
__LCADDR__: type = weak, value = $D400; # Behind quit code
|
||||
__LCSIZE__: type = weak, value = $0C00; # Rest of bank two
|
||||
}
|
||||
MEMORY {
|
||||
ZP: file = "", define = yes, start = $0080, size = $001A;
|
||||
HEADER: file = %O, start = $2000 - $003A, size = $003A;
|
||||
MAIN: file = %O, define = yes, start = $2000, size = $BF00 - $2000;
|
||||
BSS: file = "", start = __ONCE_RUN__, size = $BF00 - __STACKSIZE__ - __ONCE_RUN__;
|
||||
LC: file = "", define = yes, start = __LCADDR__, size = __LCSIZE__;
|
||||
}
|
||||
SEGMENTS {
|
||||
ZEROPAGE: load = ZP, type = zp;
|
||||
EXEHDR: load = HEADER, type = ro, optional = yes;
|
||||
STARTUP: load = MAIN, type = ro;
|
||||
LOWCODE: load = MAIN, type = ro, optional = yes;
|
||||
CODE: load = MAIN, type = ro;
|
||||
RODATA: load = MAIN, type = ro;
|
||||
DATA: load = MAIN, type = rw;
|
||||
INIT: load = MAIN, type = rw;
|
||||
ONCE: load = MAIN, type = ro, define = yes;
|
||||
LC: load = MAIN, run = LC, type = ro, optional = yes;
|
||||
BSS: load = BSS, type = bss, define = yes;
|
||||
}
|
||||
FEATURES {
|
||||
CONDES: type = constructor,
|
||||
label = __CONSTRUCTOR_TABLE__,
|
||||
count = __CONSTRUCTOR_COUNT__,
|
||||
segment = ONCE;
|
||||
CONDES: type = destructor,
|
||||
label = __DESTRUCTOR_TABLE__,
|
||||
count = __DESTRUCTOR_COUNT__,
|
||||
segment = RODATA;
|
||||
CONDES: type = interruptor,
|
||||
label = __INTERRUPTOR_TABLE__,
|
||||
count = __INTERRUPTOR_COUNT__,
|
||||
segment = RODATA,
|
||||
import = __CALLIRQ__;
|
||||
}
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
make clean
|
||||
make
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -d ..\Binary\Flasher.dsk flasher
|
||||
java -jar ..\Binary\AppleCommander-ac-1.5.0.jar -as ..\Binary\Flasher.dsk flasher < Flasher.bin
|
||||
copy Flasher.bin ..\Binary
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#!/bin/bash
|
||||
|
||||
make clean
|
||||
make
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -d ../Binary/Flasher.dsk flasher
|
||||
java -jar ../Binary/AppleCommander-ac-1.5.0.jar -as ../Binary/Flasher.dsk flasher < Flasher.bin
|
||||
cp Flasher.bin ../Binary/
|
||||
|
|
@ -0,0 +1,346 @@
|
|||
###############################################################################
|
||||
### Generic Makefile for cc65 projects - full version with abstract options ###
|
||||
### V1.3.0(w) 2010 - 2013 Oliver Schmidt & Patryk "Silver Dream !" ?ogiewa ###
|
||||
###############################################################################
|
||||
|
||||
###############################################################################
|
||||
### In order to override defaults - values can be assigned to the variables ###
|
||||
###############################################################################
|
||||
|
||||
# Space or comma separated list of cc65 supported target platforms to build for.
|
||||
# Default: c64 (lowercase!)
|
||||
TARGETS := apple2enh
|
||||
|
||||
# Name of the final, single-file executable.
|
||||
# Default: name of the current dir with target name appended
|
||||
PROGRAM := Flasher
|
||||
|
||||
# Path(s) to additional libraries required for linking the program
|
||||
# Use only if you don't want to place copies of the libraries in SRCDIR
|
||||
# Default: none
|
||||
LIBS :=
|
||||
|
||||
# Custom linker configuration file
|
||||
# Use only if you don't want to place it in SRCDIR
|
||||
# Default: none
|
||||
CONFIG := apple2enh-system.cfg
|
||||
|
||||
# Additional C compiler flags and options.
|
||||
# Default: none
|
||||
CFLAGS =
|
||||
|
||||
# Additional assembler flags and options.
|
||||
# Default: none
|
||||
ASFLAGS =
|
||||
|
||||
# Additional linker flags and options.
|
||||
# Default: none
|
||||
LDFLAGS =
|
||||
|
||||
# Path to the directory containing C and ASM sources.
|
||||
# Default: src
|
||||
SRCDIR :=
|
||||
|
||||
# Path to the directory where object files are to be stored (inside respective target subdirectories).
|
||||
# Default: obj
|
||||
OBJDIR :=
|
||||
|
||||
# Command used to run the emulator.
|
||||
# Default: depending on target platform. For default (c64) target: x64 -kernal kernal -VICIIdsize -autoload
|
||||
EMUCMD :=
|
||||
|
||||
# Optional commands used before starting the emulation process, and after finishing it.
|
||||
# Default: none
|
||||
# Examples
|
||||
#PREEMUCMD := osascript -e "tell application \"System Events\" to set isRunning to (name of processes) contains \"X11.bin\"" -e "if isRunning is true then tell application \"X11\" to activate"
|
||||
#PREEMUCMD := osascript -e "tell application \"X11\" to activate"
|
||||
#POSTEMUCMD := osascript -e "tell application \"System Events\" to tell process \"X11\" to set visible to false"
|
||||
#POSTEMUCMD := osascript -e "tell application \"Terminal\" to activate"
|
||||
PREEMUCMD :=
|
||||
POSTEMUCMD :=
|
||||
|
||||
# On Windows machines VICE emulators may not be available in the PATH by default.
|
||||
# In such case, please set the variable below to point to directory containing
|
||||
# VICE emulators.
|
||||
#VICE_HOME := "C:\Program Files\WinVICE-2.2-x86\"
|
||||
VICE_HOME :=
|
||||
|
||||
# Options state file name. You should not need to change this, but for those
|
||||
# rare cases when you feel you really need to name it differently - here you are
|
||||
STATEFILE := Makefile.options
|
||||
|
||||
###################################################################################
|
||||
#### DO NOT EDIT BELOW THIS LINE, UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! ####
|
||||
###################################################################################
|
||||
|
||||
###################################################################################
|
||||
### Mapping abstract options to the actual compiler, assembler and linker flags ###
|
||||
### Predefined compiler, assembler and linker flags, used with abstract options ###
|
||||
### valid for 2.14.x. Consult the documentation of your cc65 version before use ###
|
||||
###################################################################################
|
||||
|
||||
# Compiler flags used to tell the compiler to optimise for SPEED
|
||||
define _optspeed_
|
||||
CFLAGS += -Oris
|
||||
endef
|
||||
|
||||
# Compiler flags used to tell the compiler to optimise for SIZE
|
||||
define _optsize_
|
||||
CFLAGS += -Or
|
||||
endef
|
||||
|
||||
# Compiler and assembler flags for generating listings
|
||||
define _listing_
|
||||
CFLAGS += --listing $$(@:.o=.lst) -T
|
||||
ASFLAGS += --listing $$(@:.o=.lst)
|
||||
REMOVES += $(addsuffix .lst,$(basename $(OBJECTS)))
|
||||
endef
|
||||
|
||||
# Linker flags for generating map file
|
||||
define _mapfile_
|
||||
LDFLAGS += --mapfile $$@.map
|
||||
REMOVES += $(PROGRAM).map
|
||||
endef
|
||||
|
||||
# Linker flags for generating VICE label file
|
||||
define _labelfile_
|
||||
LDFLAGS += -Ln $$@.lbl
|
||||
REMOVES += $(PROGRAM).lbl
|
||||
endef
|
||||
|
||||
# Linker flags for generating a debug file
|
||||
define _debugfile_
|
||||
LDFLAGS += -Wl --dbgfile,$$@.dbg
|
||||
REMOVES += $(PROGRAM).dbg
|
||||
endef
|
||||
|
||||
###############################################################################
|
||||
### Defaults to be used if nothing defined in the editable sections above ###
|
||||
###############################################################################
|
||||
|
||||
# Presume the C64 target like the cl65 compile & link utility does.
|
||||
# Set TARGETS to override.
|
||||
ifeq ($(TARGETS),)
|
||||
TARGETS := c64
|
||||
endif
|
||||
|
||||
# Presume we're in a project directory so name the program like the current
|
||||
# directory. Set PROGRAM to override.
|
||||
ifeq ($(PROGRAM),)
|
||||
PROGRAM := $(notdir $(CURDIR))
|
||||
endif
|
||||
|
||||
# Presume the C and asm source files to be located in the subdirectory 'src'.
|
||||
# Set SRCDIR to override.
|
||||
ifeq ($(SRCDIR),)
|
||||
SRCDIR := src
|
||||
endif
|
||||
|
||||
# Presume the object and dependency files to be located in the subdirectory
|
||||
# 'obj' (which will be created). Set OBJDIR to override.
|
||||
ifeq ($(OBJDIR),)
|
||||
OBJDIR := obj
|
||||
endif
|
||||
TARGETOBJDIR := $(OBJDIR)
|
||||
|
||||
# On Windows it is mandatory to have CC65_HOME set. So do not unnecessarily
|
||||
# rely on cl65 being added to the PATH in this scenario.
|
||||
ifdef CC65_HOME
|
||||
CC := $(CC65_HOME)/bin/cl65
|
||||
else
|
||||
CC := cl65
|
||||
endif
|
||||
|
||||
# Default emulator commands and options for particular targets.
|
||||
# Set EMUCMD to override.
|
||||
c64_EMUCMD := $(VICE_HOME)x64 -kernal kernal -VICIIdsize -autoload
|
||||
c128_EMUCMD := $(VICE_HOME)x128 -kernal kernal -VICIIdsize -autoload
|
||||
vic20_EMUCMD := $(VICE_HOME)xvic -kernal kernal -VICdsize -autoload
|
||||
pet_EMUCMD := $(VICE_HOME)xpet -Crtcdsize -autoload
|
||||
plus4_EMUCMD := $(VICE_HOME)xplus4 -TEDdsize -autoload
|
||||
# So far there is no x16 emulator in VICE (why??) so we have to use xplus4 with -memsize option
|
||||
c16_EMUCMD := $(VICE_HOME)xplus4 -ramsize 16 -TEDdsize -autoload
|
||||
cbm510_EMUCMD := $(VICE_HOME)xcbm2 -model 510 -VICIIdsize -autoload
|
||||
cbm610_EMUCMD := $(VICE_HOME)xcbm2 -model 610 -Crtcdsize -autoload
|
||||
atari_EMUCMD := atari800 -windowed -xl -pal -nopatchall -run
|
||||
|
||||
ifeq ($(EMUCMD),)
|
||||
EMUCMD = $($(CC65TARGET)_EMUCMD)
|
||||
endif
|
||||
|
||||
###############################################################################
|
||||
### The magic begins ###
|
||||
###############################################################################
|
||||
|
||||
# The "Native Win32" GNU Make contains quite some workarounds to get along with
|
||||
# cmd.exe as shell. However it does not provide means to determine that it does
|
||||
# actually activate those workarounds. Especially $(SHELL) does NOT contain the
|
||||
# value 'cmd.exe'. So the usual way to determine if cmd.exe is being used is to
|
||||
# execute the command 'echo' without any parameters. Only cmd.exe will return a
|
||||
# non-empty string - saying 'ECHO is on/off'.
|
||||
#
|
||||
# Many "Native Win32" programs accept '/' as directory delimiter just fine. How-
|
||||
# ever the internal commands of cmd.exe generally require '\' to be used.
|
||||
#
|
||||
# cmd.exe has an internal command 'mkdir' that doesn't understand nor require a
|
||||
# '-p' to create parent directories as needed.
|
||||
#
|
||||
# cmd.exe has an internal command 'del' that reports a syntax error if executed
|
||||
# without any file so make sure to call it only if there's an actual argument.
|
||||
ifeq ($(shell echo),)
|
||||
MKDIR = mkdir -p $1
|
||||
RMDIR = rmdir $1
|
||||
RMFILES = $(RM) $1
|
||||
else
|
||||
MKDIR = mkdir $(subst /,\,$1)
|
||||
RMDIR = rmdir $(subst /,\,$1)
|
||||
RMFILES = $(if $1,del /f $(subst /,\,$1))
|
||||
endif
|
||||
COMMA := ,
|
||||
SPACE := $(N/A) $(N/A)
|
||||
define NEWLINE
|
||||
|
||||
|
||||
endef
|
||||
# Note: Do not remove any of the two empty lines above !
|
||||
|
||||
TARGETLIST := $(subst $(COMMA),$(SPACE),$(TARGETS))
|
||||
|
||||
ifeq ($(words $(TARGETLIST)),1)
|
||||
|
||||
# Set PROGRAM to something like 'myprog.c64'.
|
||||
override PROGRAM := $(PROGRAM).bin
|
||||
|
||||
# Set SOURCES to something like 'src/foo.c src/bar.s'.
|
||||
# Use of assembler files with names ending differently than .s is deprecated!
|
||||
SOURCES := $(wildcard $(SRCDIR)/*.c)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.s)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.asm)
|
||||
SOURCES += $(wildcard $(SRCDIR)/*.a65)
|
||||
|
||||
# Add to SOURCES something like 'src/c64/me.c src/c64/too.s'.
|
||||
# Use of assembler files with names ending differently than .s is deprecated!
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.c)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.s)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.asm)
|
||||
SOURCES += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.a65)
|
||||
|
||||
# Set OBJECTS to something like 'obj/c64/foo.o obj/c64/bar.o'.
|
||||
OBJECTS := $(addsuffix .o,$(basename $(addprefix $(TARGETOBJDIR)/,$(notdir $(SOURCES)))))
|
||||
|
||||
# Set DEPENDS to something like 'obj/c64/foo.d obj/c64/bar.d'.
|
||||
DEPENDS := $(OBJECTS:.o=.d)
|
||||
|
||||
# Add to LIBS something like 'src/foo.lib src/c64/bar.lib'.
|
||||
LIBS += $(wildcard $(SRCDIR)/*.lib)
|
||||
LIBS += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.lib)
|
||||
|
||||
# Add to CONFIG something like 'src/c64/bar.cfg src/foo.cfg'.
|
||||
CONFIG += $(wildcard $(SRCDIR)/$(TARGETLIST)/*.cfg)
|
||||
CONFIG += $(wildcard $(SRCDIR)/*.cfg)
|
||||
|
||||
# Select CONFIG file to use. Target specific configs have higher priority.
|
||||
ifneq ($(word 2,$(CONFIG)),)
|
||||
CONFIG := $(firstword $(CONFIG))
|
||||
$(info Using config file $(CONFIG) for linking)
|
||||
endif
|
||||
|
||||
.SUFFIXES:
|
||||
.PHONY: all test clean zap love
|
||||
|
||||
all: $(PROGRAM)
|
||||
|
||||
-include $(DEPENDS)
|
||||
-include $(STATEFILE)
|
||||
|
||||
# If OPTIONS are given on the command line then save them to STATEFILE
|
||||
# if (and only if) they have actually changed. But if OPTIONS are not
|
||||
# given on the command line then load them from STATEFILE. Have object
|
||||
# files depend on STATEFILE only if it actually exists.
|
||||
ifeq ($(origin OPTIONS),command line)
|
||||
ifneq ($(OPTIONS),$(_OPTIONS_))
|
||||
ifeq ($(OPTIONS),)
|
||||
$(info Removing OPTIONS)
|
||||
$(shell $(RM) $(STATEFILE))
|
||||
$(eval $(STATEFILE):)
|
||||
else
|
||||
$(info Saving OPTIONS=$(OPTIONS))
|
||||
$(shell echo _OPTIONS_=$(OPTIONS) > $(STATEFILE))
|
||||
endif
|
||||
$(eval $(OBJECTS): $(STATEFILE))
|
||||
endif
|
||||
else
|
||||
ifeq ($(origin _OPTIONS_),file)
|
||||
$(info Using saved OPTIONS=$(_OPTIONS_))
|
||||
OPTIONS = $(_OPTIONS_)
|
||||
$(eval $(OBJECTS): $(STATEFILE))
|
||||
endif
|
||||
endif
|
||||
|
||||
# Transform the abstract OPTIONS to the actual cc65 options.
|
||||
$(foreach o,$(subst $(COMMA),$(SPACE),$(OPTIONS)),$(eval $(_$o_)))
|
||||
|
||||
# Strip potential variant suffix from the actual cc65 target.
|
||||
CC65TARGET := $(firstword $(subst .,$(SPACE),$(TARGETLIST)))
|
||||
|
||||
# The remaining targets.
|
||||
$(TARGETOBJDIR):
|
||||
$(call MKDIR,$@)
|
||||
|
||||
vpath %.c $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.c | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(CFLAGS) -o $@ $<
|
||||
|
||||
vpath %.s $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.s | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
vpath %.asm $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.asm | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
vpath %.a65 $(SRCDIR)/$(TARGETLIST) $(SRCDIR)
|
||||
|
||||
$(TARGETOBJDIR)/%.o: %.a65 | $(TARGETOBJDIR)
|
||||
$(CC) -t $(CC65TARGET) -c --create-dep $(@:.o=.d) $(ASFLAGS) -o $@ $<
|
||||
|
||||
$(PROGRAM): $(CONFIG) $(OBJECTS) $(LIBS)
|
||||
$(CC) -t $(CC65TARGET) $(LDFLAGS) -o $@ $(patsubst %.cfg,-C %.cfg,$^)
|
||||
|
||||
test: $(PROGRAM)
|
||||
$(PREEMUCMD)
|
||||
$(EMUCMD) $<
|
||||
$(POSTEMUCMD)
|
||||
|
||||
clean:
|
||||
$(call RMFILES,$(OBJECTS))
|
||||
$(call RMFILES,$(DEPENDS))
|
||||
$(call RMFILES,$(REMOVES))
|
||||
$(call RMFILES,$(PROGRAM))
|
||||
|
||||
else # $(words $(TARGETLIST)),1
|
||||
|
||||
all test clean:
|
||||
$(foreach t,$(TARGETLIST),$(MAKE) TARGETS=$t $@$(NEWLINE))
|
||||
|
||||
endif # $(words $(TARGETLIST)),1
|
||||
|
||||
OBJDIRLIST := $(wildcard $(OBJDIR)/*)
|
||||
|
||||
zap:
|
||||
$(foreach o,$(OBJDIRLIST),-$(call RMFILES,$o/*.o $o/*.d $o/*.lst)$(NEWLINE))
|
||||
$(foreach o,$(OBJDIRLIST),-$(call RMDIR,$o)$(NEWLINE))
|
||||
-$(call RMDIR,$(OBJDIR))
|
||||
-$(call RMFILES,$(basename $(PROGRAM)).* $(STATEFILE))
|
||||
|
||||
love:
|
||||
@echo "Not war, eh?"
|
||||
|
||||
###################################################################
|
||||
### Place your additional targets in the additional Makefiles ###
|
||||
### in the same directory - their names have to end with ".mk"! ###
|
||||
###################################################################
|
||||
-include *.mk
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
#ifndef APPLE_II_SD_H
|
||||
#define APPLE_II_SD_H
|
||||
|
||||
typedef unsigned char uint8;
|
||||
typedef unsigned short uint16;
|
||||
typedef unsigned long uint32;
|
||||
typedef unsigned char boolean;
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#define SLOT_IO_START (volatile uint8*)0xC080
|
||||
#define SLOT_ROM_START (volatile uint8*)0xC000
|
||||
#define EXT_ROM_START (volatile uint8*)0xC800
|
||||
|
||||
#define CFFF (volatile uint8*)0xCFFF
|
||||
|
||||
typedef volatile struct
|
||||
{
|
||||
// data register
|
||||
// +0
|
||||
uint8 data;
|
||||
|
||||
// status register
|
||||
// +1
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned pgmen : 1;
|
||||
unsigned : 1;
|
||||
unsigned ece : 1;
|
||||
unsigned : 1;
|
||||
unsigned frx : 1;
|
||||
const unsigned bsy : 1;
|
||||
unsigned : 1;
|
||||
const unsigned tc : 1;
|
||||
};
|
||||
|
||||
uint8 status;
|
||||
} status;
|
||||
|
||||
// clock divisor register, unused
|
||||
// +2
|
||||
uint8 clkDiv;
|
||||
|
||||
// slave select and card state register
|
||||
// +3
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned slaveSel : 1;
|
||||
unsigned : 3;
|
||||
unsigned sdhc : 1;
|
||||
const unsigned wp : 1;
|
||||
const unsigned card : 1;
|
||||
unsigned inited : 1;
|
||||
};
|
||||
|
||||
uint8 ss_card;
|
||||
} ss_card;
|
||||
} APPLE_II_SD_T;
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
#include "AppleIISd.h"
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdio.h>
|
||||
#include <errno.h>
|
||||
#include <conio.h>
|
||||
#include <string.h>
|
||||
#include <apple2enh.h>
|
||||
|
||||
// Binary can't be larger than 2k
|
||||
#define BUFFER_SIZE 2048
|
||||
#define BIN_FILE_NAME "AppleIISd.bin"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
STATE_0, // pipe
|
||||
STATE_1, // slash
|
||||
STATE_2, // hyphen
|
||||
STATE_3, // backslash
|
||||
|
||||
STATE_LAST // don't use
|
||||
} STATE_CURSOR_T;
|
||||
|
||||
const char state_char[STATE_LAST] = { '|', '/', '-', '\\' };
|
||||
static uint8 buffer[BUFFER_SIZE];
|
||||
|
||||
static void writeChip(const uint8* pSource, volatile uint8* pDest, uint16 length);
|
||||
static boolean verifyChip(const uint8* pSource, volatile uint8* pDest, uint16 length);
|
||||
static void printStatus(uint8 percentage);
|
||||
|
||||
int main()
|
||||
{
|
||||
int retval = 1;
|
||||
FILE* pFile;
|
||||
char slotNum;
|
||||
boolean erase = FALSE;
|
||||
uint16 fileSize = 0;
|
||||
|
||||
APPLE_II_SD_T* pAIISD;
|
||||
volatile uint8* pSlotRom = SLOT_ROM_START;
|
||||
volatile uint8 dummy;
|
||||
|
||||
videomode(VIDEOMODE_40COL);
|
||||
clrscr();
|
||||
cprintf("AppleIISd firmware flasher V1.2\r\n");
|
||||
cprintf("(c) 2019-2020 Florian Reitz\r\n\r\n");
|
||||
|
||||
// ask for slot
|
||||
cursor(1); // enable blinking cursor
|
||||
cprintf("Slot number (1-7): ");
|
||||
cscanf("%c", &slotNum);
|
||||
slotNum -= 0x30;
|
||||
cursor(0); // disable blinking cursor
|
||||
|
||||
if(slotNum == 0)
|
||||
{
|
||||
// erase device
|
||||
erase = TRUE;
|
||||
// ask for slot
|
||||
cursor(1); // enable blinking cursor
|
||||
cprintf("Erase device in slot number (1-7): ");
|
||||
cscanf("%c", &slotNum);
|
||||
slotNum -= 0x30;
|
||||
cursor(0); // disable blinking cursor
|
||||
}
|
||||
|
||||
// check if slot is valid
|
||||
if((slotNum < 1) || (slotNum > 7))
|
||||
{
|
||||
cprintf("\r\nInvalid slot number!");
|
||||
cgetc();
|
||||
return 1; // failure
|
||||
}
|
||||
|
||||
pAIISD = (APPLE_II_SD_T*)(SLOT_IO_START + (slotNum << 4));
|
||||
pSlotRom += slotNum << 8;
|
||||
|
||||
if(erase)
|
||||
{
|
||||
fileSize = BUFFER_SIZE;
|
||||
memset(buffer, 0, sizeof(buffer));
|
||||
}
|
||||
else
|
||||
{
|
||||
// open file
|
||||
pFile = fopen(BIN_FILE_NAME, "rb");
|
||||
if(pFile)
|
||||
{
|
||||
// read buffer
|
||||
fileSize = fread(buffer, 1, sizeof(buffer), pFile);
|
||||
fclose(pFile);
|
||||
pFile = NULL;
|
||||
|
||||
if(fileSize != BUFFER_SIZE)
|
||||
{
|
||||
cprintf("\r\nWrong file size: %d\r\n", fileSize);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
cprintf("\r\nCan't open %s file\r\n", BIN_FILE_NAME);
|
||||
fileSize = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if(fileSize == BUFFER_SIZE)
|
||||
{
|
||||
// enable write
|
||||
pAIISD->status.pgmen = 1;
|
||||
|
||||
// write to SLOTROM
|
||||
cprintf("\r\n\r\nFlashing SLOTROM: ");
|
||||
writeChip(buffer, pSlotRom, 256);
|
||||
|
||||
cprintf("\r\nVerifying SLOTROM: ");
|
||||
if(verifyChip(buffer, pSlotRom, 256))
|
||||
{
|
||||
// write to EXT_ROM
|
||||
cprintf("\r\n\r\nFlashing EXTROM: ");
|
||||
|
||||
// clear CFFF and dummy read to enable correct EXT_ROM
|
||||
dummy = *CFFF;
|
||||
dummy = *pSlotRom;
|
||||
|
||||
writeChip(buffer + 256, EXT_ROM_START, fileSize - 256);
|
||||
cprintf("\r\nVerifying EXTROM: ");
|
||||
|
||||
dummy = *CFFF;
|
||||
dummy = *pSlotRom;
|
||||
|
||||
if(verifyChip(buffer + 256, EXT_ROM_START, fileSize - 256))
|
||||
{
|
||||
cprintf("\r\n\r\nFlashing finished!\n");
|
||||
retval = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// disable write
|
||||
pAIISD->status.pgmen = 0;
|
||||
}
|
||||
|
||||
cgetc();
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void writeChip(const uint8* pSource, volatile uint8* pDest, uint16 length)
|
||||
{
|
||||
uint32 i;
|
||||
volatile uint8 readData;
|
||||
|
||||
for(i=0; i<length; i++)
|
||||
{
|
||||
pDest[i] = pSource[i];
|
||||
printStatus((i * 100u / length) + 1);
|
||||
|
||||
// wait for write cycle
|
||||
do
|
||||
{
|
||||
readData = pDest[i];
|
||||
}
|
||||
while((readData & 0x80) != (pSource[i] & 0x80));
|
||||
}
|
||||
}
|
||||
|
||||
static boolean verifyChip(const uint8* pSource, volatile uint8* pDest, uint16 length)
|
||||
{
|
||||
uint32 i;
|
||||
|
||||
for(i=0; i<length; i++)
|
||||
{
|
||||
printStatus((i * 100u / length) + 1);
|
||||
|
||||
if(pDest[i] != pSource[i])
|
||||
{
|
||||
// verification not successful
|
||||
cprintf("\r\n\r\n!!! Verification failed at %p !!!\r\n", &pDest[i]);
|
||||
cprintf("Was 0x%02hhX, should be 0x%02hhX\r\n", pDest[i], pSource[i]);
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static void printStatus(uint8 percentage)
|
||||
{
|
||||
static STATE_CURSOR_T state = STATE_0;
|
||||
uint8 wait = 0;
|
||||
uint8 x = wherex();
|
||||
char cState = (percentage < 100) ? state_char[state] : ' ';
|
||||
|
||||
cprintf("% 3hhu%% %c", percentage, cState);
|
||||
gotox(x);
|
||||
|
||||
state++;
|
||||
if(state == STATE_LAST)
|
||||
{
|
||||
state = STATE_0;
|
||||
}
|
||||
}
|
||||
|
|
@ -31,27 +31,29 @@ use IEEE.STD_LOGIC_1164.ALL;
|
|||
|
||||
entity AddressDecoder is
|
||||
Port ( A : in std_logic_vector (11 downto 8);
|
||||
B : out std_logic_vector (10 downto 8); -- to EPROM
|
||||
B : out std_logic_vector (10 downto 8); -- to EEPROM
|
||||
CLK : in std_logic;
|
||||
PHI0 : in std_logic;
|
||||
RNW : in std_logic;
|
||||
NDEV_SEL : in std_logic; -- $C0n0 - $C0nF
|
||||
NIO_SEL : in std_logic; -- $Cs00 - $CsFF
|
||||
NIO_STB : in std_logic; -- $C800 - $CFFF
|
||||
NDEV_SEL : in std_logic; -- $C0n0 - $C0nF, CPLD registers
|
||||
NIO_SEL : in std_logic; -- $Cs00 - $CsFF, EEPROM bank 0
|
||||
NIO_STB : in std_logic; -- $C800 - $CFFF, EEPROM banks 1 to 7
|
||||
NRESET : in std_logic;
|
||||
DATA_EN : out std_logic; -- to CPLD
|
||||
DATA_EN : out std_logic; -- to CPLD
|
||||
PGM_EN : in std_logic; -- from CPLD;
|
||||
NG : out std_logic; -- to bus transceiver
|
||||
NOE : out std_logic); -- to EPROM
|
||||
NOE : out std_logic; -- to EEPROM
|
||||
NWE : out std_logic); -- to EEPROM
|
||||
end AddressDecoder;
|
||||
|
||||
architecture Behavioral of AddressDecoder is
|
||||
|
||||
signal cfxx : std_logic; -- $C800 - $CFFF disable
|
||||
signal noe_int : std_logic;
|
||||
signal ndev_sel_int : std_logic;
|
||||
signal nio_sel_int : std_logic;
|
||||
signal nio_stb_int : std_logic;
|
||||
signal ncs : std_logic; -- $C800 - $CFFF enabled
|
||||
signal ncs : std_logic; -- $C800 - $CFFE enabled
|
||||
signal a_int : std_logic_vector (11 downto 8);
|
||||
|
||||
begin
|
||||
|
||||
|
|
@ -61,17 +63,32 @@ begin
|
|||
-- only from the first rising edge of 7M when any select
|
||||
-- line is low (Phi0 high) to the falling edge of Phi0
|
||||
|
||||
B(8) <= A(8) or not A(11);
|
||||
B(9) <= A(9) or not A(11);
|
||||
B(10) <= A(10) or not A(11);
|
||||
DATA_EN <= RNW and not ndev_sel_int and PHI0;
|
||||
NG <= (ndev_sel_int and noe_int) or not PHI0;
|
||||
NOE <= noe_int or not PHI0;
|
||||
noe_int <= not RNW or not ndev_sel_int
|
||||
or (nio_sel_int and nio_stb_int)
|
||||
or (nio_sel_int and ncs);
|
||||
-- $C0xx to $C7xx is mapped to EEPROM bank 0
|
||||
-- $C8xx to $CExx is mapped to banks 1 to 7
|
||||
|
||||
cfxx <= A(8) and A(9) and A(10) and not nio_stb_int;
|
||||
B(8) <= (a_int(11) and not a_int(8))
|
||||
or (a_int(11) and a_int(10) and a_int(9));
|
||||
B(9) <= (a_int(11) and not a_int(9) and a_int(8))
|
||||
or (a_int(11) and a_int(9) and not a_int(8))
|
||||
or (a_int(11) and a_int(10) and a_int(9));
|
||||
B(10) <= (a_int(11) and a_int(10))
|
||||
or (a_int(11) and a_int(9) and a_int(8));
|
||||
|
||||
DATA_EN <= RNW and not NDEV_SEL;
|
||||
NG <= (ndev_sel_int and nio_sel_int and nio_stb_int)
|
||||
or (ndev_sel_int and nio_sel_int and ncs)
|
||||
or not PHI0;
|
||||
NOE <= not RNW
|
||||
or (not NIO_SEL and not NIO_STB)
|
||||
or (NIO_SEL and NIO_STB)
|
||||
or (NIO_SEL and ncs);
|
||||
NWE <= RNW
|
||||
or (not NIO_SEL and not NIO_STB)
|
||||
or (NIO_SEL and NIO_STB)
|
||||
or (NIO_SEL and ncs)
|
||||
or not PGM_EN;
|
||||
|
||||
cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int;
|
||||
|
||||
process(NRESET, nio_sel_int, cfxx)
|
||||
begin
|
||||
|
|
@ -88,12 +105,12 @@ begin
|
|||
ndev_sel_int <= '1';
|
||||
nio_sel_int <= '1';
|
||||
nio_stb_int <= '1';
|
||||
a_int <= "0000";
|
||||
elsif rising_edge(CLK) then
|
||||
ndev_sel_int <= NDEV_SEL;
|
||||
nio_sel_int <= NIO_SEL;
|
||||
nio_stb_int <= NIO_STB;
|
||||
a_int <= A;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
|
|
|||
|
|
@ -50,9 +50,11 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
|
|||
NIO_SEL : IN std_logic;
|
||||
NIO_STB : IN std_logic;
|
||||
NRESET : IN std_logic;
|
||||
DATA_EN : OUT std_logic;
|
||||
DATA_EN : OUT std_logic;
|
||||
PGM_EN : IN std_logic;
|
||||
NG : OUT std_logic;
|
||||
NOE : OUT std_logic
|
||||
NOE : OUT std_logic;
|
||||
NWE : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
|
@ -65,20 +67,22 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
|
|||
signal NIO_STB : std_logic := '1';
|
||||
signal NRESET : std_logic := '1';
|
||||
signal CLK : std_logic := '0';
|
||||
signal PHI0 : std_logic := '1';
|
||||
signal PHI0 : std_logic := '1';
|
||||
signal PGM_EN : std_logic := '1';
|
||||
|
||||
--Outputs
|
||||
--Outputs
|
||||
signal B : std_logic_vector(10 downto 8);
|
||||
signal DATA_EN : std_logic;
|
||||
signal NG : std_logic;
|
||||
signal NOE : std_logic;
|
||||
signal NWE : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 142 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: AddressDecoder PORT MAP (
|
||||
A => A,
|
||||
B => B,
|
||||
|
|
@ -89,18 +93,20 @@ BEGIN
|
|||
NIO_SEL => NIO_SEL,
|
||||
NIO_STB => NIO_STB,
|
||||
NRESET => NRESET,
|
||||
DATA_EN => DATA_EN,
|
||||
DATA_EN => DATA_EN,
|
||||
PGM_EN => PGM_EN,
|
||||
NG => NG,
|
||||
NOE => NOE
|
||||
NOE => NOE,
|
||||
NWE => NWE
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
PHI0_process :process(CLK)
|
||||
|
|
@ -117,7 +123,7 @@ BEGIN
|
|||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
begin
|
||||
-- hold reset state.
|
||||
wait for CLK_period * 10;
|
||||
NRESET <= '0';
|
||||
|
|
@ -125,60 +131,209 @@ BEGIN
|
|||
NRESET <= '1';
|
||||
wait for CLK_period * 10;
|
||||
|
||||
-- insert stimulus here
|
||||
-- C0nX access
|
||||
A <= "0000"; -- must become "111"
|
||||
-- NG must be '0"
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
A <= "0000"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
|
||||
-- C0nX access, write
|
||||
-- NG must be '0"
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '0';
|
||||
A <= "0000"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CnXX access
|
||||
A <= "0100"; -- must become "111"
|
||||
-- CnXX access, select
|
||||
-- NG must be '0'
|
||||
-- NOE must be '0'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
A <= "0100"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='0') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CnXX access, write, select
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '0'
|
||||
RNW <= '0';
|
||||
A <= "0100"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='0') report "NWE error" severity error;
|
||||
NIO_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CnXX access, write, select, no PGM_EN
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '0';
|
||||
PGM_EN <= '0';
|
||||
A <= "0100"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx access, selected
|
||||
A <= "1000"; -- must become "000"
|
||||
-- NG must be '0'
|
||||
-- NOE must be '0'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
PGM_EN <= '1';
|
||||
A <= "1000"; -- must become "001"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="001") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='0') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx write access, selected
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '0'
|
||||
RNW <= '0';
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='0') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C9xx access, selected
|
||||
A <= "1001"; -- must become "001"
|
||||
-- NG must be '0'
|
||||
-- NOE must be '0'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
A <= "1001"; -- must become "010"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="010") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='0') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C9xx access write, selected
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '0'
|
||||
RNW <= '0';
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='0') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CPLD access
|
||||
A <= "0101"; -- must become "111"
|
||||
-- NG must be '0'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '1';
|
||||
A <= "0101"; -- must become "000"
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="000") report "Address error" severity error;
|
||||
assert (NG='0') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- CFFF access
|
||||
-- NG must be '1'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
A <= "1111"; -- must become "111"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="111") report "Address error" severity error;
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx access, unselected
|
||||
A <= "1000"; -- must become "000"
|
||||
-- NG must be '1'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
A <= "1000"; -- must become "001"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="001") report "Address error" severity error;
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
-- C8xx access write, unselected
|
||||
-- NG must be '1'
|
||||
-- NOE must be '1'
|
||||
-- NWE must be '1'
|
||||
RNW <= '0';
|
||||
A <= "1000"; -- must become "001"
|
||||
wait until rising_edge(PHI0);
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
assert (B="001") report "Address error" severity error;
|
||||
assert (NG='1') report "NG error" severity error;
|
||||
assert (NOE='1') report "NOE error" severity error;
|
||||
assert (NWE='1') report "NWE error" severity error;
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
MODULE AddressDecoder_old
|
||||
|
|
@ -1,275 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<drawing version="7">
|
||||
<attr value="xc9500xl" name="DeviceFamilyName">
|
||||
<trait delete="all:0" />
|
||||
<trait editname="all:0" />
|
||||
<trait edittrait="all:0" />
|
||||
</attr>
|
||||
<netlist>
|
||||
<signal name="A10" />
|
||||
<signal name="A9" />
|
||||
<signal name="A8" />
|
||||
<signal name="XLXN_10" />
|
||||
<signal name="CLK" />
|
||||
<signal name="XLXN_14" />
|
||||
<signal name="B10" />
|
||||
<signal name="B9" />
|
||||
<signal name="B8" />
|
||||
<signal name="NIO_SEL" />
|
||||
<signal name="NIO_STB" />
|
||||
<signal name="XLXN_38" />
|
||||
<signal name="XLXN_46" />
|
||||
<signal name="XLXN_47" />
|
||||
<signal name="NDEV_SEL" />
|
||||
<signal name="NOE" />
|
||||
<signal name="XLXN_53" />
|
||||
<signal name="RNW" />
|
||||
<signal name="XLXN_55" />
|
||||
<port polarity="Input" name="A10" />
|
||||
<port polarity="Input" name="A9" />
|
||||
<port polarity="Input" name="A8" />
|
||||
<port polarity="Input" name="CLK" />
|
||||
<port polarity="Output" name="B10" />
|
||||
<port polarity="Output" name="B9" />
|
||||
<port polarity="Output" name="B8" />
|
||||
<port polarity="Input" name="NIO_SEL" />
|
||||
<port polarity="Input" name="NIO_STB" />
|
||||
<port polarity="Input" name="NDEV_SEL" />
|
||||
<port polarity="Output" name="NOE" />
|
||||
<port polarity="Input" name="RNW" />
|
||||
<blockdef name="fdrs">
|
||||
<timestamp>2001-3-9T11:23:0</timestamp>
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="64" y1="-256" y2="-256" x1="0" />
|
||||
<line x2="320" y1="-256" y2="-256" x1="384" />
|
||||
<line x2="64" y1="-32" y2="-32" x1="0" />
|
||||
<line x2="64" y1="-352" y2="-352" x1="0" />
|
||||
<rect width="256" x="64" y="-320" height="256" />
|
||||
<line x2="192" y1="-64" y2="-32" x1="192" />
|
||||
<line x2="64" y1="-32" y2="-32" x1="192" />
|
||||
<line x2="80" y1="-112" y2="-128" x1="64" />
|
||||
<line x2="64" y1="-128" y2="-144" x1="80" />
|
||||
<line x2="192" y1="-320" y2="-352" x1="192" />
|
||||
<line x2="64" y1="-352" y2="-352" x1="192" />
|
||||
</blockdef>
|
||||
<blockdef name="inv">
|
||||
<timestamp>2001-3-9T11:23:50</timestamp>
|
||||
<line x2="64" y1="-32" y2="-32" x1="0" />
|
||||
<line x2="160" y1="-32" y2="-32" x1="224" />
|
||||
<line x2="128" y1="-64" y2="-32" x1="64" />
|
||||
<line x2="64" y1="-32" y2="0" x1="128" />
|
||||
<line x2="64" y1="0" y2="-64" x1="64" />
|
||||
<circle r="16" cx="144" cy="-32" />
|
||||
</blockdef>
|
||||
<blockdef name="vcc">
|
||||
<timestamp>2001-3-9T11:23:11</timestamp>
|
||||
<line x2="32" y1="-64" y2="-64" x1="96" />
|
||||
<line x2="64" y1="0" y2="-32" x1="64" />
|
||||
<line x2="64" y1="-32" y2="-64" x1="64" />
|
||||
</blockdef>
|
||||
<blockdef name="and2">
|
||||
<timestamp>2001-5-11T10:41:37</timestamp>
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="192" y1="-96" y2="-96" x1="256" />
|
||||
<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
|
||||
<line x2="64" y1="-48" y2="-48" x1="144" />
|
||||
<line x2="144" y1="-144" y2="-144" x1="64" />
|
||||
<line x2="64" y1="-48" y2="-144" x1="64" />
|
||||
</blockdef>
|
||||
<blockdef name="and4">
|
||||
<timestamp>2001-5-11T10:43:14</timestamp>
|
||||
<line x2="64" y1="-112" y2="-112" x1="144" />
|
||||
<arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
|
||||
<line x2="144" y1="-208" y2="-208" x1="64" />
|
||||
<line x2="64" y1="-64" y2="-256" x1="64" />
|
||||
<line x2="192" y1="-160" y2="-160" x1="256" />
|
||||
<line x2="64" y1="-256" y2="-256" x1="0" />
|
||||
<line x2="64" y1="-192" y2="-192" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
</blockdef>
|
||||
<blockdef name="nand2">
|
||||
<timestamp>2001-3-9T11:23:50</timestamp>
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="216" y1="-96" y2="-96" x1="256" />
|
||||
<circle r="12" cx="204" cy="-96" />
|
||||
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|
||||
<line x2="144" y1="-144" y2="-144" x1="64" />
|
||||
<line x2="64" y1="-48" y2="-48" x1="144" />
|
||||
<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
|
||||
</blockdef>
|
||||
<blockdef name="or2">
|
||||
<timestamp>2000-1-1T10:10:10</timestamp>
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="192" y1="-96" y2="-96" x1="256" />
|
||||
<arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
|
||||
<arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
|
||||
<line x2="48" y1="-144" y2="-144" x1="112" />
|
||||
<arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
|
||||
<line x2="48" y1="-48" y2="-48" x1="112" />
|
||||
</blockdef>
|
||||
<block symbolname="fdrs" name="XLXI_16">
|
||||
<blockpin signalname="CLK" name="C" />
|
||||
<blockpin signalname="XLXN_14" name="D" />
|
||||
<blockpin signalname="XLXN_10" name="R" />
|
||||
<blockpin signalname="XLXN_46" name="S" />
|
||||
<blockpin signalname="XLXN_47" name="Q" />
|
||||
</block>
|
||||
<block symbolname="vcc" name="XLXI_17">
|
||||
<blockpin signalname="XLXN_14" name="P" />
|
||||
</block>
|
||||
<block symbolname="and2" name="XLXI_18">
|
||||
<blockpin signalname="A10" name="I0" />
|
||||
<blockpin signalname="XLXN_38" name="I1" />
|
||||
<blockpin signalname="B10" name="O" />
|
||||
</block>
|
||||
<block symbolname="and2" name="XLXI_19">
|
||||
<blockpin signalname="A9" name="I0" />
|
||||
<blockpin signalname="XLXN_38" name="I1" />
|
||||
<blockpin signalname="B9" name="O" />
|
||||
</block>
|
||||
<block symbolname="and2" name="XLXI_20">
|
||||
<blockpin signalname="A8" name="I0" />
|
||||
<blockpin signalname="XLXN_38" name="I1" />
|
||||
<blockpin signalname="B8" name="O" />
|
||||
</block>
|
||||
<block symbolname="inv" name="XLXI_22">
|
||||
<blockpin signalname="NIO_SEL" name="I" />
|
||||
<blockpin signalname="XLXN_46" name="O" />
|
||||
</block>
|
||||
<block symbolname="and4" name="XLXI_30">
|
||||
<blockpin signalname="A8" name="I0" />
|
||||
<blockpin signalname="A9" name="I1" />
|
||||
<blockpin signalname="A10" name="I2" />
|
||||
<blockpin signalname="XLXN_38" name="I3" />
|
||||
<blockpin signalname="XLXN_10" name="O" />
|
||||
</block>
|
||||
<block symbolname="inv" name="XLXI_31">
|
||||
<blockpin signalname="NIO_STB" name="I" />
|
||||
<blockpin signalname="XLXN_38" name="O" />
|
||||
</block>
|
||||
<block symbolname="nand2" name="XLXI_32">
|
||||
<blockpin signalname="XLXN_47" name="I0" />
|
||||
<blockpin signalname="NDEV_SEL" name="I1" />
|
||||
<blockpin signalname="XLXN_55" name="O" />
|
||||
</block>
|
||||
<block symbolname="inv" name="XLXI_33">
|
||||
<blockpin signalname="RNW" name="I" />
|
||||
<blockpin signalname="XLXN_53" name="O" />
|
||||
</block>
|
||||
<block symbolname="or2" name="XLXI_34">
|
||||
<blockpin signalname="XLXN_55" name="I0" />
|
||||
<blockpin signalname="XLXN_53" name="I1" />
|
||||
<blockpin signalname="NOE" name="O" />
|
||||
</block>
|
||||
</netlist>
|
||||
<sheet sheetnum="1" width="3520" height="2720">
|
||||
<branch name="A10">
|
||||
<wire x2="592" y1="704" y2="704" x1="320" />
|
||||
<wire x2="704" y1="704" y2="704" x1="592" />
|
||||
<wire x2="592" y1="704" y2="992" x1="592" />
|
||||
<wire x2="1088" y1="992" y2="992" x1="592" />
|
||||
</branch>
|
||||
<branch name="A9">
|
||||
<wire x2="528" y1="768" y2="768" x1="320" />
|
||||
<wire x2="704" y1="768" y2="768" x1="528" />
|
||||
<wire x2="528" y1="768" y2="1136" x1="528" />
|
||||
<wire x2="1088" y1="1136" y2="1136" x1="528" />
|
||||
</branch>
|
||||
<branch name="A8">
|
||||
<wire x2="464" y1="832" y2="832" x1="320" />
|
||||
<wire x2="704" y1="832" y2="832" x1="464" />
|
||||
<wire x2="464" y1="832" y2="1280" x1="464" />
|
||||
<wire x2="1088" y1="1280" y2="1280" x1="464" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="704" name="A10" orien="R180" />
|
||||
<iomarker fontsize="28" x="320" y="768" name="A9" orien="R180" />
|
||||
<iomarker fontsize="28" x="320" y="832" name="A8" orien="R180" />
|
||||
<branch name="CLK">
|
||||
<wire x2="912" y1="576" y2="576" x1="320" />
|
||||
<wire x2="912" y1="576" y2="640" x1="912" />
|
||||
<wire x2="992" y1="640" y2="640" x1="912" />
|
||||
</branch>
|
||||
<branch name="B10">
|
||||
<wire x2="1664" y1="960" y2="960" x1="1344" />
|
||||
</branch>
|
||||
<branch name="B9">
|
||||
<wire x2="1664" y1="1104" y2="1104" x1="1344" />
|
||||
</branch>
|
||||
<branch name="B8">
|
||||
<wire x2="1664" y1="1248" y2="1248" x1="1344" />
|
||||
</branch>
|
||||
<branch name="NIO_SEL">
|
||||
<wire x2="352" y1="368" y2="368" x1="320" />
|
||||
</branch>
|
||||
<branch name="NIO_STB">
|
||||
<wire x2="336" y1="640" y2="640" x1="320" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="368" name="NIO_SEL" orien="R180" />
|
||||
<iomarker fontsize="28" x="320" y="640" name="NIO_STB" orien="R180" />
|
||||
<instance x="336" y="672" name="XLXI_31" orien="R0" />
|
||||
<branch name="XLXN_38">
|
||||
<wire x2="672" y1="640" y2="640" x1="560" />
|
||||
<wire x2="704" y1="640" y2="640" x1="672" />
|
||||
<wire x2="672" y1="640" y2="928" x1="672" />
|
||||
<wire x2="1088" y1="928" y2="928" x1="672" />
|
||||
<wire x2="672" y1="928" y2="1072" x1="672" />
|
||||
<wire x2="1088" y1="1072" y2="1072" x1="672" />
|
||||
<wire x2="672" y1="1072" y2="1216" x1="672" />
|
||||
<wire x2="1088" y1="1216" y2="1216" x1="672" />
|
||||
</branch>
|
||||
<instance x="704" y="896" name="XLXI_30" orien="R0" />
|
||||
<branch name="XLXN_10">
|
||||
<wire x2="992" y1="736" y2="736" x1="960" />
|
||||
</branch>
|
||||
<branch name="XLXN_14">
|
||||
<wire x2="848" y1="496" y2="512" x1="848" />
|
||||
<wire x2="992" y1="512" y2="512" x1="848" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="576" name="CLK" orien="R180" />
|
||||
<instance x="784" y="496" name="XLXI_17" orien="R0" />
|
||||
<instance x="352" y="400" name="XLXI_22" orien="R0" />
|
||||
<branch name="XLXN_46">
|
||||
<wire x2="992" y1="368" y2="368" x1="576" />
|
||||
<wire x2="992" y1="368" y2="416" x1="992" />
|
||||
</branch>
|
||||
<instance x="992" y="768" name="XLXI_16" orien="R0" />
|
||||
<instance x="1088" y="1056" name="XLXI_18" orien="R0" />
|
||||
<instance x="1088" y="1200" name="XLXI_19" orien="R0" />
|
||||
<instance x="1088" y="1344" name="XLXI_20" orien="R0" />
|
||||
<iomarker fontsize="28" x="1664" y="960" name="B10" orien="R0" />
|
||||
<iomarker fontsize="28" x="1664" y="1104" name="B9" orien="R0" />
|
||||
<iomarker fontsize="28" x="1664" y="1248" name="B8" orien="R0" />
|
||||
<instance x="1424" y="432" name="XLXI_32" orien="R0" />
|
||||
<branch name="XLXN_47">
|
||||
<wire x2="1392" y1="512" y2="512" x1="1376" />
|
||||
<wire x2="1424" y1="368" y2="368" x1="1392" />
|
||||
<wire x2="1392" y1="368" y2="512" x1="1392" />
|
||||
</branch>
|
||||
<branch name="NDEV_SEL">
|
||||
<wire x2="1424" y1="304" y2="304" x1="320" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="304" name="NDEV_SEL" orien="R180" />
|
||||
<instance x="352" y="272" name="XLXI_33" orien="R0" />
|
||||
<branch name="NOE">
|
||||
<wire x2="2016" y1="272" y2="272" x1="2000" />
|
||||
</branch>
|
||||
<branch name="XLXN_53">
|
||||
<wire x2="1744" y1="240" y2="240" x1="576" />
|
||||
</branch>
|
||||
<branch name="RNW">
|
||||
<wire x2="352" y1="240" y2="240" x1="320" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="240" name="RNW" orien="R180" />
|
||||
<instance x="1744" y="368" name="XLXI_34" orien="R0" />
|
||||
<branch name="XLXN_55">
|
||||
<wire x2="1696" y1="336" y2="336" x1="1680" />
|
||||
<wire x2="1744" y1="304" y2="304" x1="1696" />
|
||||
<wire x2="1696" y1="304" y2="336" x1="1696" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="2016" y="272" name="NOE" orien="R0" />
|
||||
</sheet>
|
||||
</drawing>
|
||||
|
|
@ -1,172 +0,0 @@
|
|||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 23:42:22 10/10/2017
|
||||
-- Design Name:
|
||||
-- Module Name: C:/Git/AppleIISd/VHDL/AddressDecoder_Test.vhd
|
||||
-- Project Name: AppleIISd
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: AddressDecoder
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY AddressDecoder_old_Test IS
|
||||
END AddressDecoder_old_Test;
|
||||
|
||||
ARCHITECTURE behavior OF AddressDecoder_old_Test IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT AddressDecoder_old
|
||||
PORT(
|
||||
A8 : IN std_logic;
|
||||
A9 : IN std_logic;
|
||||
A10 : IN std_logic;
|
||||
B8 : OUT std_logic;
|
||||
B9 : OUT std_logic;
|
||||
B10 : OUT std_logic;
|
||||
RNW : IN std_logic;
|
||||
CLK : IN std_logic;
|
||||
NDEV_SEL : IN std_logic;
|
||||
NIO_SEL : IN std_logic;
|
||||
NIO_STB : IN std_logic;
|
||||
NOE : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal A : std_logic_vector(10 downto 8) := "101";
|
||||
signal RNW : std_logic := '1';
|
||||
signal NDEV_SEL : std_logic := '1';
|
||||
signal NIO_SEL : std_logic := '1';
|
||||
signal NIO_STB : std_logic := '1';
|
||||
signal NRESET : std_logic := '1';
|
||||
signal CLK : std_logic := '0';
|
||||
signal PHI0 : std_logic := '1';
|
||||
|
||||
--Outputs
|
||||
signal B : std_logic_vector(10 downto 8);
|
||||
signal DATA_EN : std_logic;
|
||||
signal NG : std_logic;
|
||||
signal NOE : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 142 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: AddressDecoder_old PORT MAP (
|
||||
A8 => A(8),
|
||||
A9 => A(9),
|
||||
A10 => A(10),
|
||||
B8 => B(8),
|
||||
B9 => B(9),
|
||||
B10 => B(10),
|
||||
RNW => RNW,
|
||||
CLK => CLK,
|
||||
NDEV_SEL => NDEV_SEL,
|
||||
NIO_SEL => NIO_SEL,
|
||||
NIO_STB => NIO_STB,
|
||||
NOE => NOE
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
PHI0_process :process(CLK)
|
||||
variable counter : integer range 0 to 7;
|
||||
begin
|
||||
if rising_edge(CLK) or falling_edge(CLK) then
|
||||
counter := counter + 1;
|
||||
if counter = 7 then
|
||||
PHI0 <= not PHI0;
|
||||
counter := 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state.
|
||||
wait for CLK_period * 10;
|
||||
NRESET <= '0';
|
||||
wait for CLK_period * 20;
|
||||
NRESET <= '1';
|
||||
wait for CLK_period * 10;
|
||||
|
||||
-- insert stimulus here
|
||||
-- CPLD access
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
-- CnXX access
|
||||
NIO_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
NIO_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
-- C8xx access, selected
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
-- CPLD access
|
||||
NDEV_SEL <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
-- CFFF access
|
||||
A <= "111";
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
A <= "000";
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
-- C8xx access, unselected
|
||||
NIO_STB <= '0';
|
||||
wait until falling_edge(PHI0);
|
||||
NIO_STB <= '1';
|
||||
wait until rising_edge(PHI0);
|
||||
wait until rising_edge(PHI0);
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
Binary file not shown.
|
|
@ -1,44 +0,0 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
NET "DATA<2>" BUFG = DATA_GATE ;
|
||||
NET "DATA<3>" BUFG = DATA_GATE ;
|
||||
NET "DATA<4>" BUFG = DATA_GATE ;
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADD_HIGH<11>" LOC = "P44" ;
|
||||
NET "ADD_HIGH<10>" LOC = "P38" ;
|
||||
NET "ADD_HIGH<8>" LOC = "P36" ;
|
||||
NET "ADD_HIGH<9>" LOC = "P37" ;
|
||||
NET "ADD_LOW<0>" LOC = "P19" ;
|
||||
NET "ADD_LOW<1>" LOC = "P18" ;
|
||||
NET "B<10>" LOC = "P22" ;
|
||||
NET "B<8>" LOC = "P26" ;
|
||||
NET "B<9>" LOC = "P27" ;
|
||||
NET "CARD" LOC = "P33" ;
|
||||
NET "DATA<0>" LOC = "P3" ;
|
||||
NET "DATA<1>" LOC = "P4" ;
|
||||
NET "DATA<2>" LOC = "P5" ;
|
||||
NET "DATA<3>" LOC = "P6" ;
|
||||
NET "DATA<4>" LOC = "P7" ;
|
||||
NET "DATA<5>" LOC = "P9" ;
|
||||
NET "DATA<6>" LOC = "P11" ;
|
||||
NET "DATA<7>" LOC = "P13" ;
|
||||
NET "CLK" LOC = "P43" ;
|
||||
NET "LED" LOC = "P29" ;
|
||||
NET "NDEV_SEL" LOC = "P24" ;
|
||||
NET "NG" LOC = "P12" ;
|
||||
NET "NIO_SEL" LOC = "P14" ;
|
||||
NET "NIO_STB" LOC = "P42" ;
|
||||
NET "NOE" LOC = "P25" ;
|
||||
NET "PHI0" LOC = "P8" ;
|
||||
NET "NRESET" LOC = "P20" ;
|
||||
NET "RNW" LOC = "P1" ;
|
||||
NET "MISO" LOC = "P40" ;
|
||||
NET "MOSI" LOC = "P35" ;
|
||||
NET "NSEL" LOC = "P28" ;
|
||||
NET "SCLK" LOC = "P34" ;
|
||||
NET "WP" LOC = "P39" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
|
@ -43,6 +43,7 @@ Port (
|
|||
NIO_SEL : in std_logic;
|
||||
NIO_STB : in std_logic;
|
||||
NOE : out std_logic;
|
||||
NWE : out std_logic;
|
||||
PHI0 : in std_logic;
|
||||
NRESET : in std_logic;
|
||||
RNW : in std_logic;
|
||||
|
|
@ -67,11 +68,9 @@ architecture Behavioral of AppleIISd is
|
|||
signal data_in : std_logic_vector (7 downto 0);
|
||||
signal data_out : std_logic_vector (7 downto 0);
|
||||
signal addr_low_int : std_logic_vector (1 downto 0);
|
||||
signal wp_int : std_logic;
|
||||
signal card_int : std_logic;
|
||||
signal miso_int : std_logic;
|
||||
|
||||
signal data_en : std_logic;
|
||||
signal pgm_en : std_logic;
|
||||
|
||||
component SpiController is
|
||||
Port (
|
||||
|
|
@ -89,11 +88,12 @@ Port (
|
|||
nsel : out std_logic;
|
||||
wp : in std_logic;
|
||||
card : in std_logic;
|
||||
led : out std_logic
|
||||
led : out std_logic;
|
||||
pgm_en : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component AddressDecoder
|
||||
component AddressDecoder
|
||||
Port (
|
||||
A : in std_logic_vector (11 downto 8);
|
||||
B : out std_logic_vector (10 downto 8);
|
||||
|
|
@ -105,10 +105,13 @@ Port (
|
|||
NIO_STB : in std_logic;
|
||||
NRESET : in std_logic;
|
||||
DATA_EN : out std_logic;
|
||||
PGM_EN : in std_logic;
|
||||
NG : out std_logic;
|
||||
NOE : out std_logic
|
||||
);
|
||||
end component;
|
||||
NOE : out std_logic;
|
||||
NWE : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
begin
|
||||
spi: SpiController port map(
|
||||
|
|
@ -120,13 +123,14 @@ begin
|
|||
phi0 => PHI0,
|
||||
ndev_sel => NDEV_SEL,
|
||||
clk => CLK,
|
||||
miso => miso_int,
|
||||
miso => MISO,
|
||||
mosi => MOSI,
|
||||
sclk => SCLK,
|
||||
nsel => NSEL,
|
||||
wp => wp_int,
|
||||
card => card_int,
|
||||
led => LED
|
||||
wp => WP,
|
||||
card => CARD,
|
||||
led => LED,
|
||||
pgm_en => pgm_en
|
||||
);
|
||||
|
||||
addDec: AddressDecoder port map(
|
||||
|
|
@ -140,23 +144,12 @@ begin
|
|||
NIO_STB => NIO_STB,
|
||||
NRESET => NRESET,
|
||||
DATA_EN => data_en,
|
||||
PGM_EN => pgm_en,
|
||||
NOE => NOE,
|
||||
NWE => NWE,
|
||||
NG => NG
|
||||
);
|
||||
|
||||
ctrl_latch: process(CLK, NRESET)
|
||||
begin
|
||||
if(NRESET = '0') then
|
||||
wp_int <= '1';
|
||||
card_int <= '1';
|
||||
miso_int <= '1';
|
||||
elsif falling_edge(CLK) then
|
||||
wp_int <= WP;
|
||||
card_int <= CARD;
|
||||
miso_int <= MISO;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
|
||||
|
||||
-- synthesis translate_off
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADD_HIGH<10>" LOC = "P38" ;
|
||||
NET "ADD_HIGH<11>" LOC = "P44" ;
|
||||
NET "ADD_HIGH<8>" LOC = "P36" ;
|
||||
NET "ADD_HIGH<9>" LOC = "P37" ;
|
||||
NET "ADD_LOW<0>" LOC = "P19" ;
|
||||
NET "ADD_LOW<1>" LOC = "P18" ;
|
||||
NET "B<10>" LOC = "P22" ;
|
||||
NET "B<8>" LOC = "P26" ;
|
||||
NET "B<9>" LOC = "P27" ;
|
||||
NET "CARD" LOC = "P33" ;
|
||||
NET "CLK" LOC = "P43" ;
|
||||
NET "DATA<0>" LOC = "P3" ;
|
||||
NET "DATA<1>" LOC = "P4" ;
|
||||
NET "DATA<2>" LOC = "P5" | BUFG = DATA_GATE ;
|
||||
NET "DATA<3>" LOC = "P6" | BUFG = DATA_GATE ;
|
||||
NET "DATA<4>" LOC = "P7" | BUFG = DATA_GATE ;
|
||||
NET "DATA<5>" LOC = "P9" ;
|
||||
NET "DATA<6>" LOC = "P11" ;
|
||||
NET "DATA<7>" LOC = "P13" ;
|
||||
NET "LED" LOC = "P29" ;
|
||||
NET "MISO" LOC = "P40" ;
|
||||
NET "MOSI" LOC = "P35" ;
|
||||
NET "NDEV_SEL" LOC = "P24" ;
|
||||
NET "NG" LOC = "P12" ;
|
||||
NET "NIO_SEL" LOC = "P14" ;
|
||||
NET "NIO_STB" LOC = "P42" ;
|
||||
NET "NOE" LOC = "P25" ;
|
||||
NET "NRESET" LOC = "P20" ;
|
||||
NET "NSEL" LOC = "P28" ;
|
||||
NET "NWE" LOC = "P2" ;
|
||||
NET "PHI0" LOC = "P8" ;
|
||||
NET "RNW" LOC = "P1" ;
|
||||
NET "SCLK" LOC = "P34" ;
|
||||
NET "WP" LOC = "P39" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
|
@ -16,35 +16,28 @@
|
|||
|
||||
<files>
|
||||
<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
|
||||
<file xil_pn:name="AppleIISd_PC44.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder_old.sch" xil_pn:type="FILE_SCHEMATIC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder_old_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="52"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
|
|
@ -159,8 +152,8 @@
|
|||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AppleIISd_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -170,7 +163,7 @@
|
|||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
|
|
@ -184,9 +177,9 @@
|
|||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -205,7 +198,7 @@
|
|||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd_Test|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
|
@ -190,6 +190,25 @@ BEGIN
|
|||
wait for ADD_hold;
|
||||
ADD_LOW <= (others => 'U');
|
||||
|
||||
-- select card
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= (others => '1');
|
||||
RNW <= '0';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait for DATA_valid;
|
||||
DATA <= X"00";
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait for ADD_hold;
|
||||
--wait for CLK_period;
|
||||
ADD_LOW <= (others => 'U');
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'Z');
|
||||
|
||||
-- send data
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
|
|
@ -208,9 +227,28 @@ BEGIN
|
|||
ADD_LOW <= (others => 'U');
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'Z');
|
||||
wait for 20 us;
|
||||
|
||||
-- deselect card
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= (others => '1');
|
||||
RNW <= '0';
|
||||
DATA <= (others => 'U');
|
||||
wait until rising_edge(PHI0);
|
||||
NDEV_SEL <= '0';
|
||||
DATA <= (others => 'Z');
|
||||
wait for DATA_valid;
|
||||
DATA <= X"01";
|
||||
wait until falling_edge(PHI0);
|
||||
NDEV_SEL <= '1';
|
||||
wait for ADD_hold;
|
||||
--wait for CLK_period;
|
||||
ADD_LOW <= (others => 'U');
|
||||
RNW <= '1';
|
||||
DATA <= (others => 'Z');
|
||||
|
||||
-- write ece
|
||||
wait for 20 us;
|
||||
wait until falling_edge(PHI0);
|
||||
wait for ADD_valid;
|
||||
ADD_LOW <= "01";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADD_HIGH<10>" LOC = "P32" ;
|
||||
NET "ADD_HIGH<11>" LOC = "P38" ;
|
||||
NET "ADD_HIGH<8>" LOC = "P30" ;
|
||||
NET "ADD_HIGH<9>" LOC = "P31" ;
|
||||
NET "ADD_LOW<0>" LOC = "P13" ;
|
||||
NET "ADD_LOW<1>" LOC = "P12" ;
|
||||
NET "B<10>" LOC = "P16" ;
|
||||
NET "B<8>" LOC = "P20" ;
|
||||
NET "B<9>" LOC = "P21" ;
|
||||
NET "CARD" LOC = "P27" ;
|
||||
NET "CLK" LOC = "P37" ;
|
||||
NET "DATA<0>" LOC = "P41" ;
|
||||
NET "DATA<1>" LOC = "P42" ;
|
||||
NET "DATA<2>" LOC = "P43" ;
|
||||
NET "DATA<3>" LOC = "P44" ;
|
||||
NET "DATA<4>" LOC = "P1" ;
|
||||
NET "DATA<5>" LOC = "P3" ;
|
||||
NET "DATA<6>" LOC = "P5" ;
|
||||
NET "DATA<7>" LOC = "P7" ;
|
||||
NET "LED" LOC = "P23" ;
|
||||
NET "MISO" LOC = "P34" ;
|
||||
NET "MOSI" LOC = "P29" ;
|
||||
NET "NDEV_SEL" LOC = "P18" ;
|
||||
NET "NG" LOC = "P6" ;
|
||||
NET "NIO_SEL" LOC = "P8" ;
|
||||
NET "NIO_STB" LOC = "P36" ;
|
||||
NET "NOE" LOC = "P19" ;
|
||||
NET "NRESET" LOC = "P14" ;
|
||||
NET "NSEL" LOC = "P22" ;
|
||||
NET "NWE" LOC = "P40" ;
|
||||
NET "PHI0" LOC = "P2" ;
|
||||
NET "RNW" LOC = "P39" ;
|
||||
NET "SCLK" LOC = "P28" ;
|
||||
NET "WP" LOC = "P33" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd_VQ44.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="_" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AppleIISd|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="AppleIISd.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AppleIISd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="VQ44" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="AppleIISd_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="50 us" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="iMPACT Project File" xil_pn:value="AppleIISd_VQ44.ipf" xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-09-03T14:20:38" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="FD3A1F2B88484D658A65860211499755" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -1,32 +1,7 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company: n/a
|
||||
-- Engineer: A. Fachat
|
||||
--
|
||||
-- Create Date: 12:37:11 05/07/2011
|
||||
-- Design Name: SPI65B
|
||||
-- Module Name: SPI6502B - Behavioral
|
||||
-- Project Name: CS/A NETUSB 2.0
|
||||
-- Target Devices: CS/A NETUSB 2.0
|
||||
-- Tool versions:
|
||||
-- Description: An SPI interface for 6502-based computers (or compatible).
|
||||
-- modelled after the SPI65 interface by Daryl Rictor
|
||||
-- (see http://sbc.rictor.org/io/65spi.html )
|
||||
-- This implementation here, however, is a complete reimplementation
|
||||
-- as the ABEL language of the original implementation is not supported
|
||||
-- by ISE anymore.
|
||||
-- Also I added the interrupt input handling, replacing four of the
|
||||
-- original SPI select outputs with four interrupt inputs
|
||||
-- Also folded out the single MISO input into one input for each of the
|
||||
-- four supported devices, reducing external parts count again by one.
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Revision 0.02 - removed spiclk and replaced with clksrc and clkcnt_is_zero combination,
|
||||
-- to drive up SPI clock to half of input clock (and not one fourth only as before)
|
||||
-- unfortunately that costed one divisor bit to fit into the CPLD
|
||||
-- Additional Comments:
|
||||
-- Spi controller for 6502 systems
|
||||
-- based on a design by A. Fachat
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
|
|
@ -49,12 +24,10 @@ Port (
|
|||
sclk : out STD_LOGIC;
|
||||
nsel : out STD_LOGIC;
|
||||
wp : in STD_LOGIC;
|
||||
card : in STD_LOGIC;
|
||||
card : in STD_LOGIC;
|
||||
pgm_en : out STD_LOGIC;
|
||||
led : out STD_LOGIC
|
||||
);
|
||||
|
||||
constant DIV_WIDTH : integer := 3;
|
||||
|
||||
end SpiController;
|
||||
|
||||
architecture Behavioral of SpiController is
|
||||
|
|
@ -63,7 +36,9 @@ architecture Behavioral of SpiController is
|
|||
-- internal state
|
||||
signal spidatain: std_logic_vector (7 downto 0);
|
||||
signal spidataout: std_logic_vector (7 downto 0);
|
||||
signal inited: std_logic; -- card initialized
|
||||
signal sdhc: std_logic; -- is SDHC card
|
||||
signal inited: std_logic; -- card initialized
|
||||
signal pgmen: std_logic; -- enable EEPROM programming
|
||||
|
||||
-- spi register flags
|
||||
signal tc: std_logic; -- transmission complete; cleared on spi data read
|
||||
|
|
@ -71,7 +46,6 @@ architecture Behavioral of SpiController is
|
|||
signal frx: std_logic; -- fast receive mode
|
||||
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
|
||||
|
||||
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
|
||||
signal slavesel: std_logic := '1'; -- slave select output (0=selected)
|
||||
signal int_miso: std_logic;
|
||||
--------------------------
|
||||
|
|
@ -85,12 +59,9 @@ architecture Behavioral of SpiController is
|
|||
|
||||
-- spi clock
|
||||
signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
|
||||
-- TODO divcnt is not used at all??
|
||||
--signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
|
||||
signal shiftclk : std_logic;
|
||||
|
||||
begin
|
||||
--led <= not (inited);
|
||||
led <= not (bsy or not slavesel);
|
||||
bsy <= start_shifting or shifting2;
|
||||
|
||||
|
|
@ -149,13 +120,13 @@ begin
|
|||
begin
|
||||
if (nreset = '0') then
|
||||
mosi <= '1';
|
||||
sclk <= '0';
|
||||
sclk <= '1';
|
||||
else
|
||||
-- clock is sync'd
|
||||
if (rising_edge(shiftclk)) then
|
||||
if (shifting2='0' or shiftdone = '1') then
|
||||
mosi <= '1';
|
||||
sclk <= '0';
|
||||
sclk <= '1';
|
||||
else
|
||||
-- output data directly from output register
|
||||
case shiftcnt(3 downto 1) is
|
||||
|
|
@ -169,7 +140,7 @@ begin
|
|||
when "111" => mosi <= spidataout(0);
|
||||
when others => mosi <= '1';
|
||||
end case;
|
||||
sclk <= '0' xor '0' xor shiftcnt(0);
|
||||
sclk <= shiftcnt(0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
|
@ -195,29 +166,16 @@ begin
|
|||
clksrc <= phi0 when (ece = '0') else clk;
|
||||
|
||||
-- is a pulse signal to allow for divisor==0
|
||||
--shiftclk <= clksrc when divcnt = "000000" else '0';
|
||||
shiftclk <= clksrc when bsy = '1' else '0';
|
||||
|
||||
-- clkgen: process(nreset, divisor, clksrc)
|
||||
-- begin
|
||||
-- if (nreset = '0') then
|
||||
-- divcnt <= divisor;
|
||||
-- elsif (falling_edge(clksrc)) then
|
||||
-- if (shiftclk = '1') then
|
||||
-- divcnt <= divisor;
|
||||
-- else
|
||||
-- divcnt <= divcnt - 1;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
--------------------------
|
||||
-- interface section
|
||||
-- inputs
|
||||
int_miso <= (miso and not slavesel);
|
||||
|
||||
-- outputs
|
||||
nsel <= slavesel;
|
||||
nsel <= slavesel;
|
||||
pgm_en <= pgmen;
|
||||
|
||||
tc_proc: process (ndev_sel, shiftdone)
|
||||
begin
|
||||
|
|
@ -231,27 +189,26 @@ begin
|
|||
--------------------------
|
||||
-- cpu register section
|
||||
-- cpu read
|
||||
cpu_read: process(addr, spidatain, tc, bsy, frx,
|
||||
ece, divisor, slavesel, wp, card, inited)
|
||||
cpu_read: process(addr, spidatain, tc, bsy, frx, pgmen,
|
||||
ece, slavesel, wp, card, sdhc, inited)
|
||||
begin
|
||||
case addr is
|
||||
when "00" => -- read SPI data in
|
||||
data_out <= spidatain;
|
||||
when "01" => -- read status register
|
||||
data_out(0) <= '0';
|
||||
data_out(0) <= pgmen;
|
||||
data_out(1) <= '0';
|
||||
data_out(2) <= ece;
|
||||
data_out(3) <= '0';
|
||||
data_out(4) <= frx;
|
||||
data_out(5) <= bsy;
|
||||
data_out(6) <= '0';
|
||||
data_out(7) <= tc;
|
||||
when "10" => -- read sclk divisor
|
||||
data_out(DIV_WIDTH-1 downto 0) <= divisor;
|
||||
data_out(7 downto 3) <= (others => '0');
|
||||
data_out(7) <= tc;
|
||||
-- no register 2
|
||||
when "11" => -- read slave select / slave interrupt state
|
||||
data_out(0) <= slavesel;
|
||||
data_out(4 downto 1) <= (others => '0');
|
||||
data_out(3 downto 1) <= (others => '0');
|
||||
data_out(4) <= sdhc;
|
||||
data_out(5) <= wp;
|
||||
data_out(6) <= card;
|
||||
data_out(7) <= inited;
|
||||
|
|
@ -261,30 +218,34 @@ begin
|
|||
end process;
|
||||
|
||||
-- cpu write
|
||||
cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card, inited)
|
||||
cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card)
|
||||
begin
|
||||
if (nreset = '0') then
|
||||
ece <= '0';
|
||||
frx <= '0';
|
||||
slavesel <= '1';
|
||||
divisor <= (others => '0');
|
||||
spidataout <= (others => '1');
|
||||
inited <= '0';
|
||||
sdhc <= '0';
|
||||
inited <= '0';
|
||||
pgmen <= '0';
|
||||
elsif (card = '1') then
|
||||
sdhc <= '0';
|
||||
inited <= '0';
|
||||
elsif (rising_edge(ndev_sel) and is_read = '0') then
|
||||
case addr is
|
||||
when "00" => -- write SPI data out (see other process above)
|
||||
spidataout <= data_in;
|
||||
when "01" => -- write status register
|
||||
when "01" => -- write status register
|
||||
pgmen <= data_in(0);
|
||||
ece <= data_in(2);
|
||||
frx <= data_in(4);
|
||||
-- no bit 5 - 7
|
||||
when "10" => -- write divisor
|
||||
divisor <= data_in(DIV_WIDTH-1 downto 0);
|
||||
when "11" => -- write slave select / slave interrupt enable
|
||||
-- no bit 5 - 7
|
||||
-- no register 2
|
||||
when "11" => -- write slave select
|
||||
slavesel <= data_in(0);
|
||||
-- no bit 1 - 6
|
||||
-- no bit 1 - 3
|
||||
sdhc <= data_in(4);
|
||||
-- no bit 5 - 6
|
||||
inited <= data_in(7);
|
||||
when others =>
|
||||
end case;
|
||||
|
|
@ -292,4 +253,3 @@ begin
|
|||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,42 +0,0 @@
|
|||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "a10" LOC = "P38" ;
|
||||
NET "a8" LOC = "P36" ;
|
||||
NET "a9" LOC = "P37" ;
|
||||
NET "addr<0>" LOC = "P19" ;
|
||||
NET "addr<1>" LOC = "P18" ;
|
||||
NET "b10" LOC = "P22" ;
|
||||
NET "b8" LOC = "P26" ;
|
||||
NET "b9" LOC = "P27" ;
|
||||
NET "card" LOC = "P33" ;
|
||||
NET "data<0>" LOC = "P3" ;
|
||||
NET "data<1>" LOC = "P5" ;
|
||||
NET "data<2>" LOC = "P4" ;
|
||||
NET "data<3>" LOC = "P6" ;
|
||||
NET "data<4>" LOC = "P7" ;
|
||||
NET "data<5>" LOC = "P9" ;
|
||||
NET "data<6>" LOC = "P11" ;
|
||||
NET "data<7>" LOC = "P13" ;
|
||||
NET "extclk" LOC = "P42" ;
|
||||
NET "led" LOC = "P29" ;
|
||||
NET "ndev_sel" LOC = "P24" ;
|
||||
NET "ng" LOC = "P12" ;
|
||||
NET "nio_sel" LOC = "P14" ;
|
||||
NET "nio_stb" LOC = "P40" ;
|
||||
NET "nirq" LOC = "P2" ;
|
||||
NET "noe" LOC = "P25" ;
|
||||
NET "nphi2" LOC = "P44" ;
|
||||
NET "nreset" LOC = "P20" ;
|
||||
NET "nrw" LOC = "P1" ;
|
||||
NET "spi_miso" LOC = "P43" ;
|
||||
NET "spi_mosi" LOC = "P35" ;
|
||||
NET "spi_Nsel" LOC = "P28" ;
|
||||
NET "spi_sclk" LOC = "P34" ;
|
||||
NET "wp" LOC = "P39" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
Loading…
Reference in New Issue