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Added glitch filter on ACK line, registered all outputs, double-synced inputs, and fixed parity checks.

This commit is contained in:
Michael McMaster 2014-08-28 23:28:09 +10:00
parent f45769aed5
commit 7db82a4e4a
47 changed files with 6018 additions and 3499 deletions
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6
CHANGELOG
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@ -1,5 +1,9 @@
201407XX 3.6 201408XX 3.6
- Fix handling requests for LUNs other than 0 from SCSI-2 hosts. - Fix handling requests for LUNs other than 0 from SCSI-2 hosts.
- Handle glitches of the ACK line to improve stability and operate with
multiple devices on the SCSI bus.
- Re-add parity checking. This can be disabled using scsi2sd-config if
required.
20140718 3.5.2 20140718 3.5.2
- Fix blank SCSI ID in scsi2sd-config output. - Fix blank SCSI ID in scsi2sd-config output.

2
STATUS
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@ -1,2 +1,2 @@
- Parity checking not implemented for the PSoC Datapath implementation - Everything works. If it doesn't, please report the bug to michael@codesrc.com

2
readme.txt
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@ -70,6 +70,7 @@ Compatibility
Apple IIgs using Apple II High Speed SCSI controller card (from v3.3) Apple IIgs using Apple II High Speed SCSI controller card (from v3.3)
Symbolics Lisp Machine XL1200, using 1280 byte sectors (from v3.4) Symbolics Lisp Machine XL1200, using 1280 byte sectors (from v3.4)
PDP-11/73 running RSX11M+ V4.6 PDP-11/73 running RSX11M+ V4.6
Microvax 3100 Model 80 running VMS 7.3 (needs patch against v3.5.2 firmware)
Amiga 500+ with GVP A530 Amiga 500+ with GVP A530
Atari TT030 System V Atari TT030 System V
@ -88,6 +89,7 @@ Samplers
Casio FZ-20M Casio FZ-20M
Requires TERMPWR jumper. The manual shows the pin25 of the DB25 connector is "not connected". Requires TERMPWR jumper. The manual shows the pin25 of the DB25 connector is "not connected".
May require scsi2sd-config --apple flag May require scsi2sd-config --apple flag
Yamaha EX5R
Other Other

6
software/SCSI2SD/src/disk.c
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@ -563,6 +563,12 @@ void scsiDiskPoll()
if (scsiDev.phase == DATA_OUT) if (scsiDev.phase == DATA_OUT)
{ {
if (scsiDev.parityError)
{
scsiDev.sense.code = ABORTED_COMMAND;
scsiDev.sense.asc = SCSI_PARITY_ERROR;
scsiDev.status = CHECK_CONDITION;;
}
scsiDev.phase = STATUS; scsiDev.phase = STATUS;
} }
scsiDiskReset(); scsiDiskReset();

3
software/SCSI2SD/src/scsi.c
View File

@ -197,8 +197,7 @@ static void process_DataOut()
scsiRead(scsiDev.data + scsiDev.dataPtr, len); scsiRead(scsiDev.data + scsiDev.dataPtr, len);
scsiDev.dataPtr += len; scsiDev.dataPtr += len;
// TODO re-implement parity checking if (scsiDev.parityError && config->enableParity)
if (0 && scsiDev.parityError && config->enableParity)
{ {
scsiDev.sense.code = ABORTED_COMMAND; scsiDev.sense.code = ABORTED_COMMAND;
scsiDev.sense.asc = SCSI_PARITY_ERROR; scsiDev.sense.asc = SCSI_PARITY_ERROR;

18
software/SCSI2SD/src/scsiPhy.c
View File

@ -86,8 +86,9 @@ scsiReadByte(void)
while (scsiPhyRxFifoEmpty() && !scsiDev.resetFlag) {} while (scsiPhyRxFifoEmpty() && !scsiDev.resetFlag) {}
uint8_t val = scsiPhyRx(); uint8_t val = scsiPhyRx();
scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}
return val; return val;
} }
@ -113,7 +114,8 @@ scsiReadPIO(uint8* data, uint32 count)
++i; ++i;
} }
} }
while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}
} }
static void static void
@ -182,7 +184,7 @@ scsiReadDMAPoll()
if (dmaSentCount == dmaTotalCount) if (dmaSentCount == dmaTotalCount)
{ {
dmaInProgress = 0; dmaInProgress = 0;
while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
return 1; return 1;
} }
else else
@ -224,8 +226,6 @@ scsiWriteByte(uint8 value)
while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {} while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}
scsiPhyRxFifoClear(); scsiPhyRxFifoClear();
while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}
} }
static void static void
@ -271,6 +271,7 @@ doTxSingleDMA(uint8* data, uint32 count)
CyDmaClearPendingDrq(scsiDmaTxChan); CyDmaClearPendingDrq(scsiDmaTxChan);
txDMAComplete = 0; txDMAComplete = 0;
rxDMAComplete = 1;
CyDmaChEnable(scsiDmaTxChan, 1); CyDmaChEnable(scsiDmaTxChan, 1);
} }
@ -296,7 +297,6 @@ scsiWriteDMAPoll()
{ {
scsiPhyRxFifoClear(); scsiPhyRxFifoClear();
dmaInProgress = 0; dmaInProgress = 0;
while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}
return 1; return 1;
} }
else else
@ -383,6 +383,8 @@ void scsiPhyReset()
// Allow the FIFOs to fill up again. // Allow the FIFOs to fill up again.
SCSI_ClearPin(SCSI_Out_RST); SCSI_ClearPin(SCSI_Out_RST);
scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03); scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03);
SCSI_Parity_Error_Read(); // clear sticky bits
} }
static void scsiPhyInitDMA() static void scsiPhyInitDMA()
@ -397,7 +399,7 @@ static void scsiPhyInitDMA()
HI16(CYDEV_PERIPH_BASE), HI16(CYDEV_PERIPH_BASE),
HI16(CYDEV_SRAM_BASE) HI16(CYDEV_SRAM_BASE)
); );
scsiDmaTxChan = scsiDmaTxChan =
SCSI_TX_DMA_DmaInitialize( SCSI_TX_DMA_DmaInitialize(
1, // Bytes per burst 1, // Bytes per burst
@ -411,7 +413,7 @@ static void scsiPhyInitDMA()
scsiDmaRxTd[0] = CyDmaTdAllocate(); scsiDmaRxTd[0] = CyDmaTdAllocate();
scsiDmaTxTd[0] = CyDmaTdAllocate(); scsiDmaTxTd[0] = CyDmaTdAllocate();
SCSI_RX_DMA_COMPLETE_StartEx(scsiRxCompleteISR); SCSI_RX_DMA_COMPLETE_StartEx(scsiRxCompleteISR);
SCSI_TX_DMA_COMPLETE_StartEx(scsiTxCompleteISR); SCSI_TX_DMA_COMPLETE_StartEx(scsiTxCompleteISR);
} }

134
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c Normal file
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@ -0,0 +1,134 @@
/*******************************************************************************
* File Name: SCSI_Parity_Error.c
* Version 1.80
*
* Description:
* This file contains API to enable firmware to read the value of a Status
* Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Parity_Error.h"
#if !defined(SCSI_Parity_Error_sts_sts_reg__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Function Name: SCSI_Parity_Error_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Status Register.
*
* Parameters:
* None.
*
* Return:
* The current value in the Status Register.
*
*******************************************************************************/
uint8 SCSI_Parity_Error_Read(void)
{
return SCSI_Parity_Error_Status;
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_InterruptEnable
********************************************************************************
*
* Summary:
* Enables the Status Register interrupt.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Parity_Error_InterruptEnable(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
SCSI_Parity_Error_Status_Aux_Ctrl |= SCSI_Parity_Error_STATUS_INTR_ENBL;
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_InterruptDisable
********************************************************************************
*
* Summary:
* Disables the Status Register interrupt.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Parity_Error_InterruptDisable(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
SCSI_Parity_Error_Status_Aux_Ctrl &= (uint8)(~SCSI_Parity_Error_STATUS_INTR_ENBL);
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_WriteMask
********************************************************************************
*
* Summary:
* Writes the current mask value assigned to the Status Register.
*
* Parameters:
* mask: Value to write into the mask register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Parity_Error_WriteMask(uint8 mask)
{
#if(SCSI_Parity_Error_INPUTS < 8u)
mask &= (uint8)((((uint8)1u) << SCSI_Parity_Error_INPUTS) - 1u);
#endif /* End SCSI_Parity_Error_INPUTS < 8u */
SCSI_Parity_Error_Status_Mask = mask;
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_ReadMask
********************************************************************************
*
* Summary:
* Reads the current interrupt mask assigned to the Status Register.
*
* Parameters:
* None.
*
* Return:
* The value of the interrupt mask of the Status Register.
*
*******************************************************************************/
uint8 SCSI_Parity_Error_ReadMask(void)
{
return SCSI_Parity_Error_Status_Mask;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

63
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h Normal file
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@ -0,0 +1,63 @@
/*******************************************************************************
* File Name: SCSI_Parity_Error.h
* Version 1.80
*
* Description:
* This file containts Status Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */
#define CY_STATUS_REG_SCSI_Parity_Error_H
#include "cytypes.h"
#include "CyLib.h"
/***************************************
* Function Prototypes
***************************************/
uint8 SCSI_Parity_Error_Read(void) ;
void SCSI_Parity_Error_InterruptEnable(void) ;
void SCSI_Parity_Error_InterruptDisable(void) ;
void SCSI_Parity_Error_WriteMask(uint8 mask) ;
uint8 SCSI_Parity_Error_ReadMask(void) ;
/***************************************
* API Constants
***************************************/
#define SCSI_Parity_Error_STATUS_INTR_ENBL 0x10u
/***************************************
* Parameter Constants
***************************************/
/* Status Register Inputs */
#define SCSI_Parity_Error_INPUTS 1
/***************************************
* Registers
***************************************/
/* Status Register */
#define SCSI_Parity_Error_Status (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
#define SCSI_Parity_Error_Status_PTR ( (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
#define SCSI_Parity_Error_Status_Mask (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__MASK_REG )
#define SCSI_Parity_Error_Status_Aux_Ctrl (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG )
#endif /* End CY_STATUS_REG_SCSI_Parity_Error_H */
/* [] END OF FILE */

276
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
View File

@ -71,6 +71,16 @@
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST
/* USBFS_bus_reset */ /* USBFS_bus_reset */
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 #define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
@ -84,41 +94,41 @@
/* SCSI_CTL_PHASE */ /* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
/* SCSI_Out_Bits */ /* SCSI_Out_Bits */
#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
@ -133,15 +143,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
/* USBFS_arb_int */ /* USBFS_arb_int */
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -166,24 +176,24 @@
/* SCSI_Out_Ctl */ /* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL #define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK #define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL #define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
/* SCSI_Out_DBx */ /* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
@ -656,8 +666,8 @@
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL #define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK #define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL #define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@ -665,17 +675,13 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u #define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK #define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB05_MSK
#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL #define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL #define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB05_ST
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL #define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST #define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1 #define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
@ -685,28 +691,26 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK #define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL #define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST #define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB05_06_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB05_06_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB05_06_D0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB05_06_D1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL #define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB05_06_F0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB05_06_F1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1
#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB05_A0_A1 #define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1
#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB05_A0 #define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0
#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB05_A1 #define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1
#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB05_D0_D1 #define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1
#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB05_D0 #define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0
#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB05_D1 #define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1
#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL #define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB05_F0_F1 #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB05_F0 #define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB05_F1 #define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1
#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
/* USBFS_dp_int */ /* USBFS_dp_int */
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -1199,8 +1203,8 @@
/* scsiTarget */ /* scsiTarget */
#define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__MASK 0x01u
#define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL #define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST #define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__MASK 0x04u
@ -1210,54 +1214,58 @@
#define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu #define scsiTarget_StatusReg__MASK 0x1Fu
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK #define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL #define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST #define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL #define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST #define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK #define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL #define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST
#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL #define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL #define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL #define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB04_MSK
#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL #define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST #define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL #define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL #define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL #define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL #define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB04_ST
#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL #define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK #define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK #define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK #define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK #define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL #define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL #define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL #define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL #define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL #define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL #define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB04_CTL
#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK #define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL #define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB04_CTL
#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0 #define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1 #define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0 #define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB04_MSK
#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1 #define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL #define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB04_05_A0
#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0 #define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB04_05_A1
#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1 #define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB04_05_D0
#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1 #define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB04_05_D1
#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0 #define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1 #define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB04_05_F0
#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1 #define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB04_05_F1
#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0 #define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB04_A0_A1
#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1 #define scsiTarget_datapath__A0_REG CYREG_B0_UDB04_A0
#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL #define scsiTarget_datapath__A1_REG CYREG_B0_UDB04_A1
#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1 #define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB04_D0_D1
#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0 #define scsiTarget_datapath__D0_REG CYREG_B0_UDB04_D0
#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1 #define scsiTarget_datapath__D1_REG CYREG_B0_UDB04_D1
#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL #define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL #define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB04_F0_F1
#define scsiTarget_datapath__F0_REG CYREG_B0_UDB04_F0
#define scsiTarget_datapath__F1_REG CYREG_B0_UDB04_F1
#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
/* USBFS_ep_0 */ /* USBFS_ep_0 */
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0

2497
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
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File diff suppressed because it is too large Load Diff

276
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
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@ -71,6 +71,16 @@
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB10_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB10_ST
/* USBFS_bus_reset */ /* USBFS_bus_reset */
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 .set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
@ -84,41 +94,41 @@
/* SCSI_CTL_PHASE */ /* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
/* SCSI_Out_Bits */ /* SCSI_Out_Bits */
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
@ -133,15 +143,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
/* USBFS_arb_int */ /* USBFS_arb_int */
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -166,24 +176,24 @@
/* SCSI_Out_Ctl */ /* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL .set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK .set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL .set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
/* SCSI_Out_DBx */ /* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
@ -656,8 +666,8 @@
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL .set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK .set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL .set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@ -665,17 +675,13 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70 .set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK .set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB05_MSK
.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL .set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL .set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB05_ST
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL .set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST .set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1 .set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
@ -685,28 +691,26 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F .set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK .set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL .set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST .set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB05_06_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB05_06_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB05_06_D0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB05_06_D1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL .set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB05_06_F0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB05_06_F1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1
.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB05_A0_A1 .set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1
.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB05_A0 .set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0
.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB05_A1 .set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1
.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB05_D0_D1 .set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1
.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB05_D0 .set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0
.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB05_D1 .set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1
.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL .set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB05_F0_F1 .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB05_F0 .set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB05_F1 .set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1
.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
/* USBFS_dp_int */ /* USBFS_dp_int */
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -1199,8 +1203,8 @@
/* scsiTarget */ /* scsiTarget */
.set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__MASK, 0x01
.set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL .set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST .set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__MASK, 0x04
@ -1210,54 +1214,58 @@
.set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F .set scsiTarget_StatusReg__MASK, 0x1F
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB00_MSK .set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL .set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB00_ST .set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL .set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST .set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK .set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL .set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST
.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL .set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL .set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL .set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB04_MSK
.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL .set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST .set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL .set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL .set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL
.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL .set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL
.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL .set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB04_ST
.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL .set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK .set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK .set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK .set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK .set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL .set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL .set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL .set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL .set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL .set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL .set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB04_CTL
.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK .set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL .set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB04_CTL
.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0 .set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1 .set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0 .set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB04_MSK
.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1 .set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL .set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB04_05_A0
.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0 .set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB04_05_A1
.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1 .set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB04_05_D0
.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1 .set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB04_05_D1
.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0 .set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1 .set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB04_05_F0
.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1 .set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB04_05_F1
.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0 .set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB04_A0_A1
.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1 .set scsiTarget_datapath__A0_REG, CYREG_B0_UDB04_A0
.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL .set scsiTarget_datapath__A1_REG, CYREG_B0_UDB04_A1
.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1 .set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB04_D0_D1
.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0 .set scsiTarget_datapath__D0_REG, CYREG_B0_UDB04_D0
.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1 .set scsiTarget_datapath__D1_REG, CYREG_B0_UDB04_D1
.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL .set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL .set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB04_F0_F1
.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB04_F0
.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB04_F1
.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
/* USBFS_ep_0 */ /* USBFS_ep_0 */
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0

276
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
View File

@ -71,6 +71,16 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST
/* USBFS_bus_reset */ /* USBFS_bus_reset */
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@ -84,41 +94,41 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_CTL_PHASE */ /* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
/* SCSI_Out_Bits */ /* SCSI_Out_Bits */
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
@ -133,15 +143,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
/* USBFS_arb_int */ /* USBFS_arb_int */
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -166,24 +176,24 @@ USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_Out_Ctl */ /* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
/* SCSI_Out_DBx */ /* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@ -656,8 +666,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -665,17 +675,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@ -685,28 +691,26 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0 SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1 SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1 SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0 SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1 SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1 SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0 SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1 SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
/* USBFS_dp_int */ /* USBFS_dp_int */
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -1199,8 +1203,8 @@ timer_clock__PM_STBY_MSK EQU 0x04
/* scsiTarget */ /* scsiTarget */
scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__MASK EQU 0x04
@ -1210,54 +1214,58 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
/* USBFS_ep_0 */ /* USBFS_ep_0 */
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0

276
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
View File

@ -71,6 +71,16 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST
; USBFS_bus_reset ; USBFS_bus_reset
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@ -84,41 +94,41 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_CTL_PHASE ; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
; SCSI_Out_Bits ; SCSI_Out_Bits
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
@ -133,15 +143,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
; USBFS_arb_int ; USBFS_arb_int
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -166,24 +176,24 @@ USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_Out_Ctl ; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
; SCSI_Out_DBx ; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@ -656,8 +666,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -665,17 +675,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@ -685,28 +691,26 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0 SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1 SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1 SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0 SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1 SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1 SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0 SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1 SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
; USBFS_dp_int ; USBFS_dp_int
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -1199,8 +1203,8 @@ timer_clock__PM_STBY_MSK EQU 0x04
; scsiTarget ; scsiTarget
scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__MASK EQU 0x04
@ -1210,54 +1214,58 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
; USBFS_ep_0 ; USBFS_ep_0
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0

2
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
View File

@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used))
const uint8 cy_meta_loadable[] = { const uint8 cy_meta_loadable[] = {
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x52u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x03u,
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,

1
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
View File

@ -70,6 +70,7 @@
#include <SD_TX_DMA_COMPLETE.h> #include <SD_TX_DMA_COMPLETE.h>
#include <SCSI_RX_DMA_dma.h> #include <SCSI_RX_DMA_dma.h>
#include <SCSI_RX_DMA_COMPLETE.h> #include <SCSI_RX_DMA_COMPLETE.h>
#include <SCSI_Parity_Error.h>
#include <USBFS_Dm_aliases.h> #include <USBFS_Dm_aliases.h>
#include <USBFS_Dm.h> #include <USBFS_Dm.h>
#include <USBFS_Dp_aliases.h> #include <USBFS_Dp_aliases.h>

253
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml Executable file
View File

@ -0,0 +1,253 @@
<?xml version="1.0" encoding="utf-8"?>
<!--DO NOT EDIT. This document is generated by PSoC Creator design builds.-->
<PSoCCreatorIdeExport Version="1">
<Device Part="CY8C5267AXI-LP051" Processor="CortexM3" DeviceID="2E133069" />
<Toolchains>
<Toolchain Name="ARM GCC" Selected="True">
<Tool Name="prebuild" Command="" Options="" />
<Tool Name="assembler" Command="arm-none-eabi-as.exe" Options="-I. -I./Generated_Source/PSoC5 -mcpu=cortex-m3 -mthumb -g -alh=${OutputDir}/${CompileFile}.lst " />
<Tool Name="compiler" Command="arm-none-eabi-gcc.exe" Options="-I. -I./Generated_Source/PSoC5 -Wno-main -mcpu=cortex-m3 -mthumb -Wall -g -D NDEBUG -Wa,-alh=${OutputDir}\${CompileFile}.lst -Os -ffunction-sections " />
<Tool Name="linker" Command="arm-none-eabi-gcc.exe" Options="-mthumb -march=armv7-m -mfix-cortex-m3-ldrd -T .\Generated_Source\PSoC5\cm3gcc.ld -g -Wl,-Map,${OutputDir}\${ProjectShortName}.map -specs=nano.specs -Wl,--gc-sections " />
<Tool Name="postbuild" Command="" Options="" />
</Toolchain>
<Toolchain Name="ARM Keil MDK" Selected="False">
<Tool Name="prebuild" Command="" Options="" />
<Tool Name="assembler" Command="armasm.exe" Options="-i. -iGenerated_Source/PSoC5 --diag_style=gnu --thumb --cpu=Cortex-M3 -g --list=${OutputDir}/${CompileFile}.lst " />
<Tool Name="compiler" Command="armcc.exe" Options="-I. -I./Generated_Source/PSoC5 --diag_suppress=951 --diag_style=gnu --cpu=Cortex-M3 -g -D NDEBUG --signed_chars --list -Ospace --split_sections " />
<Tool Name="linker" Command="armlink.exe" Options="--diag_style=gnu --no_startup --cpu=Cortex-M3 --scatter .\Generated_Source\PSoC5\Cm3RealView.scat --map --list ${OutputDir}\${ProjectShortName}.map " />
<Tool Name="postbuild" Command="" Options="" />
</Toolchain>
</Toolchains>
<Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
<CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
<Datasheet />
<LinkerFiles>
<LinkerFile Toolchain="ARM GCC">.\Generated_Source\PSoC5\cm3gcc.ld</LinkerFile>
<LinkerFile Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\Cm3RealView.scat</LinkerFile>
<LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
</LinkerFiles>
<Folders>
<Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\src">
<Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">..\..\src\main.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\disk.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\geometry.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\inquiry.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\mode.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\scsi.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\scsiPhy.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\bits.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\sd.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\config.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\led.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\disk.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\geometry.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\inquiry.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\led.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\mode.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\scsi.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\scsiPhy.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\sense.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\bits.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\sd.h</File>
<File BuildType="BUILD" Toolchain="">..\..\src\config.h</File>
</Files>
</Folder>
<Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
<Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">.\device.h</File>
</Files>
</Folder>
<Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5">
<Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
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</PSoCCreatorIdeExport>

66
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
View File

@ -1,12 +1,11 @@
<?xml version="1.0" encoding="utf-8"?> <?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap"> <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true"> <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006577" bitWidth="8" desc="" /> <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" />
</block> </block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true"> <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" /> <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
</block> </block>
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true"> <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@ -64,7 +63,8 @@
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" /> <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" /> <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
</block> </block>
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true"> <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@ -73,7 +73,6 @@
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
</block> </block>
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true"> <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@ -154,36 +153,67 @@
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" /> <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" /> <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
</block> </block>
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646A" bitWidth="8" desc="" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x4000648A" bitWidth="8" desc="" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649A" bitWidth="8" desc="">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
<value name="ENABLED" value="1" desc="Interrupt enabled" />
<value name="DISABLED" value="0" desc="Interrupt disabled" />
</field>
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
</register>
</block>
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true"> <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" /> <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />
</block> </block>
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
</blockRegMap> </blockRegMap>

BIN
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit
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Binary file not shown.

30
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
View File

@ -2943,6 +2943,36 @@
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8> </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<filters /> <filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0> </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error" persistent="">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
<dependencies>
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error.c" persistent=".\Generated_Source\PSoC5\SCSI_Parity_Error.c">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<build_action v="ARM_C_FILE" />
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error.h" persistent=".\Generated_Source\PSoC5\SCSI_Parity_Error.h">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<build_action v="NONE" />
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
</dependencies> </dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089> </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8> </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>

161
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
View File

@ -9,7 +9,7 @@
<peripheral> <peripheral>
<name>SCSI_Out_Ctl</name> <name>SCSI_Out_Ctl</name>
<description>No description available</description> <description>No description available</description>
<baseAddress>0x40006577</baseAddress> <baseAddress>0x4000647E</baseAddress>
<addressBlock> <addressBlock>
<offset>0</offset> <offset>0</offset>
<size>0x1</size> <size>0x1</size>
@ -30,7 +30,7 @@
<peripheral> <peripheral>
<name>SCSI_Out_Bits</name> <name>SCSI_Out_Bits</name>
<description>No description available</description> <description>No description available</description>
<baseAddress>0x4000647C</baseAddress> <baseAddress>0x4000647B</baseAddress>
<addressBlock> <addressBlock>
<offset>0</offset> <offset>0</offset>
<size>0x1</size> <size>0x1</size>
@ -824,10 +824,165 @@
</register> </register>
</registers> </registers>
</peripheral> </peripheral>
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
<baseAddress>0x4000646A</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x31</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Parity_Error_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Parity_Error_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x30</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>FIFO0</name>
<description>FIFO0 clear</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable counter</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable counter</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTRENBL</name>
<description>Enables or disables the Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Interrupt enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Interrupt disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1LEVEL</name>
<description>FIFO level</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0LEVEL</name>
<description>FIFO level</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1CLEAR</name>
<description>FIFO clear</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0CLEAR</name>
<description>FIFO clear</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral> <peripheral>
<name>SCSI_CTL_PHASE</name> <name>SCSI_CTL_PHASE</name>
<description>No description available</description> <description>No description available</description>
<baseAddress>0x40006475</baseAddress> <baseAddress>0x40006471</baseAddress>
<addressBlock> <addressBlock>
<offset>0</offset> <offset>0</offset>
<size>0x1</size> <size>0x1</size>

BIN
software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
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BIN
software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym
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91
software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v
View File

@ -25,11 +25,13 @@ module scsiTarget (
output REQ, // Active High, connected to SCSI bus via inverter output REQ, // Active High, connected to SCSI bus via inverter
input nACK, // Active LOW, connected directly to SCSI bus. input nACK, // Active LOW, connected directly to SCSI bus.
input [7:0] nDBx_in, // Active LOW, connected directly to SCSI bus. input [7:0] nDBx_in, // Active LOW, connected directly to SCSI bus.
input nDBP, // Active LOW, connected directly to SCSI bus
input IO, // Active High, set by CPU via status register. input IO, // Active High, set by CPU via status register.
input nRST, // Active LOW, connected directly to SCSI bus. input nRST, // Active LOW, connected directly to SCSI bus.
input clk, input clk,
output tx_intr, output tx_intr,
output rx_intr output rx_intr,
output parityErr
); );
@ -55,6 +57,28 @@ cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync
localparam IO_WRITE = 1'b1; localparam IO_WRITE = 1'b1;
localparam IO_READ = 1'b0; localparam IO_READ = 1'b0;
/////////////////////////////////////////////////////////////////////////////
// Input filter
/////////////////////////////////////////////////////////////////////////////
// Do not respond to glitches in the ACK signal. This will cause us to
// transfer rubbish data, or too many bytes, and generally leads to
// hanging the SCSI bus. Reflected signals can cause the ACK signal
// to be dirty. We don't care so much about the others as we don't
// respond to them on the rising edge.
// 4-stage shifter. Ass
reg safeACK;
reg[3:0] ackShift;
always @(posedge op_clk) begin
if (ackShift[3:1] == 0) begin
safeACK <= 0;
end
else if (ackShift[3:1] == 1) begin
safeACK <= 1;
end
ackShift <= {ackShift[2:0], ~nACK};
end
///////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////
// STATE MACHINE // STATE MACHINE
///////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////
@ -125,14 +149,22 @@ wire[7:0] pi;
// Parallel output from the selected SRCA value (A0 or A1) to the ALU. // Parallel output from the selected SRCA value (A0 or A1) to the ALU.
wire[7:0] po; wire[7:0] po;
// Set true to trigger storing A1 into F1. // Set true to trigger storing A1 into F1. Set while in STATE_RX
wire fifoStore; reg fifoStore;
// Set to true on detecting a parity input while reading
reg parityErrReg;
// Temp values in parity calcs. We need to do it in 2 steps to avoid
// timing issues and running-out-of resources
reg[2:0] genParity;
reg REQReg;
// Set Output Pins // Set Output Pins
assign REQ = state[1] & state[2]; // STATE_READY & STATE_RX assign REQ = REQReg; // STATE_READY & STATE_RX
assign DBx_out[7:0] = data; assign DBx_out[7:0] = data;
assign pi[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus assign pi[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus
assign fifoStore = (state == STATE_RX) ? 1'b1 : 1'b0; assign parityErr = parityErrReg;
///////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////
@ -152,7 +184,7 @@ wire f0_bus_stat; // Tx FIFO not full
wire f0_blk_stat; // Tx FIFO empty wire f0_blk_stat; // Tx FIFO empty
wire f1_bus_stat; // Rx FIFO not empty wire f1_bus_stat; // Rx FIFO not empty
wire f1_blk_stat; // Rx FIFO full wire f1_blk_stat; // Rx FIFO full
wire txComplete = f0_blk_stat && (state == STATE_IDLE); wire txComplete = f0_blk_stat && (state == STATE_IDLE) && ~safeACK;
cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg
( (
/* input */ .clock(op_clk), /* input */ .clock(op_clk),
@ -174,18 +206,27 @@ always @(posedge op_clk) begin
// and output FIFO is not full. // and output FIFO is not full.
// Note that output FIFO is unused in TX mode. // Note that output FIFO is unused in TX mode.
if (!nRST) state <= STATE_IDLE; if (!nRST) state <= STATE_IDLE;
else if (nACK & !f0_blk_stat) else if (~safeACK & !f0_blk_stat && ((IO == IO_WRITE) || !f1_blk_stat))
state <= STATE_FIFOLOAD; state <= STATE_FIFOLOAD;
else else
state <= STATE_IDLE; state <= STATE_IDLE;
// Clear our output pins // Clear our output pins
data <= 8'b0; data <= 8'b0;
REQReg <= 1'b0;
fifoStore <= 1'b0;
parityErrReg <= 1'b0;
end end
STATE_FIFOLOAD: STATE_FIFOLOAD:
if (!nRST) state <= STATE_IDLE; if (!nRST) state <= STATE_IDLE;
else state <= IO == IO_WRITE ? STATE_TX : STATE_READY; else if (IO == IO_WRITE)
state <= STATE_TX;
else begin
state <= STATE_READY;
REQReg <= 1'b1;
end
STATE_TX: STATE_TX:
begin begin
@ -200,21 +241,33 @@ always @(posedge op_clk) begin
STATE_DESKEW: STATE_DESKEW:
if (!nRST) state <= STATE_IDLE; if (!nRST) state <= STATE_IDLE;
else if(deskewComplete) state <= STATE_READY; else if(deskewComplete) begin
else state <= STATE_DESKEW; state <= STATE_READY;
REQReg <= 1'b1;
end else state <= STATE_DESKEW;
STATE_READY: STATE_READY:
if (!nRST) state <= STATE_IDLE; if (!nRST) state <= STATE_IDLE;
else if (~nACK && ((IO == IO_WRITE) || !f1_blk_stat)) state <= STATE_RX; else if (safeACK) begin
else state <= STATE_READY; state <= STATE_RX;
fifoStore <= 1'b1;
STATE_RX: // same code here as for the IDLE state, as we make genParity[0] <= (~nDBP) ^ 1'b1 ^ ~nDBx_in[7] ^ ~nDBx_in[6];
// a quick run back to the next byte if possible. genParity[1] <= ~nDBx_in[5] ^ ~nDBx_in[4] ^ ~nDBx_in[3];
if (!nRST) state <= STATE_IDLE; genParity[2] <= ~nDBx_in[2] ^ ~nDBx_in[1] ^ ~nDBx_in[0];
else if (nACK & !f0_blk_stat) end else state <= STATE_READY;
state <= STATE_FIFOLOAD;
else STATE_RX:
state <= STATE_IDLE; begin
state <= STATE_IDLE;
REQReg <= 1'b0;
fifoStore <= 1'b0;
parityErrReg <= 1'b0;
data <= 8'b0;
if (IO == IO_READ) begin
parityErrReg <= ^genParity[2:0];
end
end
default: state <= STATE_IDLE; default: state <= STATE_IDLE;
endcase endcase

36
software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
View File

@ -18,7 +18,7 @@
<Tool Name="postbuild" Command="" Options="" /> <Tool Name="postbuild" Command="" Options="" />
</Toolchain> </Toolchain>
</Toolchains> </Toolchains>
<Project Name="USB_Bootloader" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" Version="4.0" Type="Bootloader"> <Project Name="USB_Bootloader" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" Version="4.0" Type="Bootloader">
<CMSIS_SVD_File>USB_Bootloader.svd</CMSIS_SVD_File> <CMSIS_SVD_File>USB_Bootloader.svd</CMSIS_SVD_File>
<Datasheet /> <Datasheet />
<LinkerFiles> <LinkerFiles>
@ -27,13 +27,13 @@
<LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile> <LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
</LinkerFiles> </LinkerFiles>
<Folders> <Folders>
<Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn"> <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn"> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">
<File BuildType="BUILD" Toolchain="">.\main.c</File> <File BuildType="BUILD" Toolchain="">.\main.c</File>
</Files> </Files>
</Folder> </Folder>
<Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5"> <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn"> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cymetadata.c</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cymetadata.c</File>
@ -111,41 +111,41 @@
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>
</Files> </Files>
</Folder> </Folder>
<Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_GCC"> <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_GCC">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn"> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">
<File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File> <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>
</Files> </Files>
</Folder> </Folder>
<Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK"> <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn"> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">
<File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File> <File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>
</Files> </Files>
</Folder> </Folder>
<Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\IAR"> <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\IAR">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn"> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">
<File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File> <File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>
</Files> </Files>
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\codegentemp"> <Folder BuildType="EXCLUDE" Path=".\codegentemp">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441"> <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473"> <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951"> <Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\DP8051"> <Folder BuildType="EXCLUDE" Path=".\DP8051">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\CortexM0"> <Folder BuildType="EXCLUDE" Path=".\CortexM0">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\CortexM3"> <Folder BuildType="EXCLUDE" Path=".\CortexM3">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />
</Folder> </Folder>
</Folders> </Folders>
</Project> </Project>

BIN
software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit
View File

Binary file not shown.

7
software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
View File

@ -1081,6 +1081,7 @@
<name_val_pair name="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" /> <name_val_pair name="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
<name_val_pair name="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" /> <name_val_pair name="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
<name_val_pair name="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" /> <name_val_pair name="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
<name_val_pair name="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
</name> </name>
<name v="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3"> <name v="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3">
<name_val_pair name=".\main.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;DEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-ffunction-sections &quot;" /> <name_val_pair name=".\main.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;DEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-ffunction-sections &quot;" />
@ -1114,7 +1115,7 @@
<name_val_pair name="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Debug\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" /> <name_val_pair name="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Debug\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
</name> </name>
</genericCmdLineData> </genericCmdLineData>
<codeGenCmdLineTag v="&quot;-.appdatapath&quot; &quot;C:\Users\Micha_000\AppData\Local\Cypress Semiconductor\PSoC Creator\3.0&quot; &quot;-.fdsnotice&quot; &quot;-.fdswarpdepfile=warp_dependencies.txt&quot; &quot;-.fdselabdepfile=elab_dependencies.txt&quot; &quot;-.fdsbldfile=generated_files.txt&quot; &quot;-p&quot; &quot;Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj&quot; &quot;-d&quot; &quot;CY8C5267AXI-LP051&quot; &quot;-s&quot; &quot;Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5&quot; &quot;--&quot; &quot;-yv2&quot; &quot;-v3&quot; &quot;-ygs&quot; &quot;-q10&quot; &quot;-o2&quot; &quot;-.fftcfgtype=LE&quot; " /> <codeGenCmdLineTag v="&quot;-.appdatapath&quot; &quot;C:\Users\Micha_000\AppData\Local\Cypress Semiconductor\PSoC Creator\3.0&quot; &quot;-.fdsnotice&quot; &quot;-.fdswarpdepfile=warp_dependencies.txt&quot; &quot;-.fdselabdepfile=elab_dependencies.txt&quot; &quot;-.fdsbldfile=generated_files.txt&quot; &quot;-p&quot; &quot;Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj&quot; &quot;-d&quot; &quot;CY8C5267AXI-LP051&quot; &quot;-s&quot; &quot;Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5&quot; &quot;--&quot; &quot;-yv2&quot; &quot;-v3&quot; &quot;-ygs&quot; &quot;-q10&quot; &quot;-o2&quot; &quot;-.fftcfgtype=LE&quot; " />
</CyGuid_b0374e30-ce3a-47f2-ad85-821643292c68> </CyGuid_b0374e30-ce3a-47f2-ad85-821643292c68>
</dataGuid> </dataGuid>
<dataGuid v="597c5b74-0c46-4204-8b7f-96f3570671dc"> <dataGuid v="597c5b74-0c46-4204-8b7f-96f3570671dc">
@ -1667,14 +1668,14 @@
<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif</v> <v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif</v>
<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif</v> <v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif</v>
</warp_dep> </warp_dep>
<deps_time v="130503061473414440" /> <deps_time v="130537023991022657" />
<top_block v="TopDesign" /> <top_block v="TopDesign" />
<last_generation v="0" /> <last_generation v="0" />
</CyGuid_925cc1e1-309e-4e08-b0a1-09a83c35b157> </CyGuid_925cc1e1-309e-4e08-b0a1-09a83c35b157>
</dataGuid> </dataGuid>
<dataGuid v="769d31ea-68b1-4f0c-b90a-7c10a43ee563"> <dataGuid v="769d31ea-68b1-4f0c-b90a-7c10a43ee563">
<CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563 type_name="CyDesigner.Common.ProjMgmt.Model.CyLinkCustomData" version="1"> <CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563 type_name="CyDesigner.Common.ProjMgmt.Model.CyLinkCustomData" version="1">
<deps_time v="130503062519177686" /> <deps_time v="130537025103831962" />
</CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563> </CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563>
</dataGuid> </dataGuid>
<dataGuid v="bf610382-39c6-441f-80b8-b04622ea7845"> <dataGuid v="bf610382-39c6-441f-80b8-b04622ea7845">

80
software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.rpt
View File

@ -1,13 +1,13 @@
Loading plugins phase: Elapsed time ==> 0s.484ms Loading plugins phase: Elapsed time ==> 0s.529ms
Initializing data phase: Elapsed time ==> 4s.047ms Initializing data phase: Elapsed time ==> 4s.249ms
<CYPRESSTAG name="CyDsfit arguments..."> <CYPRESSTAG name="CyDsfit arguments...">
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG> cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG>
<CYPRESSTAG name="Design elaboration results..."> <CYPRESSTAG name="Design elaboration results...">
</CYPRESSTAG> </CYPRESSTAG>
Elaboration phase: Elapsed time ==> 7s.623ms Elaboration phase: Elapsed time ==> 8s.312ms
<CYPRESSTAG name="HDL generation results..."> <CYPRESSTAG name="HDL generation results...">
</CYPRESSTAG> </CYPRESSTAG>
HDL generation phase: Elapsed time ==> 0s.655ms HDL generation phase: Elapsed time ==> 1s.015ms
<CYPRESSTAG name="Synthesis results..."> <CYPRESSTAG name="Synthesis results...">
| | | | | | | | | | | | | |
@ -25,23 +25,23 @@ HDL generation phase: Elapsed time ==> 0s.655ms
====================================================================== ======================================================================
Compiling: USB_Bootloader.v Compiling: USB_Bootloader.v
Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe
Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog
====================================================================== ======================================================================
====================================================================== ======================================================================
Compiling: USB_Bootloader.v Compiling: USB_Bootloader.v
Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe
Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog
====================================================================== ======================================================================
====================================================================== ======================================================================
Compiling: USB_Bootloader.v Compiling: USB_Bootloader.v
Program : vlogfe Program : vlogfe
Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v
====================================================================== ======================================================================
vlogfe V6.3 IR 41: Verilog parser vlogfe V6.3 IR 41: Verilog parser
Sun Jul 20 15:00:50 2014 Thu Aug 28 22:24:58 2014
====================================================================== ======================================================================
@ -51,7 +51,7 @@ Options : -yv2 -q10 USB_Bootloader.v
====================================================================== ======================================================================
vpp V6.3 IR 41: Verilog Pre-Processor vpp V6.3 IR 41: Verilog Pre-Processor
Sun Jul 20 15:00:50 2014 Thu Aug 28 22:24:59 2014
vpp: No errors. vpp: No errors.
@ -76,11 +76,11 @@ vlogfe: No errors.
====================================================================== ======================================================================
Compiling: USB_Bootloader.v Compiling: USB_Bootloader.v
Program : tovif Program : tovif
Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v
====================================================================== ======================================================================
tovif V6.3 IR 41: High-level synthesis tovif V6.3 IR 41: High-level synthesis
Sun Jul 20 15:00:51 2014 Thu Aug 28 22:25:00 2014
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.
@ -91,8 +91,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\c
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.
Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.
tovif: No errors. tovif: No errors.
@ -100,11 +100,11 @@ tovif: No errors.
====================================================================== ======================================================================
Compiling: USB_Bootloader.v Compiling: USB_Bootloader.v
Program : topld Program : topld
Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v
====================================================================== ======================================================================
topld V6.3 IR 41: Synthesis and optimization topld V6.3 IR 41: Synthesis and optimization
Sun Jul 20 15:00:52 2014 Thu Aug 28 22:25:02 2014
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.
@ -115,8 +115,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\c
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.
Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.
---------------------------------------------------------- ----------------------------------------------------------
@ -202,16 +202,16 @@ topld: No errors.
CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp
Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe
Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog
</CYPRESSTAG> </CYPRESSTAG>
Warp synthesis phase: Elapsed time ==> 8s.781ms Warp synthesis phase: Elapsed time ==> 10s.236ms
<CYPRESSTAG name="Fitter results..."> <CYPRESSTAG name="Fitter results...">
<CYPRESSTAG name="Fitter startup details..."> <CYPRESSTAG name="Fitter startup details...">
cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Sunday, 20 July 2014 15:00:57 cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Thursday, 28 August 2014 22:25:08
Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Design parsing"> <CYPRESSTAG name="Design parsing">
Design parsing phase: Elapsed time ==> 0s.031ms Design parsing phase: Elapsed time ==> 0s.344ms
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Tech mapping"> <CYPRESSTAG name="Tech mapping">
<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM"> <CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">
@ -1315,7 +1315,7 @@ LPF Fixed Blocks : 0 : 2 : 2 : 0.00%
SAR Fixed Blocks : 0 : 1 : 1 : 0.00% SAR Fixed Blocks : 0 : 1 : 1 : 0.00%
</CYPRESSTAG> </CYPRESSTAG>
Technology Mapping: Elapsed time ==> 0s.406ms Technology Mapping: Elapsed time ==> 0s.406ms
Tech mapping phase: Elapsed time ==> 0s.687ms Tech mapping phase: Elapsed time ==> 0s.702ms
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Analog Placement"> <CYPRESSTAG name="Analog Placement">
Initial Analog Placement Results: Initial Analog Placement Results:
@ -1345,7 +1345,7 @@ IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed)
IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed) IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed)
IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed) IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed)
USB[0]@[FFB(USB,0)] : \USBFS:USB\ USB[0]@[FFB(USB,0)] : \USBFS:USB\
Analog Placement phase: Elapsed time ==> 0s.094ms Analog Placement phase: Elapsed time ==> 0s.109ms
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Analog Routing"> <CYPRESSTAG name="Analog Routing">
Analog Routing phase: Elapsed time ==> 0s.000ms Analog Routing phase: Elapsed time ==> 0s.000ms
@ -1363,12 +1363,12 @@ Dump of CyP35AnalogRoutingResultsDB
IsVddaHalfUsedForComp = False IsVddaHalfUsedForComp = False
IsVddaHalfUsedForSar0 = False IsVddaHalfUsedForSar0 = False
IsVddaHalfUsedForSar1 = False IsVddaHalfUsedForSar1 = False
Analog Code Generation phase: Elapsed time ==> 1s.405ms Analog Code Generation phase: Elapsed time ==> 1s.453ms
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Digital Placement"> <CYPRESSTAG name="Digital Placement">
<CYPRESSTAG name="Detailed placement messages"> <CYPRESSTAG name="Detailed placement messages">
I2659: No Constrained paths were found. The placer will run in non-timing driven mode. I2659: No Constrained paths were found. The placer will run in non-timing driven mode.
I2076: Total run-time: 5.3 sec. I2076: Total run-time: 4.1 sec.
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="PLD Packing"> <CYPRESSTAG name="PLD Packing">
@ -1382,10 +1382,10 @@ PLD Packing: Elapsed time ==> 0s.000ms
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG> Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
<CYPRESSTAG name="Final Partitioning Summary"> <CYPRESSTAG name="Final Partitioning Summary">
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG> Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
Partitioning: Elapsed time ==> 0s.079ms Partitioning: Elapsed time ==> 0s.063ms
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Simulated Annealing"> <CYPRESSTAG name="Simulated Annealing">
Annealing: Elapsed time ==> 0s.000ms Annealing: Elapsed time ==> 0s.014ms
<CYPRESSTAG name="Simulated Annealing Results"> <CYPRESSTAG name="Simulated Annealing Results">
The seed used for moves was 114161200. The seed used for moves was 114161200.
Inital cost was 120, final cost is 120 (0.00% improvement).</CYPRESSTAG> Inital cost was 120, final cost is 120 (0.00% improvement).</CYPRESSTAG>
@ -2664,32 +2664,32 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connection
</CYPRESSTAG> </CYPRESSTAG>
</CYPRESSTAG> </CYPRESSTAG>
</CYPRESSTAG> </CYPRESSTAG>
Digital component placer commit/Report: Elapsed time ==> 0s.373ms Digital component placer commit/Report: Elapsed time ==> 0s.359ms
Digital Placement phase: Elapsed time ==> 9s.093ms Digital Placement phase: Elapsed time ==> 7s.578ms
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Digital Routing"> <CYPRESSTAG name="Digital Routing">
Routing successful. Routing successful.
Digital Routing phase: Elapsed time ==> 8s.703ms Digital Routing phase: Elapsed time ==> 9s.796ms
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Bitstream and API generation"> <CYPRESSTAG name="Bitstream and API generation">
Bitstream and API generation phase: Elapsed time ==> 25s.515ms Bitstream and API generation phase: Elapsed time ==> 25s.390ms
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Bitstream verification"> <CYPRESSTAG name="Bitstream verification">
Bitstream verification phase: Elapsed time ==> 0s.125ms Bitstream verification phase: Elapsed time ==> 0s.158ms
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Static timing analysis"> <CYPRESSTAG name="Static timing analysis">
Timing report is in USB_Bootloader_timing.html. Timing report is in USB_Bootloader_timing.html.
Static timing analysis phase: Elapsed time ==> 3s.999ms Static timing analysis phase: Elapsed time ==> 4s.278ms
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Data reporting"> <CYPRESSTAG name="Data reporting">
Data reporting phase: Elapsed time ==> 0s.000ms Data reporting phase: Elapsed time ==> 0s.000ms
</CYPRESSTAG> </CYPRESSTAG>
<CYPRESSTAG name="Database update..."> <CYPRESSTAG name="Database update...">
Design database save phase: Elapsed time ==> 0s.734ms Design database save phase: Elapsed time ==> 0s.656ms
</CYPRESSTAG> </CYPRESSTAG>
cydsfit: Elapsed time ==> 50s.735ms cydsfit: Elapsed time ==> 50s.921ms
</CYPRESSTAG> </CYPRESSTAG>
Fitter phase: Elapsed time ==> 50s.829ms Fitter phase: Elapsed time ==> 50s.997ms
API generation phase: Elapsed time ==> 23s.686ms API generation phase: Elapsed time ==> 24s.640ms
Dependency generation phase: Elapsed time ==> 0s.859ms Dependency generation phase: Elapsed time ==> 0s.859ms
Cleanup phase: Elapsed time ==> 0s.609ms Cleanup phase: Elapsed time ==> 0s.844ms

2
software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader_timing.html
View File

@ -539,7 +539,7 @@ function getElementsByClass(rootNode, elemName, className)
<tr> <td class="prop"> Project :</td> <tr> <td class="prop"> Project :</td>
<td class="proptext"> USB_Bootloader</td></tr> <td class="proptext"> USB_Bootloader</td></tr>
<tr> <td class="prop"> Build Time :</td> <tr> <td class="prop"> Build Time :</td>
<td class="proptext"> 07/20/14 15:01:46</td></tr> <td class="proptext"> 08/28/14 22:25:58</td></tr>
<tr> <td class="prop"> Device :</td> <tr> <td class="prop"> Device :</td>
<td class="proptext"> CY8C5267AXI-LP051</td></tr> <td class="proptext"> CY8C5267AXI-LP051</td></tr>
<tr> <td class="prop"> Temperature :</td> <tr> <td class="prop"> Temperature :</td>

521
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c Normal file
View File

@ -0,0 +1,521 @@
/*******************************************************************************
* File Name: SCSI_CLK.c
* Version 2.10
*
* Description:
* This file provides the source code to the API for the clock component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include "SCSI_CLK.h"
/* Clock Distribution registers. */
#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)
#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)
#define BCFG2_MASK (0x80u)
#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)
#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)
#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)
/*******************************************************************************
* Function Name: SCSI_CLK_Start
********************************************************************************
*
* Summary:
* Starts the clock. Note that on startup, clocks may be already running if the
* "Start on Reset" option is enabled in the DWR.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_Start(void)
{
/* Set the bit to enable the clock. */
SCSI_CLK_CLKEN |= SCSI_CLK_CLKEN_MASK;
SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
}
/*******************************************************************************
* Function Name: SCSI_CLK_Stop
********************************************************************************
*
* Summary:
* Stops the clock and returns immediately. This API does not require the
* source clock to be running but may return before the hardware is actually
* disabled. If the settings of the clock are changed after calling this
* function, the clock may glitch when it is started. To avoid the clock
* glitch, use the StopBlock function.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_Stop(void)
{
/* Clear the bit to disable the clock. */
SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
}
#if(CY_PSOC3 || CY_PSOC5LP)
/*******************************************************************************
* Function Name: SCSI_CLK_StopBlock
********************************************************************************
*
* Summary:
* Stops the clock and waits for the hardware to actually be disabled before
* returning. This ensures that the clock is never truncated (high part of the
* cycle will terminate before the clock is disabled and the API returns).
* Note that the source clock must be running or this API will never return as
* a stopped clock cannot be disabled.
*
* Parameters:
* None
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_StopBlock(void)
{
if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
{
#if HAS_CLKDIST_LD_DISABLE
uint16 oldDivider;
CLK_DIST_LD = 0u;
/* Clear all the mask bits except ours. */
#if defined(SCSI_CLK__CFG3)
CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
CLK_DIST_DMASK = 0x00u;
#else
CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
CLK_DIST_AMASK = 0x00u;
#endif /* SCSI_CLK__CFG3 */
/* Clear mask of bus clock. */
CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
oldDivider = CY_GET_REG16(SCSI_CLK_DIV_PTR);
CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
/* Wait for clock to be disabled */
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
#endif /* HAS_CLKDIST_LD_DISABLE */
/* Clear the bit to disable the clock. */
SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
#if HAS_CLKDIST_LD_DISABLE
/* Clear the disable bit */
CLK_DIST_LD = 0x00u;
CY_SET_REG16(SCSI_CLK_DIV_PTR, oldDivider);
#endif /* HAS_CLKDIST_LD_DISABLE */
}
}
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/*******************************************************************************
* Function Name: SCSI_CLK_StandbyPower
********************************************************************************
*
* Summary:
* Sets whether the clock is active in standby mode.
*
* Parameters:
* state: 0 to disable clock during standby, nonzero to enable.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_StandbyPower(uint8 state)
{
if(state == 0u)
{
SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
}
else
{
SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
}
}
/*******************************************************************************
* Function Name: SCSI_CLK_SetDividerRegister
********************************************************************************
*
* Summary:
* Modifies the clock divider and, thus, the frequency. When the clock divider
* register is set to zero or changed from zero, the clock will be temporarily
* disabled in order to change the SSS mode bit. If the clock is enabled when
* SetDividerRegister is called, then the source clock must be running.
*
* Parameters:
* clkDivider: Divider register value (0-65,535). This value is NOT the
* divider; the clock hardware divides by clkDivider plus one. For example,
* to divide the clock by 2, this parameter should be set to 1.
* restart: If nonzero, restarts the clock divider: the current clock cycle
* will be truncated and the new divide value will take effect immediately. If
* zero, the new divide value will take effect at the end of the current clock
* cycle.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
{
uint8 enabled;
uint8 currSrc = SCSI_CLK_GetSourceRegister();
uint16 oldDivider = SCSI_CLK_GetDividerRegister();
if (clkDivider != oldDivider)
{
enabled = SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK;
if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
{
/* Moving to/from SSS requires correct ordering to prevent halting the clock */
if (oldDivider == 0u)
{
/* Moving away from SSS, set the divider first so when SSS is cleared we */
/* don't halt the clock. Using the shadow load isn't required as the */
/* divider is ignored while SSS is set. */
CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
}
else
{
/* Moving to SSS, set SSS which then ignores the divider and we can set */
/* it without bothering with the shadow load. */
SCSI_CLK_MOD_SRC |= CYCLK_SSS;
CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
}
}
else
{
if (enabled != 0u)
{
CLK_DIST_LD = 0x00u;
/* Clear all the mask bits except ours. */
#if defined(SCSI_CLK__CFG3)
CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
CLK_DIST_DMASK = 0x00u;
#else
CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
CLK_DIST_AMASK = 0x00u;
#endif /* SCSI_CLK__CFG3 */
/* Clear mask of bus clock. */
CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
/* If clock is currently enabled, disable it if async or going from N-to-1*/
if (((SCSI_CLK_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
{
#if HAS_CLKDIST_LD_DISABLE
CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
/* Wait for clock to be disabled */
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
#endif /* HAS_CLKDIST_LD_DISABLE */
SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
#if HAS_CLKDIST_LD_DISABLE
/* Clear the disable bit */
CLK_DIST_LD = 0x00u;
#endif /* HAS_CLKDIST_LD_DISABLE */
}
}
/* Load divide value. */
if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
{
/* If the clock is still enabled, use the shadow registers */
CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
}
else
{
/* If the clock is disabled, set the divider directly */
CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
SCSI_CLK_CLKEN |= enabled;
}
}
}
}
/*******************************************************************************
* Function Name: SCSI_CLK_GetDividerRegister
********************************************************************************
*
* Summary:
* Gets the clock divider register value.
*
* Parameters:
* None
*
* Returns:
* Divide value of the clock minus 1. For example, if the clock is set to
* divide by 2, the return value will be 1.
*
*******************************************************************************/
uint16 SCSI_CLK_GetDividerRegister(void)
{
return CY_GET_REG16(SCSI_CLK_DIV_PTR);
}
/*******************************************************************************
* Function Name: SCSI_CLK_SetModeRegister
********************************************************************************
*
* Summary:
* Sets flags that control the operating mode of the clock. This function only
* changes flags from 0 to 1; flags that are already 1 will remain unchanged.
* To clear flags, use the ClearModeRegister function. The clock must be
* disabled before changing the mode.
*
* Parameters:
* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
* clkMode should be a set of the following optional bits or'ed together.
* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
* occur when the divider count reaches half of the divide
* value.
* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
* is asserted for approximately half of its period. When
* disabled, the output clock is asserted for one period of the
* source clock.
* - CYCLK_SYNC Enable output synchronization to master clock. This should
* be enabled for all synchronous clocks.
* See the Technical Reference Manual for details about setting the mode of
* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_SetModeRegister(uint8 modeBitMask)
{
SCSI_CLK_MOD_SRC |= modeBitMask & (uint8)SCSI_CLK_MODE_MASK;
}
/*******************************************************************************
* Function Name: SCSI_CLK_ClearModeRegister
********************************************************************************
*
* Summary:
* Clears flags that control the operating mode of the clock. This function
* only changes flags from 1 to 0; flags that are already 0 will remain
* unchanged. To set flags, use the SetModeRegister function. The clock must be
* disabled before changing the mode.
*
* Parameters:
* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
* clkMode should be a set of the following optional bits or'ed together.
* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
* occur when the divider count reaches half of the divide
* value.
* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
* is asserted for approximately half of its period. When
* disabled, the output clock is asserted for one period of the
* source clock.
* - CYCLK_SYNC Enable output synchronization to master clock. This should
* be enabled for all synchronous clocks.
* See the Technical Reference Manual for details about setting the mode of
* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_ClearModeRegister(uint8 modeBitMask)
{
SCSI_CLK_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SCSI_CLK_MODE_MASK));
}
/*******************************************************************************
* Function Name: SCSI_CLK_GetModeRegister
********************************************************************************
*
* Summary:
* Gets the clock mode register value.
*
* Parameters:
* None
*
* Returns:
* Bit mask representing the enabled mode bits. See the SetModeRegister and
* ClearModeRegister descriptions for details about the mode bits.
*
*******************************************************************************/
uint8 SCSI_CLK_GetModeRegister(void)
{
return SCSI_CLK_MOD_SRC & (uint8)(SCSI_CLK_MODE_MASK);
}
/*******************************************************************************
* Function Name: SCSI_CLK_SetSourceRegister
********************************************************************************
*
* Summary:
* Sets the input source of the clock. The clock must be disabled before
* changing the source. The old and new clock sources must be running.
*
* Parameters:
* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the
* following input sources:
* - CYCLK_SRC_SEL_SYNC_DIG
* - CYCLK_SRC_SEL_IMO
* - CYCLK_SRC_SEL_XTALM
* - CYCLK_SRC_SEL_ILO
* - CYCLK_SRC_SEL_PLL
* - CYCLK_SRC_SEL_XTALK
* - CYCLK_SRC_SEL_DSI_G
* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
* See the Technical Reference Manual for details on clock sources.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_SetSourceRegister(uint8 clkSource)
{
uint16 currDiv = SCSI_CLK_GetDividerRegister();
uint8 oldSrc = SCSI_CLK_GetSourceRegister();
if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
(clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
{
/* Switching to Master and divider is 1, set SSS, which will output master, */
/* then set the source so we are consistent. */
SCSI_CLK_MOD_SRC |= CYCLK_SSS;
SCSI_CLK_MOD_SRC =
(SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
}
else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
(clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
{
/* Switching from Master to not and divider is 1, set source, so we don't */
/* lock when we clear SSS. */
SCSI_CLK_MOD_SRC =
(SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
}
else
{
SCSI_CLK_MOD_SRC =
(SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
}
}
/*******************************************************************************
* Function Name: SCSI_CLK_GetSourceRegister
********************************************************************************
*
* Summary:
* Gets the input source of the clock.
*
* Parameters:
* None
*
* Returns:
* The input source of the clock. See SetSourceRegister for details.
*
*******************************************************************************/
uint8 SCSI_CLK_GetSourceRegister(void)
{
return SCSI_CLK_MOD_SRC & SCSI_CLK_SRC_SEL_MSK;
}
#if defined(SCSI_CLK__CFG3)
/*******************************************************************************
* Function Name: SCSI_CLK_SetPhaseRegister
********************************************************************************
*
* Summary:
* Sets the phase delay of the analog clock. This function is only available
* for analog clocks. The clock must be disabled before changing the phase
* delay to avoid glitches.
*
* Parameters:
* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
* clkPhase must be from 1 to 11 inclusive. Other values, including 0,
* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11
* produces a 10ns delay.
*
* Returns:
* None
*
*******************************************************************************/
void SCSI_CLK_SetPhaseRegister(uint8 clkPhase)
{
SCSI_CLK_PHASE = clkPhase & SCSI_CLK_PHASE_MASK;
}
/*******************************************************************************
* Function Name: SCSI_CLK_GetPhase
********************************************************************************
*
* Summary:
* Gets the phase delay of the analog clock. This function is only available
* for analog clocks.
*
* Parameters:
* None
*
* Returns:
* Phase of the analog clock. See SetPhaseRegister for details.
*
*******************************************************************************/
uint8 SCSI_CLK_GetPhaseRegister(void)
{
return SCSI_CLK_PHASE & SCSI_CLK_PHASE_MASK;
}
#endif /* SCSI_CLK__CFG3 */
/* [] END OF FILE */

124
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h Normal file
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@ -0,0 +1,124 @@
/*******************************************************************************
* File Name: SCSI_CLK.h
* Version 2.10
*
* Description:
* Provides the function and constant definitions for the clock component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CLOCK_SCSI_CLK_H)
#define CY_CLOCK_SCSI_CLK_H
#include <cytypes.h>
#include <cyfitter.h>
/***************************************
* Conditional Compilation Parameters
***************************************/
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
#error Component cy_clock_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
/***************************************
* Function Prototypes
***************************************/
void SCSI_CLK_Start(void) ;
void SCSI_CLK_Stop(void) ;
#if(CY_PSOC3 || CY_PSOC5LP)
void SCSI_CLK_StopBlock(void) ;
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
void SCSI_CLK_StandbyPower(uint8 state) ;
void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
;
uint16 SCSI_CLK_GetDividerRegister(void) ;
void SCSI_CLK_SetModeRegister(uint8 modeBitMask) ;
void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) ;
uint8 SCSI_CLK_GetModeRegister(void) ;
void SCSI_CLK_SetSourceRegister(uint8 clkSource) ;
uint8 SCSI_CLK_GetSourceRegister(void) ;
#if defined(SCSI_CLK__CFG3)
void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) ;
uint8 SCSI_CLK_GetPhaseRegister(void) ;
#endif /* defined(SCSI_CLK__CFG3) */
#define SCSI_CLK_Enable() SCSI_CLK_Start()
#define SCSI_CLK_Disable() SCSI_CLK_Stop()
#define SCSI_CLK_SetDivider(clkDivider) SCSI_CLK_SetDividerRegister(clkDivider, 1u)
#define SCSI_CLK_SetDividerValue(clkDivider) SCSI_CLK_SetDividerRegister((clkDivider) - 1u, 1u)
#define SCSI_CLK_SetMode(clkMode) SCSI_CLK_SetModeRegister(clkMode)
#define SCSI_CLK_SetSource(clkSource) SCSI_CLK_SetSourceRegister(clkSource)
#if defined(SCSI_CLK__CFG3)
#define SCSI_CLK_SetPhase(clkPhase) SCSI_CLK_SetPhaseRegister(clkPhase)
#define SCSI_CLK_SetPhaseValue(clkPhase) SCSI_CLK_SetPhaseRegister((clkPhase) + 1u)
#endif /* defined(SCSI_CLK__CFG3) */
/***************************************
* Registers
***************************************/
/* Register to enable or disable the clock */
#define SCSI_CLK_CLKEN (* (reg8 *) SCSI_CLK__PM_ACT_CFG)
#define SCSI_CLK_CLKEN_PTR ((reg8 *) SCSI_CLK__PM_ACT_CFG)
/* Register to enable or disable the clock */
#define SCSI_CLK_CLKSTBY (* (reg8 *) SCSI_CLK__PM_STBY_CFG)
#define SCSI_CLK_CLKSTBY_PTR ((reg8 *) SCSI_CLK__PM_STBY_CFG)
/* Clock LSB divider configuration register. */
#define SCSI_CLK_DIV_LSB (* (reg8 *) SCSI_CLK__CFG0)
#define SCSI_CLK_DIV_LSB_PTR ((reg8 *) SCSI_CLK__CFG0)
#define SCSI_CLK_DIV_PTR ((reg16 *) SCSI_CLK__CFG0)
/* Clock MSB divider configuration register. */
#define SCSI_CLK_DIV_MSB (* (reg8 *) SCSI_CLK__CFG1)
#define SCSI_CLK_DIV_MSB_PTR ((reg8 *) SCSI_CLK__CFG1)
/* Mode and source configuration register */
#define SCSI_CLK_MOD_SRC (* (reg8 *) SCSI_CLK__CFG2)
#define SCSI_CLK_MOD_SRC_PTR ((reg8 *) SCSI_CLK__CFG2)
#if defined(SCSI_CLK__CFG3)
/* Analog clock phase configuration register */
#define SCSI_CLK_PHASE (* (reg8 *) SCSI_CLK__CFG3)
#define SCSI_CLK_PHASE_PTR ((reg8 *) SCSI_CLK__CFG3)
#endif /* defined(SCSI_CLK__CFG3) */
/**************************************
* Register Constants
**************************************/
/* Power manager register masks */
#define SCSI_CLK_CLKEN_MASK SCSI_CLK__PM_ACT_MSK
#define SCSI_CLK_CLKSTBY_MASK SCSI_CLK__PM_STBY_MSK
/* CFG2 field masks */
#define SCSI_CLK_SRC_SEL_MSK SCSI_CLK__CFG2_SRC_SEL_MASK
#define SCSI_CLK_MODE_MASK (~(SCSI_CLK_SRC_SEL_MSK))
#if defined(SCSI_CLK__CFG3)
/* CFG3 phase mask */
#define SCSI_CLK_PHASE_MASK SCSI_CLK__CFG3_PHASE_DLY_MASK
#endif /* defined(SCSI_CLK__CFG3) */
#endif /* CY_CLOCK_SCSI_CLK_H */
/* [] END OF FILE */

134
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c Normal file
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@ -0,0 +1,134 @@
/*******************************************************************************
* File Name: SCSI_Parity_Error.c
* Version 1.80
*
* Description:
* This file contains API to enable firmware to read the value of a Status
* Register.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "SCSI_Parity_Error.h"
#if !defined(SCSI_Parity_Error_sts_sts_reg__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Function Name: SCSI_Parity_Error_Read
********************************************************************************
*
* Summary:
* Reads the current value assigned to the Status Register.
*
* Parameters:
* None.
*
* Return:
* The current value in the Status Register.
*
*******************************************************************************/
uint8 SCSI_Parity_Error_Read(void)
{
return SCSI_Parity_Error_Status;
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_InterruptEnable
********************************************************************************
*
* Summary:
* Enables the Status Register interrupt.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Parity_Error_InterruptEnable(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
SCSI_Parity_Error_Status_Aux_Ctrl |= SCSI_Parity_Error_STATUS_INTR_ENBL;
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_InterruptDisable
********************************************************************************
*
* Summary:
* Disables the Status Register interrupt.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Parity_Error_InterruptDisable(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
SCSI_Parity_Error_Status_Aux_Ctrl &= (uint8)(~SCSI_Parity_Error_STATUS_INTR_ENBL);
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_WriteMask
********************************************************************************
*
* Summary:
* Writes the current mask value assigned to the Status Register.
*
* Parameters:
* mask: Value to write into the mask register.
*
* Return:
* None.
*
*******************************************************************************/
void SCSI_Parity_Error_WriteMask(uint8 mask)
{
#if(SCSI_Parity_Error_INPUTS < 8u)
mask &= (uint8)((((uint8)1u) << SCSI_Parity_Error_INPUTS) - 1u);
#endif /* End SCSI_Parity_Error_INPUTS < 8u */
SCSI_Parity_Error_Status_Mask = mask;
}
/*******************************************************************************
* Function Name: SCSI_Parity_Error_ReadMask
********************************************************************************
*
* Summary:
* Reads the current interrupt mask assigned to the Status Register.
*
* Parameters:
* None.
*
* Return:
* The value of the interrupt mask of the Status Register.
*
*******************************************************************************/
uint8 SCSI_Parity_Error_ReadMask(void)
{
return SCSI_Parity_Error_Status_Mask;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

63
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h Normal file
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@ -0,0 +1,63 @@
/*******************************************************************************
* File Name: SCSI_Parity_Error.h
* Version 1.80
*
* Description:
* This file containts Status Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */
#define CY_STATUS_REG_SCSI_Parity_Error_H
#include "cytypes.h"
#include "CyLib.h"
/***************************************
* Function Prototypes
***************************************/
uint8 SCSI_Parity_Error_Read(void) ;
void SCSI_Parity_Error_InterruptEnable(void) ;
void SCSI_Parity_Error_InterruptDisable(void) ;
void SCSI_Parity_Error_WriteMask(uint8 mask) ;
uint8 SCSI_Parity_Error_ReadMask(void) ;
/***************************************
* API Constants
***************************************/
#define SCSI_Parity_Error_STATUS_INTR_ENBL 0x10u
/***************************************
* Parameter Constants
***************************************/
/* Status Register Inputs */
#define SCSI_Parity_Error_INPUTS 1
/***************************************
* Registers
***************************************/
/* Status Register */
#define SCSI_Parity_Error_Status (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
#define SCSI_Parity_Error_Status_PTR ( (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
#define SCSI_Parity_Error_Status_Mask (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__MASK_REG )
#define SCSI_Parity_Error_Status_Aux_Ctrl (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG )
#endif /* End CY_STATUS_REG_SCSI_Parity_Error_H */
/* [] END OF FILE */

4
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c
View File

@ -1056,7 +1056,7 @@ const uint8 cy_bootloader[] = {
0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u, 0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u,
0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u, 0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u,
0x70u, 0x47u, 0x00u, 0x00u, 0xA0u, 0x22u, 0x00u, 0x00u, 0x70u, 0x47u, 0x00u, 0x00u, 0xA0u, 0x22u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x32u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x10u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u, 0x10u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u,
0x00u, 0x40u, 0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, 0x00u, 0x40u, 0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u,
0x00u, 0x10u, 0x00u, 0x14u, 0x01u, 0x40u, 0x00u, 0x08u, 0x00u, 0x10u, 0x00u, 0x14u, 0x01u, 0x40u, 0x00u, 0x08u,
@ -1158,7 +1158,7 @@ __attribute__ ((__section__(".cymeta"), used))
#endif #endif
const uint8 cy_metadata[] = { const uint8 cy_metadata[] = {
0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u, 0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u,
0x2Eu, 0x1Fu, 0x9Au, 0x39u}; 0x2Eu, 0x1Fu, 0x9Au, 0x6Bu};
#if defined(__GNUC__) || defined(__ARMCC_VERSION) #if defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((__section__(".cycustnvl"), used)) __attribute__ ((__section__(".cycustnvl"), used))

312
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
View File

@ -71,6 +71,20 @@
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK
#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST
/* USBFS_bus_reset */ /* USBFS_bus_reset */
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 #define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
@ -84,41 +98,32 @@
/* SCSI_CTL_PHASE */ /* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
/* SCSI_Out_Bits */ /* SCSI_Out_Bits */
#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
@ -133,15 +138,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB10_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB10_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB10_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL #define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
/* USBFS_arb_int */ /* USBFS_arb_int */
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -630,34 +635,34 @@
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */ /* SDCard_BSPIM */
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL #define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST #define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB08_MSK #define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB09_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL #define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL #define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL #define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL #define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB09_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL #define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB09_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB08_ST #define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB09_ST
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL #define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL #define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL #define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL #define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL #define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK #define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK #define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK #define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK #define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL #define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB08_CTL #define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB09_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL #define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB08_CTL #define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB09_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL #define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL #define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB08_MSK #define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB09_MSK
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL #define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@ -665,17 +670,11 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u #define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB11_MSK #define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB10_MSK
#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL #define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL #define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB10_ST
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB11_ST
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1 #define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
@ -685,28 +684,32 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB08_MSK #define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB11_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL #define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB08_ST #define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB08_09_A0 #define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB08_09_A1 #define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB11_ST_CTL
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB08_09_D0 #define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB11_ST_CTL
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB08_09_D1 #define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB11_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB09_10_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB08_09_F0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB09_10_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB08_09_F1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB09_10_D0
#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB08_A0_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB09_10_D1
#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB08_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB08_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB09_10_F0
#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB08_D0_D1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB09_10_F1
#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB08_D0 #define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB09_A0_A1
#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB08_D1 #define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB09_A0
#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB08_ACTL #define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB09_A1
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB08_F0_F1 #define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB09_D0_D1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB08_F0 #define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB09_D0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB08_F1 #define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB09_D1
#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL #define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB09_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB09_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB09_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB09_F1
#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
/* USBFS_dp_int */ /* USBFS_dp_int */
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -1184,21 +1187,21 @@
#define SD_Data_Clk__PM_STBY_MSK 0x01u #define SD_Data_Clk__PM_STBY_MSK 0x01u
/* timer_clock */ /* timer_clock */
#define timer_clock__CFG0 CYREG_CLKDIST_DCFG1_CFG0 #define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
#define timer_clock__CFG1 CYREG_CLKDIST_DCFG1_CFG1 #define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
#define timer_clock__CFG2 CYREG_CLKDIST_DCFG1_CFG2 #define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
#define timer_clock__CFG2_SRC_SEL_MASK 0x07u #define timer_clock__CFG2_SRC_SEL_MASK 0x07u
#define timer_clock__INDEX 0x01u #define timer_clock__INDEX 0x02u
#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2 #define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define timer_clock__PM_ACT_MSK 0x02u #define timer_clock__PM_ACT_MSK 0x04u
#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define timer_clock__PM_STBY_MSK 0x02u #define timer_clock__PM_STBY_MSK 0x04u
/* scsiTarget */ /* scsiTarget */
#define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__MASK 0x01u
#define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL #define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST #define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__MASK 0x04u
@ -1208,54 +1211,54 @@
#define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu #define scsiTarget_StatusReg__MASK 0x1Fu
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB13_MSK #define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL #define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB13_ST #define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST
#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL #define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST #define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB14_MSK #define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB11_MSK
#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL #define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL #define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL #define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB14_ST_CTL #define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB14_ST_CTL #define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB14_ST #define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB11_ST
#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL #define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL #define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL #define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL #define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL #define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK #define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK #define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK #define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK #define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL #define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB14_CTL #define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB11_CTL
#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL #define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB14_CTL #define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB11_CTL
#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL #define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL #define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB14_MSK #define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB11_MSK
#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL #define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB14_15_A0 #define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB11_12_A0
#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB14_15_A1 #define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB11_12_A1
#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB14_15_D0 #define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB11_12_D0
#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB14_15_D1 #define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB11_12_D1
#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL #define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB14_15_F0 #define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB11_12_F0
#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB14_15_F1 #define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB11_12_F1
#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB14_A0_A1 #define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB11_A0_A1
#define scsiTarget_datapath__A0_REG CYREG_B0_UDB14_A0 #define scsiTarget_datapath__A0_REG CYREG_B0_UDB11_A0
#define scsiTarget_datapath__A1_REG CYREG_B0_UDB14_A1 #define scsiTarget_datapath__A1_REG CYREG_B0_UDB11_A1
#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB14_D0_D1 #define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB11_D0_D1
#define scsiTarget_datapath__D0_REG CYREG_B0_UDB14_D0 #define scsiTarget_datapath__D0_REG CYREG_B0_UDB11_D0
#define scsiTarget_datapath__D1_REG CYREG_B0_UDB14_D1 #define scsiTarget_datapath__D1_REG CYREG_B0_UDB11_D1
#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB14_ACTL #define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB14_F0_F1 #define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB11_F0_F1
#define scsiTarget_datapath__F0_REG CYREG_B0_UDB14_F0 #define scsiTarget_datapath__F0_REG CYREG_B0_UDB11_F0
#define scsiTarget_datapath__F1_REG CYREG_B0_UDB14_F1 #define scsiTarget_datapath__F1_REG CYREG_B0_UDB11_F1
#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL #define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL #define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
/* USBFS_ep_0 */ /* USBFS_ep_0 */
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -1493,6 +1496,17 @@
#define SCSI_ATN__SHIFT 0 #define SCSI_ATN__SHIFT 0
#define SCSI_ATN__SLW CYREG_PRT2_SLW #define SCSI_ATN__SLW CYREG_PRT2_SLW
/* SCSI_CLK */
#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
#define SCSI_CLK__INDEX 0x01u
#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define SCSI_CLK__PM_ACT_MSK 0x02u
#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define SCSI_CLK__PM_STBY_MSK 0x02u
/* SCSI_Out */ /* SCSI_Out */
#define SCSI_Out__0__AG CYREG_PRT15_AG #define SCSI_Out__0__AG CYREG_PRT15_AG
#define SCSI_Out__0__AMUX CYREG_PRT15_AMUX #define SCSI_Out__0__AMUX CYREG_PRT15_AMUX

2476
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
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File diff suppressed because it is too large Load Diff

312
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
View File

@ -71,6 +71,20 @@
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK
.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST
/* USBFS_bus_reset */ /* USBFS_bus_reset */
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 .set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
@ -84,41 +98,32 @@
/* SCSI_CTL_PHASE */ /* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
/* SCSI_Out_Bits */ /* SCSI_Out_Bits */
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
@ -133,15 +138,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB10_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB10_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB10_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL .set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
/* USBFS_arb_int */ /* USBFS_arb_int */
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -630,34 +635,34 @@
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */ /* SDCard_BSPIM */
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL .set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST .set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB08_MSK .set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB09_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL .set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL .set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL .set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL .set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB09_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL .set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB09_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB08_ST .set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB09_ST
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL .set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL .set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL .set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL .set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL .set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK .set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK .set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK .set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK .set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL .set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB08_CTL .set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB09_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL .set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB08_CTL .set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB09_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL .set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL .set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB08_MSK .set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB09_MSK
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL .set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@ -665,17 +670,11 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70 .set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB11_MSK .set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB10_MSK
.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL .set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL .set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB10_ST
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB11_ST
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1 .set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
@ -685,28 +684,32 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F .set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB08_MSK .set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB11_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL .set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB08_ST .set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB08_09_A0 .set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB08_09_A1 .set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB11_ST_CTL
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB08_09_D0 .set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB11_ST_CTL
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB08_09_D1 .set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB11_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB09_10_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB08_09_F0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB09_10_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB08_09_F1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB09_10_D0
.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB08_A0_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB09_10_D1
.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB08_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB08_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB09_10_F0
.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB08_D0_D1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB09_10_F1
.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB08_D0 .set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB09_A0_A1
.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB08_D1 .set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB09_A0
.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB08_ACTL .set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB09_A1
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB08_F0_F1 .set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB09_D0_D1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB08_F0 .set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB09_D0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB08_F1 .set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB09_D1
.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL .set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB09_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB09_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB09_F1
.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
/* USBFS_dp_int */ /* USBFS_dp_int */
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -1184,21 +1187,21 @@
.set SD_Data_Clk__PM_STBY_MSK, 0x01 .set SD_Data_Clk__PM_STBY_MSK, 0x01
/* timer_clock */ /* timer_clock */
.set timer_clock__CFG0, CYREG_CLKDIST_DCFG1_CFG0 .set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
.set timer_clock__CFG1, CYREG_CLKDIST_DCFG1_CFG1 .set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
.set timer_clock__CFG2, CYREG_CLKDIST_DCFG1_CFG2 .set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2
.set timer_clock__CFG2_SRC_SEL_MASK, 0x07 .set timer_clock__CFG2_SRC_SEL_MASK, 0x07
.set timer_clock__INDEX, 0x01 .set timer_clock__INDEX, 0x02
.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2 .set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
.set timer_clock__PM_ACT_MSK, 0x02 .set timer_clock__PM_ACT_MSK, 0x04
.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set timer_clock__PM_STBY_MSK, 0x02 .set timer_clock__PM_STBY_MSK, 0x04
/* scsiTarget */ /* scsiTarget */
.set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__MASK, 0x01
.set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL .set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST .set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__MASK, 0x04
@ -1208,54 +1211,54 @@
.set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F .set scsiTarget_StatusReg__MASK, 0x1F
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB13_MSK .set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL .set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB13_ST .set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST
.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL .set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST .set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB14_MSK .set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB11_MSK
.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL .set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL .set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL .set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB14_ST_CTL .set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB14_ST_CTL .set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB14_ST .set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB11_ST
.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL .set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL .set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL .set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL .set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL .set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK .set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK .set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK .set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK .set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL .set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB14_CTL .set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB11_CTL
.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL .set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB14_CTL .set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB11_CTL
.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL .set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL .set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB14_MSK .set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB11_MSK
.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL .set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB14_15_A0 .set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB11_12_A0
.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB14_15_A1 .set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB11_12_A1
.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB14_15_D0 .set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB11_12_D0
.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB14_15_D1 .set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB11_12_D1
.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL .set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB14_15_F0 .set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB11_12_F0
.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB14_15_F1 .set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB11_12_F1
.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB14_A0_A1 .set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB11_A0_A1
.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB14_A0 .set scsiTarget_datapath__A0_REG, CYREG_B0_UDB11_A0
.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB14_A1 .set scsiTarget_datapath__A1_REG, CYREG_B0_UDB11_A1
.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB14_D0_D1 .set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB11_D0_D1
.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB14_D0 .set scsiTarget_datapath__D0_REG, CYREG_B0_UDB11_D0
.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB14_D1 .set scsiTarget_datapath__D1_REG, CYREG_B0_UDB11_D1
.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB14_ACTL .set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB14_F0_F1 .set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB11_F0_F1
.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB14_F0 .set scsiTarget_datapath__F0_REG, CYREG_B0_UDB11_F0
.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB14_F1 .set scsiTarget_datapath__F1_REG, CYREG_B0_UDB11_F1
.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL .set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL .set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
/* USBFS_ep_0 */ /* USBFS_ep_0 */
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -1493,6 +1496,17 @@
.set SCSI_ATN__SHIFT, 0 .set SCSI_ATN__SHIFT, 0
.set SCSI_ATN__SLW, CYREG_PRT2_SLW .set SCSI_ATN__SLW, CYREG_PRT2_SLW
/* SCSI_CLK */
.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
.set SCSI_CLK__INDEX, 0x01
.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
.set SCSI_CLK__PM_ACT_MSK, 0x02
.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set SCSI_CLK__PM_STBY_MSK, 0x02
/* SCSI_Out */ /* SCSI_Out */
.set SCSI_Out__0__AG, CYREG_PRT15_AG .set SCSI_Out__0__AG, CYREG_PRT15_AG
.set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX .set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX

312
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
View File

@ -71,6 +71,20 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
/* USBFS_bus_reset */ /* USBFS_bus_reset */
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@ -84,41 +98,32 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_CTL_PHASE */ /* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
/* SCSI_Out_Bits */ /* SCSI_Out_Bits */
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
@ -133,15 +138,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
/* USBFS_arb_int */ /* USBFS_arb_int */
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -630,34 +635,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */ /* SDCard_BSPIM */
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB09_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB09_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB09_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB09_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB09_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB09_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB09_MSK
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -665,17 +670,11 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@ -685,28 +684,32 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0 SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1 SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0 SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1 SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB08_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB08_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1 SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB08_D0 SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB08_D1 SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1 SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB08_F0 SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB08_F1 SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
/* USBFS_dp_int */ /* USBFS_dp_int */
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -1184,21 +1187,21 @@ SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SD_Data_Clk__PM_STBY_MSK EQU 0x01 SD_Data_Clk__PM_STBY_MSK EQU 0x01
/* timer_clock */ /* timer_clock */
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
timer_clock__CFG2_SRC_SEL_MASK EQU 0x07 timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
timer_clock__INDEX EQU 0x01 timer_clock__INDEX EQU 0x02
timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
timer_clock__PM_ACT_MSK EQU 0x02 timer_clock__PM_ACT_MSK EQU 0x04
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
timer_clock__PM_STBY_MSK EQU 0x02 timer_clock__PM_STBY_MSK EQU 0x04
/* scsiTarget */ /* scsiTarget */
scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__MASK EQU 0x04
@ -1208,54 +1211,54 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB14_MSK scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB14_ST scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB14_CTL scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB14_CTL scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB14_MSK scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB14_15_A0 scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB14_15_A1 scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB14_15_D0 scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB14_15_D1 scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB14_15_F0 scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB14_15_F1 scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB14_A0_A1 scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB14_A0 scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB14_A1 scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB14_D0_D1 scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB14_D0 scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB14_D1 scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB14_F0_F1 scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB14_F0 scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB14_F1 scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
/* USBFS_ep_0 */ /* USBFS_ep_0 */
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -1493,6 +1496,17 @@ SCSI_ATN__PS EQU CYREG_PRT2_PS
SCSI_ATN__SHIFT EQU 0 SCSI_ATN__SHIFT EQU 0
SCSI_ATN__SLW EQU CYREG_PRT2_SLW SCSI_ATN__SLW EQU CYREG_PRT2_SLW
/* SCSI_CLK */
SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
SCSI_CLK__INDEX EQU 0x01
SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
SCSI_CLK__PM_ACT_MSK EQU 0x02
SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SCSI_CLK__PM_STBY_MSK EQU 0x02
/* SCSI_Out */ /* SCSI_Out */
SCSI_Out__0__AG EQU CYREG_PRT15_AG SCSI_Out__0__AG EQU CYREG_PRT15_AG
SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX

312
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
View File

@ -71,6 +71,20 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
; USBFS_bus_reset ; USBFS_bus_reset
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@ -84,41 +98,32 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_CTL_PHASE ; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
; SCSI_Out_Bits ; SCSI_Out_Bits
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
@ -133,15 +138,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
; USBFS_arb_int ; USBFS_arb_int
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -630,34 +635,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SDCard_BSPIM ; SDCard_BSPIM
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB09_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB09_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB09_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB09_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB09_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB09_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB09_MSK
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -665,17 +670,11 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@ -685,28 +684,32 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0 SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1 SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0 SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1 SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB08_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB08_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1 SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB08_D0 SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB08_D1 SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1 SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB08_F0 SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB08_F1 SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
; USBFS_dp_int ; USBFS_dp_int
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -1184,21 +1187,21 @@ SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SD_Data_Clk__PM_STBY_MSK EQU 0x01 SD_Data_Clk__PM_STBY_MSK EQU 0x01
; timer_clock ; timer_clock
timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
timer_clock__CFG2_SRC_SEL_MASK EQU 0x07 timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
timer_clock__INDEX EQU 0x01 timer_clock__INDEX EQU 0x02
timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
timer_clock__PM_ACT_MSK EQU 0x02 timer_clock__PM_ACT_MSK EQU 0x04
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
timer_clock__PM_STBY_MSK EQU 0x02 timer_clock__PM_STBY_MSK EQU 0x04
; scsiTarget ; scsiTarget
scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__MASK EQU 0x04
@ -1208,54 +1211,54 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB14_MSK scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB14_ST scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB14_CTL scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB14_CTL scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB14_MSK scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB14_15_A0 scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB14_15_A1 scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB14_15_D0 scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB14_15_D1 scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB14_15_F0 scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB14_15_F1 scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB14_A0_A1 scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB14_A0 scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB14_A1 scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB14_D0_D1 scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB14_D0 scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB14_D1 scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB14_F0_F1 scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB14_F0 scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB14_F1 scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
; USBFS_ep_0 ; USBFS_ep_0
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -1493,6 +1496,17 @@ SCSI_ATN__PS EQU CYREG_PRT2_PS
SCSI_ATN__SHIFT EQU 0 SCSI_ATN__SHIFT EQU 0
SCSI_ATN__SLW EQU CYREG_PRT2_SLW SCSI_ATN__SLW EQU CYREG_PRT2_SLW
; SCSI_CLK
SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
SCSI_CLK__INDEX EQU 0x01
SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
SCSI_CLK__PM_ACT_MSK EQU 0x02
SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
SCSI_CLK__PM_STBY_MSK EQU 0x02
; SCSI_Out ; SCSI_Out
SCSI_Out__0__AG EQU CYREG_PRT15_AG SCSI_Out__0__AG EQU CYREG_PRT15_AG
SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX

2
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
View File

@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used))
const uint8 cy_meta_loadable[] = { const uint8 cy_meta_loadable[] = {
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x52u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x03u,
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,

2
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
View File

@ -37,6 +37,7 @@
#include <SD_SCK.h> #include <SD_SCK.h>
#include <SD_MOSI_aliases.h> #include <SD_MOSI_aliases.h>
#include <SD_MOSI.h> #include <SD_MOSI.h>
#include <SCSI_CLK.h>
#include <SCSI_RST_aliases.h> #include <SCSI_RST_aliases.h>
#include <SCSI_RST.h> #include <SCSI_RST.h>
#include <SCSI_ATN_aliases.h> #include <SCSI_ATN_aliases.h>
@ -67,6 +68,7 @@
#include <Debug_Timer_Interrupt.h> #include <Debug_Timer_Interrupt.h>
#include <EXTLED_aliases.h> #include <EXTLED_aliases.h>
#include <EXTLED.h> #include <EXTLED.h>
#include <SCSI_Parity_Error.h>
#include <USBFS_Dm_aliases.h> #include <USBFS_Dm_aliases.h>
#include <USBFS_Dm.h> #include <USBFS_Dm.h>
#include <USBFS_Dp_aliases.h> #include <USBFS_Dp_aliases.h>

44
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
View File

@ -18,7 +18,7 @@
<Tool Name="postbuild" Command="" Options="" /> <Tool Name="postbuild" Command="" Options="" />
</Toolchain> </Toolchain>
</Toolchains> </Toolchains>
<Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable"> <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
<CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File> <CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
<Datasheet /> <Datasheet />
<LinkerFiles> <LinkerFiles>
@ -27,8 +27,8 @@
<LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile> <LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
</LinkerFiles> </LinkerFiles>
<Folders> <Folders>
<Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\src"> <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\src">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn"> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">..\..\src\main.c</File> <File BuildType="BUILD" Toolchain="">..\..\src\main.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.c</File> <File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\disk.c</File> <File BuildType="BUILD" Toolchain="">..\..\src\disk.c</File>
@ -55,13 +55,13 @@
<File BuildType="BUILD" Toolchain="">..\..\src\config.h</File> <File BuildType="BUILD" Toolchain="">..\..\src\config.h</File>
</Files> </Files>
</Folder> </Folder>
<Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn"> <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn"> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">.\device.h</File> <File BuildType="BUILD" Toolchain="">.\device.h</File>
</Files> </Files>
</Folder> </Folder>
<Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5"> <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn"> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cybootloader.c</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cybootloader.c</File>
@ -199,47 +199,51 @@
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED_aliases.h</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED.c</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED.h</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Parity_Error.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Parity_Error.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_CLK.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_CLK.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\prebuild.bat</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\prebuild.bat</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\postbuild.bat</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\postbuild.bat</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyElfTool.exe</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyElfTool.exe</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File> <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>
</Files> </Files>
</Folder> </Folder>
<Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC"> <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn"> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File> <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>
</Files> </Files>
</Folder> </Folder>
<Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK"> <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn"> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File> <File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>
</Files> </Files>
</Folder> </Folder>
<Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR"> <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn"> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File> <File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>
</Files> </Files>
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\codegentemp"> <Folder BuildType="EXCLUDE" Path=".\codegentemp">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441"> <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473"> <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951"> <Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\DP8051"> <Folder BuildType="EXCLUDE" Path=".\DP8051">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\CortexM0"> <Folder BuildType="EXCLUDE" Path=".\CortexM0">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder> </Folder>
<Folder BuildType="EXCLUDE" Path=".\CortexM3"> <Folder BuildType="EXCLUDE" Path=".\CortexM3">
<Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" /> <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder> </Folder>
</Folders> </Folders>
</Project> </Project>

76
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
View File

@ -1,9 +1,18 @@
<?xml version="1.0" encoding="utf-8"?> <?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap"> <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
</block>
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true"> <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@ -84,21 +93,46 @@
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" /> <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" /> <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
</block> </block>
<block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true"> <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
</block>
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006462" bitWidth="8" desc="" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006482" bitWidth="8" desc="" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006492" bitWidth="8" desc="">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
<field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
<value name="ENABLED" value="1" desc="Interrupt enabled" />
<value name="DISABLED" value="0" desc="Interrupt disabled" />
</field>
<field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
</field>
<field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
<field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
<value name="ENABLED" value="1" desc="Clear FIFO state" />
<value name="DISABLED" value="0" desc="Normal FIFO operation" />
</field>
</register>
</block>
<block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657B" bitWidth="8" desc="" />
</block>
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true"> <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@ -156,19 +190,15 @@
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" /> <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" /> <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
</block> </block>
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true"> <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006579" bitWidth="8" desc="" /> <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006579" bitWidth="8" desc="" />
</block> </block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true"> <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657A" bitWidth="8" desc="" />
</block>
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true"> <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" /> <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
</block> </block>
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@ -177,7 +207,7 @@
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" /> <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />

BIN
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit
View File

Binary file not shown.

60
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
View File

@ -2085,6 +2085,66 @@
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<filters /> <filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0> </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error" persistent="">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
<dependencies>
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error.c" persistent=".\Generated_Source\PSoC5\SCSI_Parity_Error.c">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
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<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error.h" persistent=".\Generated_Source\PSoC5\SCSI_Parity_Error.h">
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<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CLK" persistent="">
<Hidden v="False" />
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<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
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<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CLK.c" persistent=".\Generated_Source\PSoC5\SCSI_CLK.c">
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199
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
View File

@ -490,6 +490,182 @@
</register> </register>
</registers> </registers>
</peripheral> </peripheral>
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
<baseAddress>0x40006462</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x31</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Parity_Error_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Parity_Error_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x30</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>FIFO0</name>
<description>FIFO0 clear</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Enable counter</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Disable counter</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INTRENBL</name>
<description>Enables or disables the Interrupt</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Interrupt enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Interrupt disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1LEVEL</name>
<description>FIFO level</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0LEVEL</name>
<description>FIFO level</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO1CLEAR</name>
<description>FIFO clear</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FIFO0CLEAR</name>
<description>FIFO clear</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>ENABLED</name>
<description>Clear FIFO state</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DISABLED</name>
<description>Normal FIFO operation</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x4000657B</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Out_Bits_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral> <peripheral>
<name>Debug_Timer</name> <name>Debug_Timer</name>
<description>No description available</description> <description>No description available</description>
@ -803,31 +979,10 @@
</register> </register>
</registers> </registers>
</peripheral> </peripheral>
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x4000657A</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCSI_Out_Bits_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
<peripheral> <peripheral>
<name>SCSI_CTL_PHASE</name> <name>SCSI_CTL_PHASE</name>
<description>No description available</description> <description>No description available</description>
<baseAddress>0x4000647B</baseAddress> <baseAddress>0x40006472</baseAddress>
<addressBlock> <addressBlock>
<offset>0</offset> <offset>0</offset>
<size>0x1</size> <size>0x1</size>

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software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
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software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit
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