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cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
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Design Name: WarpSE Date: 9- 9-2023, 8:19AM
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Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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125/144 ( 87%) 441 /720 ( 61%) 271/432 ( 63%) 103/144 ( 72%) 70 /81 ( 86%)
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** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 32/54 28/90 11/11*
FB2 11/18 13/54 12/90 8/10
FB3 18/18* 40/54 66/90 10/10*
FB4 11/18 39/54 82/90 10/10*
FB5 14/18 39/54 81/90 8/10
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FB6 18/18* 36/54 68/90 10/10*
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FB7 18/18* 32/54 42/90 7/10
FB8 17/18 40/54 62/90 6/10
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----- ----- ----- -----
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125/144 271/432 441/720 70/81
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* - Resource is exhausted
** Global Control Resources **
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Signal 'C16M' mapped onto global clock net GCK1.
Signal 'C8M' mapped onto global clock net GCK2.
Signal 'FCLK' mapped onto global clock net GCK3.
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Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
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Input : 32 32 | I/O : 64 73
Output : 34 34 | GCK/IO : 3 3
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Bidirectional : 1 1 | GTS/IO : 3 4
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GCK : 3 3 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
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Total 70 70
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** Power Data **
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There are 125 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'WarpSE.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'C16M' based upon the LOC
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constraint 'P22'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'C8M' based upon the LOC
constraint 'P23'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'FCLK' based upon the LOC
constraint 'P27'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
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WARNING:Cpld:1007 - Removing unused input(s) 'C20MEN'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'SW< 1 > '. The input(s) are unused
after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'SW< 2 > '. The input(s) are unused
after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'SW< 3 > '. The input(s) are unused
after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'nBG_IOB'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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** 35 Outputs **
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
nDTACK_FSB 9 18 FB3_9 28 I/O O STD FAST RESET
nROMWE 1 2 FB3_17 34 I/O O STD FAST
nAoutOE 2 4 FB4_2 87 I/O O STD FAST SET
nDoutOE 2 5 FB4_5 89 I/O O STD FAST
nDinOE 3 7 FB4_6 90 I/O O STD FAST
nRES 1 1 FB4_8 91 I/O I/O STD FAST
nVPA_FSB 3 12 FB4_11 93 I/O O STD FAST RESET
nROMCS 2 5 FB5_2 35 I/O O STD FAST
nCAS 15 17 FB5_5 36 I/O O STD FAST RESET
nOE 3 5 FB5_6 37 I/O O STD FAST RESET
RA< 4 > 2 3 FB5_9 40 I/O O STD FAST
RA< 3 > 2 3 FB5_11 41 I/O O STD FAST
RA< 5 > 2 3 FB5_12 42 I/O O STD FAST
RA< 2 > 2 3 FB5_14 43 I/O O STD FAST
RA< 6 > 2 3 FB5_15 46 I/O O STD FAST
nVMA_IOB 3 8 FB6_2 74 I/O O STD FAST RESET
nLDS_IOB 6 10 FB6_9 79 I/O O STD FAST RESET
nUDS_IOB 6 10 FB6_11 80 I/O O STD FAST RESET
nAS_IOB 4 9 FB6_12 81 I/O O STD FAST RESET
nADoutLE1 2 3 FB6_14 82 I/O O STD FAST SET
nADoutLE0 1 2 FB6_15 85 I/O O STD FAST
nDinLE 1 2 FB6_17 86 I/O O STD FAST RESET
RA< 1 > 2 3 FB7_2 50 I/O O STD FAST
RA< 7 > 2 3 FB7_5 52 I/O O STD FAST
RA< 0 > 2 3 FB7_6 53 I/O O STD FAST
RA< 8 > 2 3 FB7_8 54 I/O O STD FAST
RA< 10 > 2 3 FB7_9 55 I/O O STD FAST
RA< 9 > 2 3 FB7_11 56 I/O O STD FAST
C25MEN 0 0 FB7_12 58 I/O O STD FAST
RA< 11 > 2 3 FB8_2 63 I/O O STD FAST
nRAS 3 7 FB8_5 64 I/O O STD FAST
nRAMLWE 1 3 FB8_6 65 I/O O STD FAST
nRAMUWE 1 3 FB8_8 66 I/O O STD FAST
nBERR_FSB 3 5 FB8_12 70 I/O O STD FAST RESET
nBR_IOB 2 4 FB8_15 72 I/O O STD FAST RESET
** 90 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
ram/RS_FSM_FFd4 1 2 FB1_1 STD RESET
ram/RS_FSM_FFd3 1 1 FB1_2 STD RESET
ram/RS_FSM_FFd2 1 1 FB1_3 STD RESET
ram/RS_FSM_FFd1 1 1 FB1_4 STD RESET
ram/RASrf 1 1 FB1_5 STD RESET
iobm/Er 1 1 FB1_6 STD RESET
cnt/nIPL2r 1 1 FB1_7 STD RESET
cnt/IS_FSM_FFd1 1 7 FB1_8 STD RESET
cnt/Er< 0 > 1 1 FB1_9 STD RESET
ram/RefDone 2 7 FB1_10 STD RESET
ram/RS_FSM_FFd5 2 3 FB1_11 STD RESET
iobs/IOU1 2 2 FB1_12 STD RESET
iobs/IOL1 2 2 FB1_13 STD RESET
cnt/Timer< 0 > 2 4 FB1_14 STD RESET
cnt/IS_FSM_FFd2 2 6 FB1_15 STD RESET
RefUrg 2 5 FB1_16 STD RESET
IOBERR 2 2 FB1_17 STD RESET
iobm/ES< 2 > 3 5 FB1_18 STD RESET
ram/DTACKr 1 1 FB2_8 STD RESET
iobs/IODONEr 1 1 FB2_9 STD RESET
iobs/IOACTr 1 1 FB2_10 STD RESET
iobm/VPAr 1 1 FB2_11 STD RESET
iobm/IOWRREQr 1 1 FB2_12 STD RESET
iobm/IOS_FSM_FFd5 1 1 FB2_13 STD RESET
iobm/IOS_FSM_FFd4 1 1 FB2_14 STD RESET
iobm/IOS_FSM_FFd1 1 1 FB2_15 STD RESET
iobm/IORDREQr 1 1 FB2_16 STD RESET
iobm/C8Mr 1 1 FB2_17 STD RESET
iobm/IOS_FSM_FFd2 2 4 FB2_18 STD RESET
cnt/QS< 1 > 13 24 FB3_1 STD RESET
cnt/LTimer< 0 > 1 3 FB3_2 STD RESET
cnt/Er< 1 > 1 1 FB3_3 STD RESET
cnt/LTimer< 6 > 2 9 FB3_4 STD RESET
cnt/LTimer< 5 > 2 8 FB3_5 STD RESET
cnt/LTimer< 4 > 2 7 FB3_6 STD RESET
cnt/LTimer< 3 > 2 6 FB3_7 STD RESET
cnt/LTimer< 2 > 2 5 FB3_8 STD RESET
cnt/LTimer< 1 > 2 4 FB3_10 STD RESET
cnt/Wait< 4 > 3 7 FB3_11 STD RESET
cnt/Wait< 3 > 3 6 FB3_12 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
cnt/Wait< 2 > 3 5 FB3_13 STD RESET
cnt/Wait< 1 > 3 4 FB3_14 STD RESET
QoSReady 4 10 FB3_15 STD RESET
cnt/QS< 0 > 12 24 FB3_16 STD RESET
fsb/ASrf 1 1 FB3_18 STD RESET
cs/nOverlay 3 8 FB4_1 STD RESET
IOU0 16 21 FB4_4 STD RESET
IOL0 16 21 FB4_9 STD RESET
IOWRREQ 15 21 FB4_13 STD RESET
iobs/TS_FSM_FFd2 13 19 FB4_16 STD RESET
iobs/IORW1 8 18 FB4_17 STD RESET
ram/RS_FSM_FFd8 13 13 FB5_1 STD SET
cnt/Wait< 0 > 1 3 FB5_8 STD RESET
ram/RASEN 10 12 FB5_10 STD RESET
RAMReady 10 14 FB5_13 STD RESET
IONPReady 5 16 FB5_16 STD RESET
ram/RASrr 12 13 FB5_18 STD RESET
iobm/IOS_FSM_FFd6 2 5 FB6_1 STD RESET
iobm/IOS_FSM_FFd7 3 6 FB6_3 STD SET
iobm/IOS_FSM_FFd3 3 5 FB6_4 STD RESET
iobm/ES< 0 > 3 6 FB6_5 STD RESET
iobm/ES< 3 > 4 6 FB6_6 STD RESET
iobm/ES< 1 > 4 6 FB6_7 STD RESET
iobm/DoutOE 4 8 FB6_8 STD RESET
IODONE 4 8 FB6_10 STD RESET
iobm/IOS0 5 12 FB6_13 STD RESET
ALE0M 5 11 FB6_16 STD RESET
IOACT 8 14 FB6_18 STD RESET
cnt/TimerTC 2 6 FB7_1 STD RESET
cnt/LTimerTC 2 15 FB7_3 STD RESET
cnt/LTimer< 9 > 2 12 FB7_4 STD RESET
cnt/LTimer< 8 > 2 11 FB7_7 STD RESET
cnt/LTimer< 7 > 2 10 FB7_10 STD RESET
cnt/LTimer< 11 > 2 14 FB7_13 STD RESET
cnt/LTimer< 10 > 2 13 FB7_14 STD RESET
RefReq 2 6 FB7_15 STD RESET
cnt/Timer< 1 > 4 5 FB7_16 STD RESET
cnt/Timer< 3 > 5 7 FB7_17 STD RESET
cnt/Timer< 2 > 5 6 FB7_18 STD RESET
IORDREQ 9 15 FB8_3 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
ram/RS_FSM_FFd7 9 11 FB8_4 STD RESET
iobs/Load1 8 17 FB8_7 STD RESET
ram/RASEL 3 8 FB8_9 STD RESET
iobs/TS_FSM_FFd1 2 3 FB8_10 STD RESET
ram/RS_FSM_FFd6 2 7 FB8_11 STD RESET
ALE0S 1 1 FB8_13 STD RESET
BACTr 1 2 FB8_14 STD RESET
iobs/Clear1 1 2 FB8_16 STD RESET
nRESout 1 2 FB8_17 STD RESET
iobs/Sent 13 18 FB8_18 STD RESET
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** 35 Inputs **
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Signal Loc Pin Pin Pin
Name No. Type Use
A_FSB< 13 > FB1_2 11 I/O I
A_FSB< 14 > FB1_3 12 I/O I
A_FSB< 15 > FB1_5 13 I/O I
A_FSB< 16 > FB1_6 14 I/O I
A_FSB< 17 > FB1_8 15 I/O I
A_FSB< 18 > FB1_9 16 I/O I
A_FSB< 19 > FB1_11 17 I/O I
A_FSB< 20 > FB1_12 18 I/O I
A_FSB< 21 > FB1_14 19 I/O I
A_FSB< 22 > FB1_15 20 I/O I
C16M FB1_17 22 GCK/I/O GCK
A_FSB< 5 > FB2_6 2 GTS/I/O I
A_FSB< 6 > FB2_8 3 GTS/I/O I
A_FSB< 7 > FB2_9 4 GTS/I/O I
A_FSB< 8 > FB2_11 6 I/O I
A_FSB< 9 > FB2_12 7 I/O I
A_FSB< 10 > FB2_14 8 I/O I
A_FSB< 11 > FB2_15 9 I/O I
A_FSB< 12 > FB2_17 10 I/O I
C8M FB3_2 23 GCK/I/O GCK/I
A_FSB< 23 > FB3_5 24 I/O I
E FB3_6 25 I/O I
FCLK FB3_8 27 GCK/I/O GCK
nWE_FSB FB3_11 29 I/O I
nLDS_FSB FB3_12 30 I/O I
nAS_FSB FB3_14 32 I/O I
nUDS_FSB FB3_15 33 I/O I
nIPL2 FB4_9 92 I/O I
A_FSB< 1 > FB4_12 94 I/O I
A_FSB< 2 > FB4_14 95 I/O I
A_FSB< 3 > FB4_15 96 I/O I
A_FSB< 4 > FB4_17 97 I/O I
nBERR_IOB FB6_5 76 I/O I
nVPA_IOB FB6_6 77 I/O I
nDTACK_IOB FB6_8 78 I/O I
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Legend:
Pin No. - ~ - User Assigned
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
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Number of function block inputs used/remaining: 32/22
Number of signals used by logic mapping into function block: 32
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
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ram/RS_FSM_FFd4 1 0 0 4 FB1_1 (b) (b)
ram/RS_FSM_FFd3 1 0 0 4 FB1_2 11 I/O I
ram/RS_FSM_FFd2 1 0 0 4 FB1_3 12 I/O I
ram/RS_FSM_FFd1 1 0 0 4 FB1_4 (b) (b)
ram/RASrf 1 0 0 4 FB1_5 13 I/O I
iobm/Er 1 0 0 4 FB1_6 14 I/O I
cnt/nIPL2r 1 0 0 4 FB1_7 (b) (b)
cnt/IS_FSM_FFd1 1 0 0 4 FB1_8 15 I/O I
cnt/Er< 0 > 1 0 0 4 FB1_9 16 I/O I
ram/RefDone 2 0 0 3 FB1_10 (b) (b)
ram/RS_FSM_FFd5 2 0 0 3 FB1_11 17 I/O I
iobs/IOU1 2 0 0 3 FB1_12 18 I/O I
iobs/IOL1 2 0 0 3 FB1_13 (b) (b)
cnt/Timer< 0 > 2 0 0 3 FB1_14 19 I/O I
cnt/IS_FSM_FFd2 2 0 0 3 FB1_15 20 I/O I
RefUrg 2 0 0 3 FB1_16 (b) (b)
IOBERR 2 0 0 3 FB1_17 22 GCK/I/O GCK
iobm/ES< 2 > 3 0 0 2 FB1_18 (b) (b)
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Signals Used by Logic in Function Block
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1: E 12: cnt/Timer< 3 > 23: nLDS_FSB
2: RefReq 13: cnt/TimerTC 24: nUDS_FSB
3: RefUrg 14: cnt/nIPL2r 25: ram/DTACKr
4: cnt/Er< 0 > 15: iobm/ES< 0 > 26: ram/RS_FSM_FFd1
5: cnt/Er< 1 > 16: iobm/ES< 1 > 27: ram/RS_FSM_FFd2
6: cnt/IS_FSM_FFd1 17: iobm/ES< 2 > 28: ram/RS_FSM_FFd3
7: cnt/IS_FSM_FFd2 18: iobm/Er 29: ram/RS_FSM_FFd5
8: cnt/LTimerTC 19: iobs/Load1 30: ram/RS_FSM_FFd6
9: cnt/Timer< 0 > 20: nAS_IOB 31: ram/RS_FSM_FFd7
10: cnt/Timer< 1 > 21: nBERR_IOB 32: ram/RefDone
11: cnt/Timer< 2 > 22: nIPL2
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
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ram/RS_FSM_FFd4 ........................X...X........... 2
ram/RS_FSM_FFd3 ..............................X......... 1
ram/RS_FSM_FFd2 ...........................X............ 1
ram/RS_FSM_FFd1 ..........................X............. 1
ram/RASrf .............................X.......... 1
iobm/Er X....................................... 1
cnt/nIPL2r .....................X.................. 1
cnt/IS_FSM_FFd1 ...XXXXX....XX.......................... 7
cnt/Er< 0 > X....................................... 1
ram/RefDone .XX......................XXX..XX........ 7
ram/RS_FSM_FFd5 ........................X...XX.......... 3
iobs/IOU1 ..................X....X................ 2
iobs/IOL1 ..................X...X................. 2
cnt/Timer< 0 > ...XX...X...X........................... 4
cnt/IS_FSM_FFd2 ...XXXXX....X........................... 6
RefUrg ...XX....XXX............................ 5
IOBERR ...................XX................... 2
iobm/ES< 2 > X.............XXXX...................... 5
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0----+----1----+----2----+----3----+----4
0 0 0 0
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Number of function block inputs used/remaining: 13/41
Number of signals used by logic mapping into function block: 13
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
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(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 99 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 1 GTS/I/O
(unused) 0 0 0 5 FB2_6 2 GTS/I/O I
(unused) 0 0 0 5 FB2_7 (b)
ram/DTACKr 1 0 0 4 FB2_8 3 GTS/I/O I
iobs/IODONEr 1 0 0 4 FB2_9 4 GTS/I/O I
iobs/IOACTr 1 0 0 4 FB2_10 (b) (b)
iobm/VPAr 1 0 0 4 FB2_11 6 I/O I
iobm/IOWRREQr 1 0 0 4 FB2_12 7 I/O I
iobm/IOS_FSM_FFd5 1 0 0 4 FB2_13 (b) (b)
iobm/IOS_FSM_FFd4 1 0 0 4 FB2_14 8 I/O I
iobm/IOS_FSM_FFd1 1 0 0 4 FB2_15 9 I/O I
iobm/IORDREQr 1 0 0 4 FB2_16 (b) (b)
iobm/C8Mr 1 0 0 4 FB2_17 10 I/O I
iobm/IOS_FSM_FFd2 2 0 0 3 FB2_18 (b) (b)
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Signals Used by Logic in Function Block
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1: C8M 6: IOWRREQ 10: iobm/IOS_FSM_FFd5
2: IOACT 7: iobm/C8Mr 11: iobm/IOS_FSM_FFd6
3: IOBERR 8: iobm/IOS_FSM_FFd2 12: nDTACK_FSB
4: IODONE 9: iobm/IOS_FSM_FFd3 13: nVPA_IOB
5: IORDREQ
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
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ram/DTACKr ...........X............................ 1
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iobs/IODONEr ...X.................................... 1
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iobs/IOACTr .X...................................... 1
iobm/VPAr ............X........................... 1
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iobm/IOWRREQr .....X.................................. 1
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iobm/IOS_FSM_FFd5 ..........X............................. 1
iobm/IOS_FSM_FFd4 .........X.............................. 1
iobm/IOS_FSM_FFd1 .......X................................ 1
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iobm/IORDREQr ....X................................... 1
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iobm/C8Mr X....................................... 1
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iobm/IOS_FSM_FFd2 ..XX..X.X............................... 4
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0----+----1----+----2----+----3----+----4
0 0 0 0
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Number of function block inputs used/remaining: 40/14
Number of signals used by logic mapping into function block: 40
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
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cnt/QS< 1 > 13 8< - 0 0 FB3_1 ( b ) ( b )
cnt/LTimer< 0 > 1 0 /\4 0 FB3_2 23 GCK/I/O GCK/I
cnt/Er< 1 > 1 0 0 4 FB3_3 (b) (b)
cnt/LTimer< 6 > 2 0 0 3 FB3_4 (b) (b)
cnt/LTimer< 5 > 2 0 0 3 FB3_5 24 I/O I
cnt/LTimer< 4 > 2 0 0 3 FB3_6 25 I/O I
cnt/LTimer< 3 > 2 0 0 3 FB3_7 (b) (b)
cnt/LTimer< 2 > 2 0 \/2 1 FB3_8 27 GCK/I/O GCK
nDTACK_FSB 9 4< - 0 0 FB3_9 28 I / O O
cnt/LTimer< 1 > 2 0 /\2 1 FB3_10 (b) (b)
cnt/Wait< 4 > 3 0 0 2 FB3_11 29 I/O I
cnt/Wait< 3 > 3 0 0 2 FB3_12 30 I/O I
cnt/Wait< 2 > 3 0 0 2 FB3_13 (b) (b)
cnt/Wait< 1 > 3 0 \/2 0 FB3_14 32 I/O I
QoSReady 4 2< - \ / 3 0 FB3_15 33 I / O I
cnt/QS< 0 > 12 7< - 0 0 FB3_16 ( b ) ( b )
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nROMWE 1 0 /\4 0 FB3_17 34 I/O O
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fsb/ASrf 1 0 \/4 0 FB3_18 (b) (b)
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Signals Used by Logic in Function Block
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1: A_FSB< 10 > 15: A_FSB< 8 > 28: cnt/QS< 0 >
2: A_FSB< 11 > 16: A_FSB< 9 > 29: cnt/QS< 1 >
3: A_FSB< 12 > 17: IONPReady 30: cnt/TimerTC
4: A_FSB< 13 > 18: QoSReady 31: cnt/Wait< 0 >
5: A_FSB< 14 > 19: RAMReady 32: cnt/Wait< 1 >
6: A_FSB< 15 > 20: cnt/Er< 0 > 33: cnt/Wait< 2 >
7: A_FSB< 16 > 21: cnt/Er< 1 > 34: cnt/Wait< 3 >
8: A_FSB< 17 > 22: cnt/LTimer< 0 > 35: cnt/Wait< 4 >
9: A_FSB< 18 > 23: cnt/LTimer< 1 > 36: fsb/ASrf
10: A_FSB< 19 > 24: cnt/LTimer< 2 > 37: iobs/Sent
11: A_FSB< 20 > 25: cnt/LTimer< 3 > 38: nADoutLE1
12: A_FSB< 21 > 26: cnt/LTimer< 4 > 39: nAS_FSB
13: A_FSB< 22 > 27: cnt/LTimer< 5 > 40: nWE_FSB
14: A_FSB< 23 >
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
cnt/QS< 1 > XXXXXXXXXXXXXXXX...XX......XXX.....X..XX.......... 24
cnt/LTimer< 0 > ...................XX........X.................... 3
cnt/Er< 1 > ...................X.............................. 1
cnt/LTimer< 6 > ...................XXXXXXXX..X.................... 9
cnt/LTimer< 5 > ...................XXXXXXX...X.................... 8
cnt/LTimer< 4 > ...................XXXXXX....X.................... 7
cnt/LTimer< 3 > ...................XXXXX.....X.................... 6
cnt/LTimer< 2 > ...................XXXX......X.................... 5
nDTACK_FSB ...XX.XXXXXXXX..XXX................XXXXX.......... 18
cnt/LTimer< 1 > ...................XXX.......X.................... 4
cnt/Wait< 4 > ..............................XXXXXX..X........... 7
cnt/Wait< 3 > ..............................XXXX.X..X........... 6
cnt/Wait< 2 > ..............................XXX..X..X........... 5
cnt/Wait< 1 > ..............................XX...X..X........... 4
QoSReady .................X.........XX.XXXXXX..X........... 10
cnt/QS< 0 > XXXXXXXXXXXXXXXX...XX......XXX.....X..XX.......... 24
nROMWE ......................................XX.......... 2
fsb/ASrf ......................................X........... 1
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
2023-07-16 03:21:41 +00:00
2023-09-28 06:46:30 +00:00
Number of function block inputs used/remaining: 39/15
Number of signals used by logic mapping into function block: 39
2023-07-16 03:21:41 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
2023-09-28 06:46:30 +00:00
cs/nOverlay 3 0 /\1 1 FB4_1 (b) (b)
nAoutOE 2 0 \/1 2 FB4_2 87 I/O O
(unused) 0 0 \/5 0 FB4_3 (b) (b)
IOU0 16 11< - 0 0 FB4_4 ( b ) ( b )
nDoutOE 2 2< - / \ 5 0 FB4_5 89 I / O O
nDinOE 3 0 /\2 0 FB4_6 90 I/O O
(unused) 0 0 0 5 FB4_7 (b)
nRES 1 0 \/4 0 FB4_8 91 I/O I/O
IOL0 16 11< - 0 0 FB4_9 92 I / O I
(unused) 0 0 /\5 0 FB4_10 (b) (b)
nVPA_FSB 3 0 /\2 0 FB4_11 93 I/O O
(unused) 0 0 \/5 0 FB4_12 94 I/O I
IOWRREQ 15 10< - 0 0 FB4_13 ( b ) ( b )
(unused) 0 0 /\5 0 FB4_14 95 I/O I
2023-07-16 06:25:27 +00:00
(unused) 0 0 \/5 0 FB4_15 96 I/O I
2023-09-28 06:46:30 +00:00
iobs/TS_FSM_FFd2 13 8< - 0 0 FB4_16 ( b ) ( b )
iobs/IORW1 8 6< - / \ 3 0 FB4_17 97 I / O I
(unused) 0 0 /\5 0 FB4_18 (b) (b)
2023-07-16 03:20:51 +00:00
2023-07-16 03:21:41 +00:00
Signals Used by Logic in Function Block
2023-09-28 06:46:30 +00:00
1: A_FSB< 13 > 14: IOWRREQ 27: iobs/IORW1
2: A_FSB< 14 > 15: nRES.PIN 28: iobs/IOU1
3: A_FSB< 16 > 16: QoSReady 29: iobs/Sent
4: A_FSB< 17 > 17: cnt/IS_FSM_FFd1 30: iobs/TS_FSM_FFd1
5: A_FSB< 18 > 18: cnt/IS_FSM_FFd2 31: iobs/TS_FSM_FFd2
6: A_FSB< 19 > 19: cs/nOverlay 32: nADoutLE1
7: A_FSB< 20 > 20: fsb/ASrf 33: nAS_FSB
8: A_FSB< 21 > 21: iobm/DoutOE 34: nAoutOE
9: A_FSB< 22 > 22: iobm/IORDREQr 35: nBR_IOB
10: A_FSB< 23 > 23: iobm/IOS0 36: nLDS_FSB
11: IOL0 24: iobm/IOWRREQr 37: nRESout
12: IONPReady 25: iobs/IOACTr 38: nUDS_FSB
13: IOU0 26: iobs/IOL1 39: nWE_FSB
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
cs/nOverlay ......XXXX....X...XX............X....... 8
nAoutOE ................XX...............XX..... 4
IOU0 XXXXXXXXXX..X.....XX.......XXXXXX....XX. 21
nDoutOE ....................XXXX.........X...... 5
nDinOE ......XXXX........X.............X.....X. 7
nRES ....................................X... 1
IOL0 XXXXXXXXXXX.......XX.....X..XXXXX..X..X. 21
nVPA_FSB ..XXXXXXXX.X...X...X............X....... 12
IOWRREQ XXXXXXXXXX...X....XX....X.X.XXXXX.....X. 21
iobs/TS_FSM_FFd2 XXXXXXXXXX........XX....X...XXXXX.....X. 19
iobs/IORW1 XXXXXXXXXX.........X......X.XXXXX.....X. 18
0----+----1----+----2----+----3----+----4
0 0 0 0
2022-03-29 08:23:54 +00:00
2023-09-28 06:46:30 +00:00
Number of function block inputs used/remaining: 39/15
Number of signals used by logic mapping into function block: 39
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
2023-07-16 06:25:27 +00:00
ram/RS_FSM_FFd8 13 8< - 0 0 FB5_1 ( b ) ( b )
2023-09-28 06:46:30 +00:00
nROMCS 2 2< - / \ 5 0 FB5_2 35 I / O O
(unused) 0 0 /\2 3 FB5_3 (b) (b)
2023-07-16 06:25:27 +00:00
(unused) 0 0 \/5 0 FB5_4 (b) (b)
nCAS 15 10< - 0 0 FB5_5 36 I / O O
nOE 3 3< - / \ 5 0 FB5_6 37 I / O O
2023-09-28 06:46:30 +00:00
(unused) 0 0 /\3 2 FB5_7 (b) (b)
cnt/Wait< 0 > 1 0 \/2 2 FB5_8 39 I/O (b)
RA< 4 > 2 2< - \ / 5 0 FB5_9 40 I / O O
ram/RASEN 10 5< - 0 0 FB5_10 ( b ) ( b )
RA< 3 > 2 0 \/2 1 FB5_11 41 I/O O
RA< 5 > 2 2< - \ / 5 0 FB5_12 42 I / O O
RAMReady 10 5< - 0 0 FB5_13 ( b ) ( b )
RA< 2 > 2 0 \/2 1 FB5_14 43 I/O O
RA< 6 > 2 2< - \ / 5 0 FB5_15 46 I / O O
IONPReady 5 5< - \ / 5 0 FB5_16 ( b ) ( b )
(unused) 0 0 \/5 0 FB5_17 49 I/O (b)
ram/RASrr 12 10< - \ / 3 0 FB5_18 ( b ) ( b )
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
2023-09-28 06:46:30 +00:00
1: A_FSB< 11 > 14: A_FSB< 4 > 27: nWE_FSB
2: A_FSB< 12 > 15: A_FSB< 5 > 28: ram/DTACKr
3: A_FSB< 13 > 16: A_FSB< 7 > 29: ram/RASEL
4: A_FSB< 14 > 17: BACTr 30: ram/RASEN
5: A_FSB< 16 > 18: IONPReady 31: ram/RS_FSM_FFd1
6: A_FSB< 17 > 19: RefReq 32: ram/RS_FSM_FFd2
7: A_FSB< 18 > 20: RefUrg 33: ram/RS_FSM_FFd3
8: A_FSB< 19 > 21: cnt/Wait< 0 > 34: ram/RS_FSM_FFd4
9: A_FSB< 20 > 22: cs/nOverlay 35: ram/RS_FSM_FFd5
10: A_FSB< 21 > 23: fsb/ASrf 36: ram/RS_FSM_FFd6
11: A_FSB< 22 > 24: iobs/IODONEr 37: ram/RS_FSM_FFd7
12: A_FSB< 23 > 25: iobs/Sent 38: ram/RS_FSM_FFd8
13: A_FSB< 3 > 26: nAS_FSB 39: ram/RefDone
2023-04-09 08:19:06 +00:00
2023-09-28 06:46:30 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ram/RS_FSM_FFd8 ..........XX....X.XX.XX..X...XX..X...XX. 13
nROMCS ........XXXX.........X.................. 5
nCAS ..........XX....X.XX..X..X.X.XXXXXX.XXX. 17
nOE ................X.....X..XXX............ 5
cnt/Wait< 0 > ....................X.X..X.............. 3
RA< 4 > X...........X...............X........... 3
ram/RASEN ..........XX....X.XX..X..X...XX..X...XX. 12
RA< 3 > .......XX...................X........... 3
RA< 5 > .X...........X..............X........... 3
RAMReady ..........XX....X.XX..X..X...XX..XXX.XX. 14
RA< 2 > ....X..........X............X........... 3
RA< 6 > ..X...........X.............X........... 3
IONPReady ..XXXXXXXXXX.....X....XXXXX............. 16
ram/RASrr ..........XX....X.XX.XX..X...X...X..XXX. 13
0----+----1----+----2----+----3----+----4
0 0 0 0
2022-03-29 08:23:54 +00:00
2023-07-16 03:21:41 +00:00
Number of function block inputs used/remaining: 36/18
Number of signals used by logic mapping into function block: 36
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
2023-07-16 03:21:41 +00:00
iobm/IOS_FSM_FFd6 2 0 0 3 FB6_1 (b) (b)
2022-03-29 08:23:54 +00:00
nVMA_IOB 3 0 0 2 FB6_2 74 I/O O
2023-07-16 03:21:41 +00:00
iobm/IOS_FSM_FFd7 3 0 0 2 FB6_3 (b) (b)
iobm/IOS_FSM_FFd3 3 0 0 2 FB6_4 (b) (b)
iobm/ES< 0 > 3 0 0 2 FB6_5 76 I/O I
iobm/ES< 3 > 4 0 0 1 FB6_6 77 I/O I
iobm/ES< 1 > 4 0 0 1 FB6_7 (b) (b)
2023-04-07 06:33:04 +00:00
iobm/DoutOE 4 0 \/1 0 FB6_8 78 I/O I
nLDS_IOB 6 1< - 0 0 FB6_9 79 I / O O
IODONE 4 0 \/1 0 FB6_10 (b) (b)
nUDS_IOB 6 1< - 0 0 FB6_11 80 I / O O
nAS_IOB 4 0 0 1 FB6_12 81 I/O O
iobm/IOS0 5 0 0 0 FB6_13 (b) (b)
2022-03-29 08:23:54 +00:00
nADoutLE1 2 0 0 3 FB6_14 82 I/O O
2023-04-01 08:46:47 +00:00
nADoutLE0 1 0 0 4 FB6_15 85 I/O O
2023-04-07 06:33:04 +00:00
ALE0M 5 0 0 0 FB6_16 (b) (b)
nDinLE 1 0 \/3 1 FB6_17 86 I/O O
IOACT 8 3< - 0 0 FB6_18 ( b ) ( b )
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
2023-07-16 03:21:41 +00:00
1: ALE0M 13: iobm/ES< 1 > 25: iobm/IOS_FSM_FFd7
2: ALE0S 14: iobm/ES< 2 > 26: iobm/IOWRREQr
3: E 15: iobm/ES< 3 > 27: iobm/VPAr
4: IOACT 16: iobm/Er 28: iobs/Clear1
5: IOBERR 17: iobm/IORDREQr 29: iobs/Load1
6: IODONE 18: iobm/IOS0 30: nADoutLE1
7: IOL0 19: iobm/IOS_FSM_FFd1 31: nAS_IOB
8: IOU0 20: iobm/IOS_FSM_FFd2 32: nAoutOE
9: nRES.PIN 21: iobm/IOS_FSM_FFd3 33: nDTACK_IOB
10: iobm/C8Mr 22: iobm/IOS_FSM_FFd4 34: nLDS_IOB
11: iobm/DoutOE 23: iobm/IOS_FSM_FFd5 35: nUDS_IOB
12: iobm/ES< 0 > 24: iobm/IOS_FSM_FFd6 36: nVMA_IOB
2022-03-29 08:23:54 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
2023-07-16 03:21:41 +00:00
iobm/IOS_FSM_FFd6 .........X......X.......XX.....X........ 5
nVMA_IOB ...X.......XXXX...........X....X...X.... 8
iobm/IOS_FSM_FFd7 .........X......X.X.....XX.....X........ 6
iobm/IOS_FSM_FFd3 ....XX...X..........XX.................. 5
iobm/ES< 0 > ..X........XXXXX........................ 6
iobm/ES< 3 > ..X........XXXXX........................ 6
iobm/ES< 1 > ..X........XXXXX........................ 6
iobm/DoutOE .........XX.........XXXXXX.............. 8
nLDS_IOB ......X..X......X...XXXXX......X.X...... 10
IODONE ........X..XXXX...............X.X..X.... 8
nUDS_IOB .......X.X......X...XXXXX......X..X..... 10
nAS_IOB .........X......X...XXXXXX.....X........ 9
iobm/IOS0 .........X......XXXXXXXXXX.....X........ 12
nADoutLE1 ...........................XXX.......... 3
2023-03-26 08:33:59 +00:00
nADoutLE0 XX...................................... 2
2023-07-16 03:21:41 +00:00
ALE0M X...............X.XXXXXXXX.....X........ 11
nDinLE ....................XX.................. 2
IOACT ...XXX...X......X.XXXXXXXX.....X........ 14
2022-03-29 08:23:54 +00:00
0----+----1----+----2----+----3----+----4
0 0 0 0
2023-09-28 06:46:30 +00:00
Number of function block inputs used/remaining: 32/22
Number of signals used by logic mapping into function block: 32
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
2023-07-16 06:25:27 +00:00
cnt/TimerTC 2 0 0 3 FB7_1 (b) (b)
RA< 1 > 2 0 0 3 FB7_2 50 I/O O
2023-09-28 06:46:30 +00:00
cnt/LTimerTC 2 0 0 3 FB7_3 (b) (b)
cnt/LTimer< 9 > 2 0 0 3 FB7_4 (b) (b)
2023-03-22 01:11:58 +00:00
RA< 7 > 2 0 0 3 FB7_5 52 I/O O
2022-03-29 08:23:54 +00:00
RA< 0 > 2 0 0 3 FB7_6 53 I/O O
2023-09-28 06:46:30 +00:00
cnt/LTimer< 8 > 2 0 0 3 FB7_7 (b) (b)
2023-04-07 06:33:04 +00:00
RA< 8 > 2 0 0 3 FB7_8 54 I/O O
RA< 10 > 2 0 0 3 FB7_9 55 I/O O
2023-09-28 06:46:30 +00:00
cnt/LTimer< 7 > 2 0 0 3 FB7_10 (b) (b)
2023-03-22 01:11:58 +00:00
RA< 9 > 2 0 0 3 FB7_11 56 I/O O
C25MEN 0 0 0 5 FB7_12 58 I/O O
2023-09-28 06:46:30 +00:00
cnt/LTimer< 11 > 2 0 0 3 FB7_13 (b) (b)
cnt/LTimer< 10 > 2 0 0 3 FB7_14 59 I/O (b)
RefReq 2 0 0 3 FB7_15 60 I/O (b)
cnt/Timer< 1 > 4 0 0 1 FB7_16 (b) (b)
2023-07-16 06:25:27 +00:00
cnt/Timer< 3 > 5 0 0 0 FB7_17 61 I/O (b)
cnt/Timer< 2 > 5 0 0 0 FB7_18 (b) (b)
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
2023-09-28 06:46:30 +00:00
1: A_FSB< 10 > 12: A_FSB< 9 > 23: cnt/LTimer< 6 >
2: A_FSB< 14 > 13: cnt/Er< 0 > 24: cnt/LTimer< 7 >
3: A_FSB< 15 > 14: cnt/Er< 1 > 25: cnt/LTimer< 8 >
4: A_FSB< 17 > 15: cnt/LTimer< 0 > 26: cnt/LTimer< 9 >
5: A_FSB< 18 > 16: cnt/LTimer< 10 > 27: cnt/Timer< 0 >
6: A_FSB< 1 > 17: cnt/LTimer< 11 > 28: cnt/Timer< 1 >
7: A_FSB< 21 > 18: cnt/LTimer< 1 > 29: cnt/Timer< 2 >
8: A_FSB< 2 > 19: cnt/LTimer< 2 > 30: cnt/Timer< 3 >
9: A_FSB< 6 > 20: cnt/LTimer< 3 > 31: cnt/TimerTC
10: A_FSB< 7 > 21: cnt/LTimer< 4 > 32: ram/RASEL
11: A_FSB< 8 > 22: cnt/LTimer< 5 >
2023-07-16 03:21:41 +00:00
2023-07-16 06:25:27 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
2023-09-28 06:46:30 +00:00
cnt/TimerTC ............XX............XXXX.......... 6
RA< 1 > X......X.......................X........ 3
cnt/LTimerTC ............XXXXXXXXXXXXXX....X......... 15
cnt/LTimer< 9 > ............XXX..XXXXXXXX.....X......... 12
RA< 7 > .X......X......................X........ 3
RA< 0 > .....X.....X...................X........ 3
cnt/LTimer< 8 > ............XXX..XXXXXXX......X......... 11
RA< 8 > ....X.X........................X........ 3
RA< 10 > ...X.....X.....................X........ 3
cnt/LTimer< 7 > ............XXX..XXXXXX.......X......... 10
RA< 9 > ..X.......X....................X........ 3
2023-07-16 06:25:27 +00:00
C25MEN ........................................ 0
2023-09-28 06:46:30 +00:00
cnt/LTimer< 11 > ............XXXX.XXXXXXXXX....X......... 14
cnt/LTimer< 10 > ............XXX..XXXXXXXXX....X......... 13
RefReq ............XX............XXXX.......... 6
cnt/Timer< 1 > ............XX............XX..X......... 5
cnt/Timer< 3 > ............XX............XXXXX......... 7
cnt/Timer< 2 > ............XX............XXX.X......... 6
2023-07-16 06:25:27 +00:00
0----+----1----+----2----+----3----+----4
0 0 0 0
2022-03-29 08:23:54 +00:00
2023-09-28 06:46:30 +00:00
Number of function block inputs used/remaining: 40/14
Number of signals used by logic mapping into function block: 40
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
2023-09-28 06:46:30 +00:00
(unused) 0 0 /\5 0 FB8_1 (b) (b)
RA< 11 > 2 0 \/3 0 FB8_2 63 I/O O
IORDREQ 9 4< - 0 0 FB8_3 ( b ) ( b )
ram/RS_FSM_FFd7 9 5< - / \ 1 0 FB8_4 ( b ) ( b )
nRAS 3 3< - / \ 5 0 FB8_5 64 I / O O
nRAMLWE 1 0 /\3 1 FB8_6 65 I/O O
iobs/Load1 8 3< - 0 0 FB8_7 ( b ) ( b )
nRAMUWE 1 0 /\3 1 FB8_8 66 I/O O
ram/RASEL 3 0 0 2 FB8_9 67 I/O (b)
iobs/TS_FSM_FFd1 2 0 0 3 FB8_10 (b) (b)
ram/RS_FSM_FFd6 2 0 0 3 FB8_11 68 I/O (b)
nBERR_FSB 3 0 0 2 FB8_12 70 I/O O
ALE0S 1 0 0 4 FB8_13 (b) (b)
BACTr 1 0 0 4 FB8_14 71 I/O (b)
nBR_IOB 2 0 0 3 FB8_15 72 I/O O
iobs/Clear1 1 0 0 4 FB8_16 (b) (b)
nRESout 1 0 \/3 1 FB8_17 73 I/O (b)
iobs/Sent 13 8< - 0 0 FB8_18 ( b ) ( b )
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
2023-09-28 06:46:30 +00:00
1: A_FSB< 13 > 15: RefUrg 28: nBERR_FSB
2: A_FSB< 14 > 16: cnt/IS_FSM_FFd1 29: nBR_IOB
3: A_FSB< 16 > 17: cnt/IS_FSM_FFd2 30: nLDS_FSB
4: A_FSB< 17 > 18: cnt/nIPL2r 31: nUDS_FSB
5: A_FSB< 18 > 19: cs/nOverlay 32: nWE_FSB
6: A_FSB< 19 > 20: fsb/ASrf 33: ram/RASEL
7: A_FSB< 20 > 21: iobs/IOACTr 34: ram/RASEN
8: A_FSB< 21 > 22: iobs/IORW1 35: ram/RASrf
9: A_FSB< 22 > 23: iobs/Sent 36: ram/RASrr
10: A_FSB< 23 > 24: iobs/TS_FSM_FFd1 37: ram/RS_FSM_FFd4
11: BACTr 25: iobs/TS_FSM_FFd2 38: ram/RS_FSM_FFd6
12: IOBERR 26: nADoutLE1 39: ram/RS_FSM_FFd8
13: IORDREQ 27: nAS_FSB 40: ram/RefDone
14: RefReq
2023-07-16 03:21:41 +00:00
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
2023-09-28 06:46:30 +00:00
RA< 11 > .....XX.........................X................. 3
IORDREQ ......XXXX..X.....XXXXXXXXX....X.................. 15
ram/RS_FSM_FFd7 ........XXX..XX....X......X......X..X.XX.......... 11
nRAS ........XX........X.......X......XXX.............. 7
nRAMLWE .............................X.XX................. 3
iobs/Load1 XXXXXXXXXX.........X..XXXXX....X.................. 17
nRAMUWE ..............................XXX................. 3
ram/RASEL ........XX........XX......X......X...XX........... 8
iobs/TS_FSM_FFd1 ....................X..XX......................... 3
ram/RS_FSM_FFd6 ........XX........XX......X......X....X........... 7
nBERR_FSB ...........X.......X..X...XX...................... 5
ALE0S ........................X......................... 1
BACTr ...................X......X....................... 2
nBR_IOB ...............XXX..........X..................... 4
iobs/Clear1 .......................XX......................... 2
nRESout ...............XX................................. 2
iobs/Sent XXXXXXXXXX........XX..XXXXX....X.................. 18
2023-07-16 03:21:41 +00:00
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
2022-03-29 08:23:54 +00:00
********** Mapped Logic **********
2023-03-26 08:33:59 +00:00
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,C16M,'0','0');
2023-04-07 06:33:04 +00:00
ALE0M_D < = ((iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND nAoutOE)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
iobm/IOS_FSM_FFd1)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
iobm/IOS_FSM_FFd2)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT ALE0M)
OR (iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
NOT iobm/IORDREQr AND NOT iobm/IOWRREQr));
2022-03-29 08:23:54 +00:00
2023-04-01 08:46:47 +00:00
FDCPE_ALE0S: FDCPE port map (ALE0S,iobs/TS_FSM_FFd2,FCLK,'0','0');
2022-03-29 08:23:54 +00:00
2023-07-16 06:25:27 +00:00
FDCPE_BACTr: FDCPE port map (BACTr,BACTr_D,FCLK,'0','0');
BACTr_D < = (nAS_FSB AND NOT fsb/ASrf);
2023-07-13 20:03:30 +00:00
2023-07-16 03:20:51 +00:00
C25MEN < = '1';
2023-07-13 20:03:30 +00:00
2023-04-01 12:20:02 +00:00
2023-07-16 03:21:41 +00:00
2023-04-01 12:20:02 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,C16M,'0','0');
2023-04-07 06:33:04 +00:00
IOACT_D < = ((iobm/IOS_FSM_FFd4)
OR (iobm/IOS_FSM_FFd5)
OR (iobm/IOS_FSM_FFd6)
OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3)
OR (iobm/IOS_FSM_FFd7 AND iobm/IOWRREQr AND NOT nAoutOE)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND IOACT AND
NOT iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2)
OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr)
OR (iobm/IOS_FSM_FFd7 AND iobm/IORDREQr AND NOT nAoutOE));
FDCPE_IOBERR: FDCPE port map (IOBERR,NOT nBERR_IOB,NOT C8M,nAS_IOB,'0');
FDCPE_IODONE: FDCPE port map (IODONE,IODONE_D,NOT C8M,nAS_IOB,'0');
IODONE_D < = ((NOT nRES.PIN)
OR (NOT nDTACK_IOB)
OR (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
iobm/ES(3)));
FTCPE_IOL0: FTCPE port map (IOL0,IOL0_T,FCLK,'0','0');
IOL0_T < = ((iobs/TS_FSM_FFd1)
2023-09-28 06:46:30 +00:00
OR (NOT iobs/IOL1 AND NOT IOL0 AND NOT nADoutLE1)
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND
nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(20) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND nWE_FSB AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (nVPA_FSB_OBUF.EXP)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-07-16 03:21:41 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(19) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(18) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-01 12:20:02 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(17) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(16) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (nLDS_FSB AND NOT IOL0 AND nADoutLE1)
OR (NOT nLDS_FSB AND IOL0 AND nADoutLE1)
OR (iobs/IOL1 AND IOL0 AND NOT nADoutLE1));
2023-07-16 03:21:41 +00:00
FDCPE_IONPReady: FDCPE port map (IONPReady,IONPReady_D,FCLK,'0','0');
2023-09-28 06:46:30 +00:00
IONPReady_D < = ((NOT iobs/Sent AND NOT IONPReady)
2023-07-16 03:21:41 +00:00
OR (NOT IONPReady AND NOT iobs/IODONEr)
2023-09-28 06:46:30 +00:00
OR (nAS_FSB AND NOT fsb/ASrf)
2023-07-16 03:21:41 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT nWE_FSB AND NOT IONPReady)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT nWE_FSB AND NOT IONPReady));
2023-04-07 06:33:04 +00:00
FDCPE_IORDREQ: FDCPE port map (IORDREQ,IORDREQ_D,FCLK,'0','0');
2023-07-16 03:21:43 +00:00
IORDREQ_D < = ((NOT iobs/IORW1 AND NOT iobs/TS_FSM_FFd2 AND NOT nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/TS_FSM_FFd2 AND
nADoutLE1)
2023-07-16 03:21:43 +00:00
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND
nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND cs/nOverlay AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
2023-07-16 03:21:43 +00:00
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr)
OR (iobs/TS_FSM_FFd2 AND NOT IORDREQ)
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT nWE_FSB AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1));
2023-04-07 06:33:04 +00:00
FTCPE_IOU0: FTCPE port map (IOU0,IOU0_T,FCLK,'0','0');
IOU0_T < = ((iobs/TS_FSM_FFd1)
2023-09-28 06:46:30 +00:00
OR (nAoutOE_OBUF.EXP)
2023-04-07 06:33:04 +00:00
OR (NOT iobs/IOU1 AND NOT IOU0 AND NOT nADoutLE1)
2023-04-01 08:46:47 +00:00
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND
2023-03-26 08:33:59 +00:00
nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(20) AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-07-16 03:20:51 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND nWE_FSB AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-09-28 06:46:30 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(19) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-07-16 03:21:41 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(18) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(17) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(16) AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-09-28 06:46:30 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND cs/nOverlay AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (nUDS_FSB AND NOT IOU0 AND nADoutLE1)
OR (NOT nUDS_FSB AND IOU0 AND nADoutLE1)
OR (iobs/IOU1 AND IOU0 AND NOT nADoutLE1));
FDCPE_IOWRREQ: FDCPE port map (IOWRREQ,IOWRREQ_D,FCLK,'0','0');
IOWRREQ_D < = ((A_FSB(22) AND A_FSB(21) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (A_FSB(22) AND NOT iobs/Sent AND NOT cs/nOverlay AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (A_FSB(22) AND NOT iobs/Sent AND NOT cs/nOverlay AND NOT nWE_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
2023-07-16 03:21:41 +00:00
A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
2023-07-16 03:21:41 +00:00
A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND NOT iobs/Sent AND NOT nWE_FSB AND
2023-04-09 08:19:06 +00:00
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2 AND IOWRREQ)
OR (iobs/TS_FSM_FFd2 AND NOT iobs/IOACTr AND IOWRREQ)
OR (NOT iobs/IORW1 AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND
NOT nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1));
2023-03-25 07:49:44 +00:00
2023-07-16 03:21:41 +00:00
FDCPE_QoSReady: FDCPE port map (QoSReady,QoSReady_D,FCLK,'0','0');
2023-09-28 06:46:30 +00:00
QoSReady_D < = ((QoSReady AND fsb/ASrf)
OR (NOT cnt/Wait(0) AND NOT cnt/Wait(1) AND NOT cnt/Wait(2) AND
NOT cnt/Wait(3) AND cnt/Wait(4))
OR (NOT cnt/QS(0) AND NOT cnt/QS(1))
OR (QoSReady AND NOT nAS_FSB));
2023-07-16 03:21:41 +00:00
2022-03-29 08:23:54 +00:00
2023-04-07 06:33:04 +00:00
RA(0) < = ((ram/RASEL AND A_FSB(1))
OR (NOT ram/RASEL AND A_FSB(9)));
2022-03-29 08:23:54 +00:00
2023-07-16 03:21:41 +00:00
RA(1) < = ((A_FSB(10) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(2)));
2022-03-29 08:23:54 +00:00
2023-07-16 03:21:43 +00:00
RA(2) < = ((A_FSB(16) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(7)));
2022-03-29 08:23:54 +00:00
2023-04-07 06:33:04 +00:00
RA(3) < = ((A_FSB(20) AND ram/RASEL)
OR (A_FSB(19) AND NOT ram/RASEL));
2022-03-29 08:23:54 +00:00
2023-07-16 03:21:41 +00:00
RA(4) < = ((A_FSB(11) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(3)));
2022-03-29 08:23:54 +00:00
2023-07-16 03:21:41 +00:00
RA(5) < = ((A_FSB(12) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(4)));
2022-03-29 08:23:54 +00:00
2023-07-16 03:21:41 +00:00
RA(6) < = ((A_FSB(13) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(5)));
2022-03-29 08:23:54 +00:00
2023-07-16 03:21:41 +00:00
RA(7) < = ((A_FSB(14) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(6)));
2022-03-29 08:23:54 +00:00
2023-03-22 01:11:58 +00:00
2023-04-07 06:33:04 +00:00
RA(8) < = ((A_FSB(21) AND ram/RASEL)
OR (A_FSB(18) AND NOT ram/RASEL));
2023-03-22 01:11:58 +00:00
2023-07-16 03:21:41 +00:00
RA(9) < = ((A_FSB(15) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(8)));
2023-03-22 01:11:58 +00:00
2023-04-07 06:33:04 +00:00
RA(10) < = ((A_FSB(17) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(7)));
2023-03-22 01:11:58 +00:00
2023-04-07 06:33:04 +00:00
RA(11) < = ((A_FSB(20) AND ram/RASEL)
OR (A_FSB(19) AND NOT ram/RASEL));
2023-03-22 01:11:58 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_RAMReady: FDCPE port map (RAMReady,RAMReady_D,FCLK,'0','0');
2023-07-16 06:25:27 +00:00
RAMReady_D < = ((RefUrg AND NOT ram/RefDone AND nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6 AND NOT fsb/ASrf)
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
2023-09-28 06:46:30 +00:00
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND
NOT ram/RS_FSM_FFd6 AND NOT BACTr)
2023-07-16 06:25:27 +00:00
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND
2023-09-28 06:46:30 +00:00
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND
NOT ram/RS_FSM_FFd6 AND NOT BACTr AND fsb/ASrf)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND
NOT ram/RS_FSM_FFd6 AND NOT BACTr)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND
NOT ram/RS_FSM_FFd6 AND NOT BACTr AND fsb/ASrf)
2023-07-16 06:25:27 +00:00
OR (NOT ram/RS_FSM_FFd8 AND NOT ram/RS_FSM_FFd4 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd8 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RASEN AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6));
2023-07-16 03:21:41 +00:00
FDCPE_RefReq: FDCPE port map (RefReq,RefReq_D,FCLK,'0','0',RefReq_CE);
RefReq_D < = (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
cnt/Timer(3));
RefReq_CE < = (NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_RefUrg: FDCPE port map (RefUrg,RefUrg_D,FCLK,'0','0',RefUrg_CE);
2023-07-16 06:25:27 +00:00
RefUrg_D < = (NOT cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3));
2023-07-16 03:21:41 +00:00
RefUrg_CE < = (NOT cnt/Er(0) AND cnt/Er(1));
2022-03-29 08:23:54 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_cnt/Er0: FDCPE port map (cnt/Er(0),E,FCLK,'0','0');
2022-03-29 08:23:54 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_cnt/Er1: FDCPE port map (cnt/Er(1),cnt/Er(0),FCLK,'0','0');
2022-03-29 08:23:54 +00:00
2023-04-09 08:19:06 +00:00
FTCPE_cnt/IS_FSM_FFd1: FTCPE port map (cnt/IS_FSM_FFd1,cnt/IS_FSM_FFd1_T,FCLK,'0','0');
2023-09-28 06:46:30 +00:00
cnt/IS_FSM_FFd1_T < = (cnt/TimerTC AND cnt/LTimerTC AND NOT cnt/IS_FSM_FFd1 AND
cnt/IS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/nIPL2r AND cnt/Er(1));
2023-04-09 08:19:06 +00:00
FTCPE_cnt/IS_FSM_FFd2: FTCPE port map (cnt/IS_FSM_FFd2,cnt/IS_FSM_FFd2_T,FCLK,'0','0');
2023-09-28 06:46:30 +00:00
cnt/IS_FSM_FFd2_T < = ((cnt/TimerTC AND cnt/LTimerTC AND cnt/IS_FSM_FFd1 AND
cnt/IS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1))
OR (cnt/TimerTC AND cnt/LTimerTC AND NOT cnt/IS_FSM_FFd1 AND
NOT cnt/IS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1)));
FTCPE_cnt/LTimer0: FTCPE port map (cnt/LTimer(0),'1',FCLK,'0','0',cnt/LTimer_CE(0));
cnt/LTimer_CE(0) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer1: FTCPE port map (cnt/LTimer(1),cnt/LTimer(0),FCLK,'0','0',cnt/LTimer_CE(1));
cnt/LTimer_CE(1) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer2: FTCPE port map (cnt/LTimer(2),cnt/LTimer_T(2),FCLK,'0','0',cnt/LTimer_CE(2));
cnt/LTimer_T(2) < = (cnt/LTimer(0) AND cnt/LTimer(1));
cnt/LTimer_CE(2) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer3: FTCPE port map (cnt/LTimer(3),cnt/LTimer_T(3),FCLK,'0','0',cnt/LTimer_CE(3));
cnt/LTimer_T(3) < = (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2));
cnt/LTimer_CE(3) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer4: FTCPE port map (cnt/LTimer(4),cnt/LTimer_T(4),FCLK,'0','0',cnt/LTimer_CE(4));
cnt/LTimer_T(4) < = (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3));
cnt/LTimer_CE(4) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer5: FTCPE port map (cnt/LTimer(5),cnt/LTimer_T(5),FCLK,'0','0',cnt/LTimer_CE(5));
cnt/LTimer_T(5) < = (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4));
cnt/LTimer_CE(5) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer6: FTCPE port map (cnt/LTimer(6),cnt/LTimer_T(6),FCLK,'0','0',cnt/LTimer_CE(6));
cnt/LTimer_T(6) < = (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5));
cnt/LTimer_CE(6) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer7: FTCPE port map (cnt/LTimer(7),cnt/LTimer_T(7),FCLK,'0','0',cnt/LTimer_CE(7));
cnt/LTimer_T(7) < = (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6));
cnt/LTimer_CE(7) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer8: FTCPE port map (cnt/LTimer(8),cnt/LTimer_T(8),FCLK,'0','0',cnt/LTimer_CE(8));
cnt/LTimer_T(8) < = (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7));
cnt/LTimer_CE(8) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer9: FTCPE port map (cnt/LTimer(9),cnt/LTimer_T(9),FCLK,'0','0',cnt/LTimer_CE(9));
cnt/LTimer_T(9) < = (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7) AND cnt/LTimer(8));
cnt/LTimer_CE(9) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer10: FTCPE port map (cnt/LTimer(10),cnt/LTimer_T(10),FCLK,'0','0',cnt/LTimer_CE(10));
cnt/LTimer_T(10) < = (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
cnt/LTimer_CE(10) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer11: FTCPE port map (cnt/LTimer(11),cnt/LTimer_T(11),FCLK,'0','0',cnt/LTimer_CE(11));
cnt/LTimer_T(11) < = (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND
cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
cnt/LTimer_CE(11) < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_cnt/LTimerTC: FDCPE port map (cnt/LTimerTC,cnt/LTimerTC_D,FCLK,'0','0',cnt/LTimerTC_CE);
cnt/LTimerTC_D < = (NOT cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND
cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND
cnt/LTimer(11));
cnt/LTimerTC_CE < = (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_cnt/QS0: FDCPE port map (cnt/QS(0),cnt/QS_D(0),FCLK,'0','0');
cnt/QS_D(0) < = ((NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
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A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
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NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(8))
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
2023-09-28 06:46:30 +00:00
A_FSB(13) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(9))
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
2023-07-16 06:25:27 +00:00
A_FSB(13) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
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NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(8))
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
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NOT nWE_FSB AND A_FSB(9) AND fsb/ASrf)
2023-07-16 03:21:43 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
NOT nWE_FSB AND A_FSB(8) AND fsb/ASrf)
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
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NOT nWE_FSB AND A_FSB(9) AND fsb/ASrf)
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
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NOT nWE_FSB AND A_FSB(8) AND fsb/ASrf)
OR (cnt/QS(0) AND NOT cnt/TimerTC)
OR (cnt/QS(0) AND cnt/Er(0))
OR (cnt/QS(0) AND NOT cnt/Er(1))
OR (NOT cnt/QS(0) AND cnt/QS(1) AND cnt/TimerTC AND NOT cnt/Er(0) AND
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cnt/Er(1))
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(9)));
2023-07-16 03:21:41 +00:00
2023-09-28 06:46:30 +00:00
FDCPE_cnt/QS1: FDCPE port map (cnt/QS(1),cnt/QS_D(1),FCLK,'0','0');
cnt/QS_D(1) < = ((NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
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A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
2023-07-16 06:25:27 +00:00
A_FSB(13) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
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NOT nWE_FSB AND A_FSB(9) AND fsb/ASrf)
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
2023-07-16 06:25:27 +00:00
A_FSB(13) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
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NOT nWE_FSB AND A_FSB(8) AND fsb/ASrf)
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
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NOT nWE_FSB AND A_FSB(9) AND fsb/ASrf)
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
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NOT nWE_FSB AND A_FSB(8) AND fsb/ASrf)
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(9))
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
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NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(8))
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(9))
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
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NOT nWE_FSB AND NOT nAS_FSB AND A_FSB(8))
OR (NOT cnt/QS(0) AND NOT cnt/QS(1))
OR (NOT cnt/QS(1) AND NOT cnt/TimerTC)
OR (NOT cnt/QS(1) AND cnt/Er(0))
OR (NOT cnt/QS(1) AND NOT cnt/Er(1))
OR (cnt/QS(0) AND cnt/QS(1) AND cnt/TimerTC AND NOT cnt/Er(0) AND
cnt/Er(1)));
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FTCPE_cnt/Timer0: FTCPE port map (cnt/Timer(0),cnt/Timer_T(0),FCLK,'0','0',cnt/Timer_CE(0));
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cnt/Timer_T(0) < = (NOT cnt/Timer(0) AND cnt/TimerTC AND NOT cnt/Er(0) AND
cnt/Er(1));
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cnt/Timer_CE(0) < = (NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_cnt/Timer1: FDCPE port map (cnt/Timer(1),cnt/Timer_D(1),FCLK,'0','0',cnt/Timer_CE(1));
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cnt/Timer_D(1) < = ((cnt/Timer(0) AND cnt/Timer(1))
OR (NOT cnt/Timer(0) AND NOT cnt/Timer(1))
OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
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cnt/Timer_CE(1) < = (NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_cnt/Timer2: FDCPE port map (cnt/Timer(2),cnt/Timer_D(2),FCLK,'0','0',cnt/Timer_CE(2));
2023-03-27 14:17:22 +00:00
cnt/Timer_D(2) < = ((NOT cnt/Timer(0) AND NOT cnt/Timer(2))
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OR (NOT cnt/Timer(1) AND NOT cnt/Timer(2))
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OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2))
OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
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cnt/Timer_CE(2) < = (NOT cnt/Er(0) AND cnt/Er(1));
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FTCPE_cnt/Timer3: FTCPE port map (cnt/Timer(3),cnt/Timer_T(3),FCLK,'0','0',cnt/Timer_CE(3));
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cnt/Timer_T(3) < = ((cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
NOT cnt/TimerTC)
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OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
cnt/Er(0))
OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
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NOT cnt/Er(1))
OR (cnt/Timer(3) AND cnt/TimerTC AND NOT cnt/Er(0) AND
cnt/Er(1)));
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cnt/Timer_CE(3) < = (NOT cnt/Er(0) AND cnt/Er(1));
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FDCPE_cnt/TimerTC: FDCPE port map (cnt/TimerTC,cnt/TimerTC_D,FCLK,'0','0',cnt/TimerTC_CE);
cnt/TimerTC_D < = (cnt/Timer(0) AND NOT cnt/Timer(1) AND NOT cnt/Timer(2) AND
cnt/Timer(3));
cnt/TimerTC_CE < = (NOT cnt/Er(0) AND cnt/Er(1));
2023-07-16 03:21:41 +00:00
2023-09-28 06:46:30 +00:00
FTCPE_cnt/Wait0: FTCPE port map (cnt/Wait(0),cnt/Wait_T(0),FCLK,'0','0');
cnt/Wait_T(0) < = (nAS_FSB AND NOT cnt/Wait(0) AND NOT fsb/ASrf);
FDCPE_cnt/Wait1: FDCPE port map (cnt/Wait(1),cnt/Wait_D(1),FCLK,'0','0');
cnt/Wait_D(1) < = ((nAS_FSB AND NOT fsb/ASrf)
OR (cnt/Wait(0) AND cnt/Wait(1))
OR (NOT cnt/Wait(0) AND NOT cnt/Wait(1)));
FTCPE_cnt/Wait2: FTCPE port map (cnt/Wait(2),cnt/Wait_T(2),FCLK,'0','0');
cnt/Wait_T(2) < = ((nAS_FSB AND cnt/Wait(2) AND NOT fsb/ASrf)
OR (NOT nAS_FSB AND cnt/Wait(0) AND cnt/Wait(1))
OR (cnt/Wait(0) AND cnt/Wait(1) AND fsb/ASrf));
FTCPE_cnt/Wait3: FTCPE port map (cnt/Wait(3),cnt/Wait_T(3),FCLK,'0','0');
cnt/Wait_T(3) < = ((nAS_FSB AND cnt/Wait(3) AND NOT fsb/ASrf)
OR (NOT nAS_FSB AND cnt/Wait(0) AND cnt/Wait(1) AND
cnt/Wait(2))
OR (cnt/Wait(0) AND cnt/Wait(1) AND cnt/Wait(2) AND
fsb/ASrf));
FTCPE_cnt/Wait4: FTCPE port map (cnt/Wait(4),cnt/Wait_T(4),FCLK,'0','0');
cnt/Wait_T(4) < = ((nAS_FSB AND cnt/Wait(4) AND NOT fsb/ASrf)
OR (NOT nAS_FSB AND cnt/Wait(0) AND cnt/Wait(1) AND
cnt/Wait(2) AND cnt/Wait(3))
OR (cnt/Wait(0) AND cnt/Wait(1) AND cnt/Wait(2) AND
cnt/Wait(3) AND fsb/ASrf));
2023-03-26 08:33:59 +00:00
FDCPE_cnt/nIPL2r: FDCPE port map (cnt/nIPL2r,nIPL2,FCLK,'0','0');
2023-04-01 08:46:47 +00:00
FTCPE_cs/nOverlay: FTCPE port map (cs/nOverlay,cs/nOverlay_T,FCLK,'0','0');
cs/nOverlay_T < = ((NOT nRES.PIN AND cs/nOverlay AND nAS_FSB AND NOT fsb/ASrf)
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OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT cs/nOverlay AND NOT nAS_FSB)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT cs/nOverlay AND fsb/ASrf));
2023-03-26 08:33:59 +00:00
2023-04-01 08:46:47 +00:00
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT FCLK,'0','0');
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_iobm/C8Mr: FDCPE port map (iobm/C8Mr,C8M,C16M,'0','0');
FTCPE_iobm/DoutOE: FTCPE port map (iobm/DoutOE,iobm/DoutOE_T,C16M,'0','0');
iobm/DoutOE_T < = ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND NOT iobm/DoutOE AND
iobm/IOWRREQr)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
iobm/DoutOE)
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
iobm/DoutOE)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND iobm/DoutOE AND NOT iobm/IOWRREQr));
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),NOT C8M,'0','0');
iobm/ES_T(0) < = ((iobm/ES(0) AND NOT E AND iobm/Er)
OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
NOT iobm/ES(3) AND E)
OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
NOT iobm/ES(3) AND NOT iobm/Er));
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),NOT C8M,'0','0');
2023-03-26 08:33:59 +00:00
iobm/ES_D(1) < = ((iobm/ES(0) AND iobm/ES(1))
OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
2023-04-07 06:33:04 +00:00
OR (NOT E AND iobm/Er)
OR (iobm/ES(0) AND NOT iobm/ES(2) AND iobm/ES(3)));
FTCPE_iobm/ES2: FTCPE port map (iobm/ES(2),iobm/ES_T(2),NOT C8M,'0','0');
iobm/ES_T(2) < = ((iobm/ES(0) AND iobm/ES(1) AND E)
OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/Er)
OR (iobm/ES(2) AND NOT E AND iobm/Er));
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),NOT C8M,'0','0');
iobm/ES_T(3) < = ((iobm/ES(3) AND NOT E AND iobm/Er)
OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND E)
OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND NOT iobm/Er)
OR (iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
iobm/ES(3)));
2023-03-26 08:33:59 +00:00
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E,NOT C8M,'0','0');
2023-04-07 06:33:04 +00:00
FDCPE_iobm/IORDREQr: FDCPE port map (iobm/IORDREQr,IORDREQ,C16M,'0','0');
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_iobm/IOS0: FDCPE port map (iobm/IOS0,iobm/IOS0_D,C16M,'0','0');
iobm/IOS0_D < = ((iobm/IOS_FSM_FFd1)
OR (iobm/IOS_FSM_FFd7 AND iobm/C8Mr)
OR (iobm/IOS_FSM_FFd7 AND nAoutOE)
OR (iobm/IOS_FSM_FFd7 AND NOT iobm/IORDREQr AND
NOT iobm/IOWRREQr)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
NOT iobm/IOS_FSM_FFd2 AND iobm/IOS0));
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,C16M,'0','0');
2023-03-26 08:33:59 +00:00
2023-04-01 08:46:47 +00:00
FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,C16M,'0','0');
2023-04-07 06:33:04 +00:00
iobm/IOS_FSM_FFd2_D < = ((IOBERR AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr)
OR (IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr));
2023-03-26 08:33:59 +00:00
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,'0','0');
2023-04-07 06:33:04 +00:00
iobm/IOS_FSM_FFd3_D < = ((iobm/IOS_FSM_FFd4)
OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr)
OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3));
FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,C16M,'0','0');
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,C16M,'0','0');
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd6_D,C16M,'0','0');
iobm/IOS_FSM_FFd6_D < = ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IORDREQr AND
NOT nAoutOE)
OR (iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IOWRREQr AND
NOT nAoutOE));
FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,C16M,'0','0');
iobm/IOS_FSM_FFd7_D < = ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd1)
OR (NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd1 AND iobm/IORDREQr AND
NOT nAoutOE)
OR (NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd1 AND iobm/IOWRREQr AND
NOT nAoutOE));
FDCPE_iobm/IOWRREQr: FDCPE port map (iobm/IOWRREQr,IOWRREQ,C16M,'0','0');
FDCPE_iobm/VPAr: FDCPE port map (iobm/VPAr,NOT nVPA_IOB,NOT C8M,'0','0');
2023-03-26 08:33:59 +00:00
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
iobs/Clear1_D < = (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2);
2023-03-26 08:33:59 +00:00
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
FDCPE_iobs/IODONEr: FDCPE port map (iobs/IODONEr,IODONE,FCLK,'0','0');
2023-04-01 08:46:47 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,FCLK,'0','0',iobs/Load1);
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,FCLK,'0','0');
2023-09-28 06:46:30 +00:00
iobs/IORW1_T < = ((cs/nOverlay.EXP)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-16 06:25:27 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND
iobs/TS_FSM_FFd1 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-16 03:21:41 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND
fsb/ASrf AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-16 03:21:41 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
2023-07-16 06:25:27 +00:00
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND
iobs/TS_FSM_FFd1 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-16 03:21:41 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
2023-07-16 06:25:27 +00:00
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd1 AND
2023-07-16 03:21:41 +00:00
fsb/ASrf AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-09-28 06:46:30 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND
fsb/ASrf AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-16 03:21:41 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND
iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND
2023-09-28 06:46:30 +00:00
iobs/TS_FSM_FFd2 AND nADoutLE1));
2023-03-26 08:33:59 +00:00
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,FCLK,'0','0',iobs/Load1);
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
iobs/Load1_D < = ((NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-16 03:21:41 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
2023-07-16 06:25:27 +00:00
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd1 AND
2023-07-16 03:21:41 +00:00
nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
2023-07-16 06:25:27 +00:00
NOT iobs/Sent AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND fsb/ASrf AND
2023-07-16 03:21:41 +00:00
nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
2023-07-16 06:25:27 +00:00
NOT iobs/Sent AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND fsb/ASrf AND
2023-07-16 03:21:41 +00:00
nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-16 03:21:41 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd2 AND
nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-16 06:25:27 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND fsb/ASrf AND
2023-07-16 03:21:41 +00:00
nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-16 03:21:41 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
2023-09-28 06:46:30 +00:00
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd1 AND
nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
2023-07-16 03:21:41 +00:00
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd2 AND
2023-07-16 03:21:43 +00:00
nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND fsb/ASrf AND
2023-07-16 03:21:41 +00:00
nADoutLE1));
2023-04-01 12:20:02 +00:00
FTCPE_iobs/Sent: FTCPE port map (iobs/Sent,iobs/Sent_T,FCLK,'0','0');
2023-09-28 06:46:30 +00:00
iobs/Sent_T < = ((A_FSB(22) AND NOT iobs/Sent AND NOT cs/nOverlay AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1)
2023-07-16 03:21:43 +00:00
OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Sent AND
2023-07-16 03:21:41 +00:00
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Sent AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND NOT iobs/Sent AND NOT cs/nOverlay AND NOT nAS_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-01 12:20:02 +00:00
OR (iobs/Sent AND nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(23) AND NOT iobs/Sent AND NOT nAS_FSB AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Sent AND NOT iobs/TS_FSM_FFd1 AND
2023-09-28 06:46:30 +00:00
NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Sent AND NOT nAS_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Sent AND NOT nAS_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1));
2023-04-01 08:46:47 +00:00
FDCPE_iobs/TS_FSM_FFd1: FDCPE port map (iobs/TS_FSM_FFd1,iobs/TS_FSM_FFd1_D,FCLK,'0','0');
iobs/TS_FSM_FFd1_D < = ((iobs/TS_FSM_FFd2)
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr));
FDCPE_iobs/TS_FSM_FFd2: FDCPE port map (iobs/TS_FSM_FFd2,iobs/TS_FSM_FFd2_D,FCLK,'0','0');
2023-07-16 06:25:27 +00:00
iobs/TS_FSM_FFd2_D < = ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
2023-04-01 12:20:02 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(20) AND
2023-04-01 12:20:02 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-09-28 06:46:30 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(18) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-07-16 06:25:27 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(17) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-07-16 03:21:41 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(16) AND
2023-04-01 12:20:02 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-07-16 06:25:27 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(19) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(13) AND NOT A_FSB(14) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND cs/nOverlay AND
2023-04-01 12:20:02 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
2023-04-01 08:46:47 +00:00
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr)
2023-07-16 06:25:27 +00:00
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND
nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND nWE_FSB AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1));
2023-03-26 08:33:59 +00:00
nADoutLE0 < = (NOT ALE0M AND NOT ALE0S);
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,FCLK,'0','0');
nADoutLE1_D < = ((iobs/Load1)
OR (NOT iobs/Clear1 AND NOT nADoutLE1));
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB_I,nAS_IOB,NOT C16M,'0','0');
2023-04-07 06:33:04 +00:00
nAS_IOB < = ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IORDREQr AND
NOT iobm/IOWRREQr));
2023-03-26 08:33:59 +00:00
nAS_IOB < = nAS_IOB_I when nAS_IOB_OE = '1' else 'Z';
nAS_IOB_OE < = NOT nAoutOE;
FDCPE_nAoutOE: FDCPE port map (nAoutOE,nAoutOE_D,FCLK,'0','0');
2023-04-09 08:19:06 +00:00
nAoutOE_D < = ((NOT nBR_IOB AND cnt/IS_FSM_FFd1 AND cnt/IS_FSM_FFd2)
OR (cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND NOT nAoutOE));
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_nBERR_FSB: FDCPE port map (nBERR_FSB,nBERR_FSB_D,FCLK,'0','0');
2023-09-28 06:46:30 +00:00
nBERR_FSB_D < = ((NOT iobs/Sent AND nBERR_FSB)
OR (NOT IOBERR AND nBERR_FSB)
2023-04-07 06:33:04 +00:00
OR (nAS_FSB AND NOT fsb/ASrf));
2023-03-26 08:33:59 +00:00
FTCPE_nBR_IOB: FTCPE port map (nBR_IOB,nBR_IOB_T,FCLK,'0','0');
2023-04-09 08:19:06 +00:00
nBR_IOB_T < = ((nBR_IOB AND NOT cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2)
OR (NOT nBR_IOB AND NOT cnt/IS_FSM_FFd1 AND cnt/IS_FSM_FFd2 AND
NOT cnt/nIPL2r));
2023-03-26 08:33:59 +00:00
2023-07-16 06:25:27 +00:00
FDCPE_nCAS: FDCPE port map (nCAS,nCAS_D,NOT FCLK,'0','0');
nCAS_D < = ((ram/RS_FSM_FFd1)
OR (ram/RS_FSM_FFd2)
OR (ram/RS_FSM_FFd3)
OR (NOT RefUrg AND ram/RS_FSM_FFd4)
OR (ram/RefDone AND ram/RS_FSM_FFd8)
OR (ram/RefDone AND ram/RS_FSM_FFd4)
OR (ram/RefDone AND ram/RS_FSM_FFd7)
OR (NOT RefUrg AND NOT RefReq AND ram/RS_FSM_FFd8)
OR (NOT RefUrg AND ram/RS_FSM_FFd8 AND BACTr)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT RefUrg AND
ram/RS_FSM_FFd8)
OR (NOT RefUrg AND nAS_FSB AND ram/RS_FSM_FFd8 AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
ram/RS_FSM_FFd8 AND ram/RASEN)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND ram/RS_FSM_FFd8 AND
ram/RASEN AND fsb/ASrf)
OR (NOT RefUrg AND ram/RS_FSM_FFd7)
OR (ram/DTACKr AND ram/RS_FSM_FFd5));
2023-03-26 08:33:59 +00:00
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,FCLK,'0','0');
2023-07-16 03:21:43 +00:00
nDTACK_FSB_D < = ((NOT QoSReady)
OR (NOT A_FSB(22) AND NOT IONPReady AND NOT RAMReady)
OR (A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16))
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
2023-09-28 06:46:30 +00:00
A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT IONPReady AND NOT nADoutLE1)
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
2023-07-16 06:25:27 +00:00
A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT IONPReady AND NOT nADoutLE1)
2023-07-16 03:21:41 +00:00
OR (A_FSB(23) AND NOT IONPReady)
2023-09-28 06:46:30 +00:00
OR (nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(22) AND A_FSB(21) AND NOT IONPReady)
OR (A_FSB(22) AND A_FSB(20) AND NOT IONPReady));
2023-03-22 01:11:58 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT C16M,'0','0');
2023-04-07 06:33:04 +00:00
nDinLE_D < = (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4);
2022-03-29 08:23:54 +00:00
2023-09-28 06:46:30 +00:00
nDinOE < = NOT (((A_FSB(23) AND cs/nOverlay AND nWE_FSB AND NOT nAS_FSB)
OR (A_FSB(22) AND A_FSB(21) AND cs/nOverlay AND nWE_FSB AND
2023-07-16 06:25:27 +00:00
NOT nAS_FSB)
OR (A_FSB(22) AND A_FSB(20) AND cs/nOverlay AND nWE_FSB AND
2023-09-28 06:46:30 +00:00
NOT nAS_FSB)));
2023-03-22 01:11:58 +00:00
2022-03-29 08:23:54 +00:00
2023-04-09 08:19:06 +00:00
nDoutOE < = NOT (((iobm/DoutOE AND NOT nAoutOE)
OR (NOT iobm/IORDREQr AND iobm/IOS0 AND NOT iobm/IOWRREQr AND
NOT nAoutOE)));
2022-03-29 08:23:54 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB_I,nLDS_IOB,NOT C16M,'0','0');
2023-04-07 06:33:04 +00:00
nLDS_IOB < = ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND IOL0 AND
iobm/IORDREQr)
OR (iobm/IOS_FSM_FFd3 AND IOL0)
OR (iobm/IOS_FSM_FFd4 AND IOL0)
OR (iobm/IOS_FSM_FFd5 AND IOL0)
OR (NOT nLDS_IOB AND iobm/IOS_FSM_FFd6 AND IOL0));
2023-03-26 08:33:59 +00:00
nLDS_IOB < = nLDS_IOB_I when nLDS_IOB_OE = '1' else 'Z';
nLDS_IOB_OE < = NOT nAoutOE;
2022-03-29 08:23:54 +00:00
2023-07-16 06:25:27 +00:00
FDCPE_nOE: FDCPE port map (nOE,nOE_D,FCLK,'0','0');
nOE_D < = ((NOT nWE_FSB)
OR (nAS_FSB AND NOT fsb/ASrf)
2023-09-28 06:46:30 +00:00
OR (ram/DTACKr AND BACTr));
2022-03-29 08:23:54 +00:00
2023-07-16 06:25:27 +00:00
nRAMLWE < = NOT ((NOT nWE_FSB AND NOT nLDS_FSB AND ram/RASEL));
2022-03-29 08:23:54 +00:00
2023-07-16 06:25:27 +00:00
nRAMUWE < = NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND ram/RASEL));
2022-03-29 08:23:54 +00:00
2023-04-01 12:20:02 +00:00
2023-07-16 03:21:43 +00:00
nRAS < = NOT (((ram/RASrf)
OR (ram/RASrr)
2023-07-16 06:25:27 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
ram/RASEN)));
2022-03-29 08:23:54 +00:00
2023-03-26 08:33:59 +00:00
nRES_I < = '0';
nRES < = nRES_I when nRES_OE = '1' else 'Z';
nRES_OE < = NOT nRESout;
2023-03-22 01:11:58 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_nRESout: FDCPE port map (nRESout,nRESout_D,FCLK,'0','0');
2023-04-09 08:19:06 +00:00
nRESout_D < = (cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2);
2023-03-22 01:11:58 +00:00
2022-03-29 08:23:54 +00:00
2023-07-16 06:25:27 +00:00
nROMCS < = NOT (((NOT cs/nOverlay)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20))));
2022-03-29 08:23:54 +00:00
2023-03-26 08:33:59 +00:00
nROMWE < = NOT ((NOT nWE_FSB AND NOT nAS_FSB));
2022-03-29 08:23:54 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB_I,nUDS_IOB,NOT C16M,'0','0');
2023-04-07 06:33:04 +00:00
nUDS_IOB < = ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND IOU0 AND
iobm/IORDREQr)
OR (iobm/IOS_FSM_FFd3 AND IOU0)
OR (iobm/IOS_FSM_FFd4 AND IOU0)
OR (iobm/IOS_FSM_FFd5 AND IOU0)
OR (NOT nUDS_IOB AND iobm/IOS_FSM_FFd6 AND IOU0));
2023-03-26 08:33:59 +00:00
nUDS_IOB < = nUDS_IOB_I when nUDS_IOB_OE = '1' else 'Z';
nUDS_IOB_OE < = NOT nAoutOE;
2022-03-29 08:23:54 +00:00
2023-04-07 06:33:04 +00:00
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB_I,nVMA_IOB_T,C8M,'0','0');
nVMA_IOB_T < = ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
NOT iobm/ES(3))
OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(2) AND NOT iobm/ES(1) AND
NOT iobm/ES(3) AND IOACT AND iobm/VPAr));
2023-03-26 08:33:59 +00:00
nVMA_IOB < = nVMA_IOB_I when nVMA_IOB_OE = '1' else 'Z';
nVMA_IOB_OE < = NOT nAoutOE;
2022-03-29 08:23:54 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_nVPA_FSB: FDCPE port map (nVPA_FSB,nVPA_FSB_D,FCLK,'0',nAS_FSB);
nVPA_FSB_D < = ((A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-16 06:25:27 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND QoSReady AND
2023-09-28 06:46:30 +00:00
IONPReady AND NOT nAS_FSB)
2023-04-07 06:33:04 +00:00
OR (A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-16 06:25:27 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND QoSReady AND
2023-09-28 06:46:30 +00:00
IONPReady AND fsb/ASrf));
2023-03-26 08:33:59 +00:00
2023-07-16 06:25:27 +00:00
FDCPE_ram/DTACKr: FDCPE port map (ram/DTACKr,NOT nDTACK_FSB,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
2023-07-13 20:03:30 +00:00
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,FCLK,'0','0');
2023-07-16 06:25:27 +00:00
ram/RASEL_D < = ((ram/RS_FSM_FFd6)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
ram/RS_FSM_FFd8 AND ram/RASEN)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
ram/RS_FSM_FFd8 AND ram/RASEN AND fsb/ASrf));
FDCPE_ram/RASEN: FDCPE port map (ram/RASEN,ram/RASEN_D,FCLK,'0','0');
2023-09-28 06:46:30 +00:00
ram/RASEN_D < = ((RefUrg AND NOT ram/RefDone AND nAS_FSB AND
2023-07-16 06:25:27 +00:00
NOT ram/RS_FSM_FFd1 AND NOT fsb/ASrf)
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr)
2023-09-28 06:46:30 +00:00
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr AND fsb/ASrf)
2023-07-16 06:25:27 +00:00
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr AND fsb/ASrf)
OR (NOT ram/RS_FSM_FFd8 AND NOT ram/RS_FSM_FFd4 AND
NOT ram/RS_FSM_FFd1)
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd1)
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd1)
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd8 AND
NOT ram/RS_FSM_FFd1)
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RASEN AND
NOT ram/RS_FSM_FFd1));
FDCPE_ram/RASrf: FDCPE port map (ram/RASrf,ram/RS_FSM_FFd6,NOT FCLK,'0','0');
2023-04-07 06:33:04 +00:00
FDCPE_ram/RASrr: FDCPE port map (ram/RASrr,ram/RASrr_D,FCLK,'0','0');
2023-07-16 06:25:27 +00:00
ram/RASrr_D < = ((ram/RS_FSM_FFd7)
2023-09-28 06:46:30 +00:00
OR (IONPReady.EXP)
2023-07-16 06:25:27 +00:00
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
ram/RS_FSM_FFd8)
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
ram/RS_FSM_FFd8)
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd8 AND
2023-09-28 06:46:30 +00:00
NOT ram/RASEN)
OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
ram/RS_FSM_FFd8 AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
ram/RS_FSM_FFd8 AND ram/RASEN)
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd4));
2023-04-07 06:33:04 +00:00
FDCPE_ram/RS_FSM_FFd1: FDCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd2,FCLK,'0','0');
2023-07-16 03:21:43 +00:00
FDCPE_ram/RS_FSM_FFd2: FDCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd3,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
2023-07-16 06:25:27 +00:00
FDCPE_ram/RS_FSM_FFd3: FDCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd7,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
FDCPE_ram/RS_FSM_FFd4: FDCPE port map (ram/RS_FSM_FFd4,ram/RS_FSM_FFd4_D,FCLK,'0','0');
2023-07-16 06:25:27 +00:00
ram/RS_FSM_FFd4_D < = (ram/DTACKr AND ram/RS_FSM_FFd5);
2023-04-07 06:33:04 +00:00
2023-07-16 06:25:27 +00:00
FDCPE_ram/RS_FSM_FFd5: FDCPE port map (ram/RS_FSM_FFd5,ram/RS_FSM_FFd5_D,FCLK,'0','0');
ram/RS_FSM_FFd5_D < = ((ram/RS_FSM_FFd6)
OR (NOT ram/DTACKr AND ram/RS_FSM_FFd5));
2023-04-07 06:33:04 +00:00
FDCPE_ram/RS_FSM_FFd6: FDCPE port map (ram/RS_FSM_FFd6,ram/RS_FSM_FFd6_D,FCLK,'0','0');
2023-07-16 06:25:27 +00:00
ram/RS_FSM_FFd6_D < = ((NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
ram/RS_FSM_FFd8 AND ram/RASEN)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
ram/RS_FSM_FFd8 AND ram/RASEN AND fsb/ASrf));
2023-04-07 06:33:04 +00:00
FDCPE_ram/RS_FSM_FFd7: FDCPE port map (ram/RS_FSM_FFd7,ram/RS_FSM_FFd7_D,FCLK,'0','0');
2023-09-28 06:46:30 +00:00
ram/RS_FSM_FFd7_D < = ((RefUrg AND NOT ram/RefDone AND nAS_FSB AND
ram/RS_FSM_FFd8 AND NOT fsb/ASrf)
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
2023-07-16 06:25:27 +00:00
ram/RS_FSM_FFd8 AND NOT BACTr)
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND
ram/RS_FSM_FFd8 AND NOT BACTr AND fsb/ASrf)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
ram/RS_FSM_FFd8 AND NOT BACTr)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND
ram/RS_FSM_FFd8 AND NOT BACTr AND fsb/ASrf)
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd4)
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
ram/RS_FSM_FFd8)
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
ram/RS_FSM_FFd8)
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd8 AND
2023-09-28 06:46:30 +00:00
NOT ram/RASEN));
2023-07-16 03:21:43 +00:00
FDCPE_ram/RS_FSM_FFd8: FDCPE port map (ram/RS_FSM_FFd8,ram/RS_FSM_FFd8_D,FCLK,'0','0');
2023-07-16 06:25:27 +00:00
ram/RS_FSM_FFd8_D < = ((A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr)
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr AND fsb/ASrf)
2023-09-28 06:46:30 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
NOT ram/RS_FSM_FFd4 AND ram/RASEN AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
2023-07-16 06:25:27 +00:00
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr AND fsb/ASrf)
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd8 AND
NOT ram/RS_FSM_FFd1)
2023-07-16 03:21:41 +00:00
OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
2023-07-16 06:25:27 +00:00
NOT ram/RS_FSM_FFd1 AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd4 AND ram/RASEN AND NOT ram/RS_FSM_FFd1)
OR (NOT ram/RS_FSM_FFd8 AND NOT ram/RS_FSM_FFd4 AND
NOT ram/RS_FSM_FFd1)
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd1)
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd1)
OR (RefUrg AND cs/nOverlay AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd1)
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RASEN AND
NOT ram/RS_FSM_FFd1));
2023-07-16 03:21:41 +00:00
FDCPE_ram/RefDone: FDCPE port map (ram/RefDone,ram/RefDone_D,FCLK,'0','0');
ram/RefDone_D < = ((NOT RefUrg AND NOT RefReq)
2023-07-16 06:25:27 +00:00
OR (NOT ram/RefDone AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd7 AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3));
2023-03-22 01:11:58 +00:00
2022-03-29 08:23:54 +00:00
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
Device : XC95144XL-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC95144XL-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 51 VCC
2 A_FSB< 5 > 52 RA< 7 >
3 A_FSB< 6 > 53 RA< 0 >
4 A_FSB< 7 > 54 RA< 8 >
5 VCC 55 RA< 10 >
6 A_FSB< 8 > 56 RA< 9 >
7 A_FSB< 9 > 57 VCC
2023-03-22 01:11:58 +00:00
8 A_FSB< 10 > 58 C25MEN
2023-04-09 08:19:06 +00:00
9 A_FSB< 11 > 59 KPR
2023-03-22 01:11:58 +00:00
10 A_FSB< 12 > 60 KPR
11 A_FSB< 13 > 61 KPR
2022-03-29 08:23:54 +00:00
12 A_FSB< 14 > 62 GND
13 A_FSB< 15 > 63 RA< 11 >
14 A_FSB< 16 > 64 nRAS
15 A_FSB< 17 > 65 nRAMLWE
16 A_FSB< 18 > 66 nRAMUWE
17 A_FSB< 19 > 67 KPR
18 A_FSB< 20 > 68 KPR
19 A_FSB< 21 > 69 GND
20 A_FSB< 22 > 70 nBERR_FSB
21 GND 71 KPR
2023-03-22 01:11:58 +00:00
22 C16M 72 nBR_IOB
2023-03-25 07:49:44 +00:00
23 C8M 73 KPR
2022-03-29 08:23:54 +00:00
24 A_FSB< 23 > 74 nVMA_IOB
2023-03-22 01:11:58 +00:00
25 E 75 GND
2022-03-29 08:23:54 +00:00
26 VCC 76 nBERR_IOB
2023-03-22 01:11:58 +00:00
27 FCLK 77 nVPA_IOB
2022-03-29 08:23:54 +00:00
28 nDTACK_FSB 78 nDTACK_IOB
29 nWE_FSB 79 nLDS_IOB
30 nLDS_FSB 80 nUDS_IOB
31 GND 81 nAS_IOB
32 nAS_FSB 82 nADoutLE1
33 nUDS_FSB 83 TDO
34 nROMWE 84 GND
35 nROMCS 85 nADoutLE0
36 nCAS 86 nDinLE
37 nOE 87 nAoutOE
38 VCC 88 VCC
39 KPR 89 nDoutOE
40 RA< 4 > 90 nDinOE
41 RA< 3 > 91 nRES
42 RA< 5 > 92 nIPL2
43 RA< 2 > 93 nVPA_FSB
44 GND 94 A_FSB< 1 >
45 TDI 95 A_FSB< 2 >
46 RA< 6 > 96 A_FSB< 3 >
47 TMS 97 A_FSB< 4 >
48 TCK 98 VCC
49 KPR 99 KPR
50 RA< 1 > 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
2023-03-26 08:33:59 +00:00
Pterm Limit : 25
2022-03-29 08:23:54 +00:00
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