Macintosh-HW/Warp-SE
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250 Commits 51 Branches 0 Tags 125 MiB
dev-0.7a-fastiack-noclockgate
Commit Graph

193 Commits

Author SHA1 Message Date
Zane Kaminski
de00b7801e 0.7a-fastiack-noclockgate compiled 2024-10-12 00:30:18 -04:00
Zane Kaminski
d697b086ac 0.7a-fastiack-35us-noclockgate 2024-10-12 00:27:06 -04:00
Zane Kaminski
c666de2126 0.7a-fastiack-35us compiled 2024-10-12 00:19:33 -04:00
Zane Kaminski
57292bccbb 0.7a-fastiack compiled 2024-10-12 00:15:33 -04:00
Zane Kaminski
cd6b04cce1 0.7a-fastscsi-35us compiled 2024-10-12 00:08:33 -04:00
Zane Kaminski
bf23aa4f9d 0.7a-fastscsi-35us-noclockgate compiled 2024-10-12 00:04:30 -04:00
Zane Kaminski
3cf2ffc342 0.6a-fastscsi-noclockgate compiled 2024-10-12 00:01:05 -04:00
Zane Kaminski
e03000dd37 0.7a-fast compiled 2024-10-11 23:55:37 -04:00
Zane Kaminski
b626c9decf 0.7a-35us-noclockgate compiled 2024-10-11 23:51:17 -04:00
Zane Kaminski
2ec96aac2e 0.6a-noclockgate compiled 2024-10-11 23:47:41 -04:00
Zane Kaminski
f7e3ae2376 0.7a-fastscsi compiled 2024-10-11 17:47:15 -04:00
Zane Kaminski
1c2b6508f8 0.7a-slow-noclockgate compiled 2024-10-11 17:44:04 -04:00
Zane Kaminski
be721bbde7 0.7a-slow compiled 2024-10-11 17:40:49 -04:00
Zane Kaminski
317e928a4e 0.7a-35us compiled 2024-10-11 17:37:34 -04:00
Zane Kaminski
381bed2832 0.7a compiled and working 2024-10-11 17:29:20 -04:00
Zane Kaminski
4788ad7fe0 Add settings module power-on reset 2024-10-11 17:28:08 -04:00
Zane Kaminski
d92e235e25 Add slowdown settings 2024-10-11 16:41:31 -04:00
Zane Kaminski
cfe5cf936c Hm actual 0.6i 2024-10-09 08:04:44 -04:00
Zane Kaminski
89e2e575fe 0.6i compiled and working 2024-10-09 08:02:20 -04:00
Zane Kaminski
a9665dd8a8 Add back 68k clock gated slowdown 2024-10-09 08:00:35 -04:00
Zane Kaminski
bc75f67fb2 Output ASrf from FSB unit 2024-10-09 07:59:55 -04:00
Zane Kaminski
6419beb4cf 0.6h compiled and working 2024-10-09 04:29:32 -04:00
Zane Kaminski
6efaf0da6a Make PDS /BR open-drain 2024-10-09 04:17:31 -04:00
Zane Kaminski
1d48cad261 Delete "new old" 2024-10-09 04:17:25 -04:00
Zane Kaminski
ffad08ffb5 Undo I/O R/W gate for now. Will have to re-add this later for new revision with PDS R/W connected to CPLD. 2024-10-09 04:15:23 -04:00
Zane Kaminski
e44991266c 0.6g compiled. Should work but untested 2024-10-08 23:13:39 -04:00
Zane Kaminski
209685c956 Actually assign PDS R/W signal to I/O pin 2024-10-08 22:48:55 -04:00
Zane Kaminski
48633d0847 RAM RefDone reset by RefReqIn only. No longer depends on RefUrg too 2024-10-08 22:48:11 -04:00
Zane Kaminski
14ef33904f Remove BACTr from ROM /WE equation 2024-10-08 21:13:29 -04:00
Zane Kaminski
b21da9baee RAM /OE asynchronously reset by /AS rising 2024-10-08 21:13:18 -04:00
Zane Kaminski
07da9cd645 Revise comments in RAM.v 2024-10-08 21:12:13 -04:00
Zane Kaminski
582def5b32 Gate writes to motherboard RAM/ROM into reads. 2024-10-08 07:32:06 -04:00
Zane Kaminski
da1220315e Fix PDS R/W constraint 2024-10-08 07:30:28 -04:00
Zane Kaminski
28bf6e78ad PDS R/W output in IOBM latches IORW after assertion 2024-10-08 07:21:29 -04:00
Zane Kaminski
8d2f868d42 Turn off FSB data output onto PDS bus when PDS bus idle 2024-10-08 07:21:01 -04:00
Zane Kaminski
6e3d76ad80 Reformat DoutOE equation in IOBM 2024-10-08 07:20:23 -04:00
Zane Kaminski
42657b5167 Revised comments in IOBM 2024-10-08 07:20:01 -04:00
Zane Kaminski
705b15cf47 Gate RAM /OE with RAMCS instead of RAMCS0X 2024-10-08 07:19:35 -04:00
Zane Kaminski
41dc054172 Formatting changes in RAM.v 2024-10-08 07:19:18 -04:00
Zane Kaminski
1f8df60eb7 Add PDS R/W back 2024-10-08 07:18:59 -04:00
Zane Kaminski
6d565f39d4 Remove sound-specific QoS 2024-10-08 07:18:53 -04:00
Zane Kaminski
882b1d9ce6 0.6f compiled and working 2024-10-07 07:54:05 -04:00
Zane Kaminski
11ea9524c4 Better comments in RAM controller 2024-10-07 07:53:56 -04:00
Zane Kaminski
53bc4c08bd New RAM /OE control so it doesn't bus fight 2024-10-07 07:53:41 -04:00
Zane Kaminski
a7632a3057 /ROMWE gated with BACTr 2024-10-07 07:53:23 -04:00
Zane Kaminski
d7b8063e1a Slow slew rate on more outputs 2024-10-07 07:53:13 -04:00
Zane Kaminski
7c6787352b Extra 1/2 FCLK IODONE delay 2024-10-07 06:09:43 -04:00
Zane Kaminski
d14ca62644 Register /DTACK at C16M clock edge instead 2024-10-07 06:09:25 -04:00
Zane Kaminski
b240a054f2 More /VMA setup time matching MC68k timing 2024-10-07 06:09:02 -04:00
Zane Kaminski
d1cce84963 Eliminate IOBERR 2024-10-07 01:37:58 -04:00