Warp-SE

Macintosh-HW/Warp-SE

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0.7a-fastscc-35us

dev

dev-0.6a

dev-0.6b

dev-0.6c

dev-0.6d

dev-0.6e

dev-0.6f

dev-0.6g

dev-0.6h

dev-0.6i

dev-0.7a

dev-0.7a-35us

dev-0.7a-35us-noclockgate

dev-0.7a-fast

dev-0.7a-fastiack-35us

dev-0.7a-fastiack-35us-noclockgate

dev-0.7a-fastiack-fastscc

dev-0.7a-fastiack-fastscc-35us

dev-0.7a-fastiack-fastscc-35us-noclockgate

dev-0.7a-fastiack-fastscc-fastscsi

dev-0.7a-fastiack-fastscc-fastscsi-35us

dev-0.7a-fastiack-fastscc-fastscsi-35us-noclockgate

dev-0.7a-fastiack-fastscc-fastscsi-noclockgate

dev-0.7a-fastiack-fastscc-noclockgate

dev-0.7a-fastiack-fastscsi

dev-0.7a-fastiack-fastscsi-35us

dev-0.7a-fastiack-fastscsi-35us-noclockgate

dev-0.7a-fastiack-fastscsi-noclockgate

dev-0.7a-fastiack-noclockgate

dev-0.7a-fastscc

dev-0.7a-fastscc-35us-noclockgate

dev-0.7a-fastscc-noclockgate

dev-0.7a-fastscsi

dev-0.7a-fastscsi-35us

dev-0.7a-fastscsi-35us-noclockgate

dev-0.7a-fastscsi-noclockgate

dev-0.7a-noclockgate

dev-0.7a-slow

dev-0.7a-slow-noclockgate

dev-0.7b

dev-0.7c

dev-0.7c-fast

dev-0.7c-slow

dev-0.7d

dev-0.7d-fastscc

dev-0.7d-slowscc

dev-0.7e

dev-0.8a

dev-4410B

dev-4411B

f5d0d796bc 0.7e compiled and works dev-0.7e Zane Kaminski 2024-11-04 19:21:23 -0500
04b7cde054 Startup sequence rewritten for shorter LTimer period Zane Kaminski 2024-11-04 19:21:05 -0500
c4d28b3dee Shorten LTimer period Zane Kaminski 2024-11-04 19:20:36 -0500
262a79fe74 Speed up after SCSI access Zane Kaminski 2024-11-04 19:20:22 -0500
d3383f0c02 "Prince of Persia" fix -- more slowdown time after VIA access Zane Kaminski 2024-11-04 19:20:07 -0500
d1f58eb0cc C8M-based POR supports higher fast clock frequencies Zane Kaminski 2024-11-04 19:19:31 -0500
55b93b3a16 Remove old CPLD stuff dev Zane Kaminski 2024-10-22 23:32:36 -0400
20b207a62c Firmware changes for board changes Zane Kaminski 2024-10-22 05:23:24 -0400
fbdfe9464a Board changes Zane Kaminski 2024-10-22 05:23:16 -0400
8987ee3aab Remove overclocking board Zane Kaminski 2024-10-22 05:22:58 -0400
651a2bb0d2 Before switching to SiT2001 oscillator Zane Kaminski 2024-10-20 19:51:31 -0400
a94a40b13a More PLD toward final version Zane Kaminski 2024-10-20 19:51:05 -0400
5721821571 Add OC board Zane Kaminski 2024-10-20 19:51:00 -0400
85a7b6262f Merge branch 'dev-0.8a' into dev Zane Kaminski 2024-10-17 01:03:45 -0400
c0cc50cd7e Just one setting, whether sound accesses trigger slowdown dev-0.8a Zane Kaminski 2024-10-17 00:52:44 -0400
8b54476fc8 Add back settings Zane Kaminski 2024-10-16 23:33:00 -0400
29b1436bad Put back fatsscc Zane Kaminski 2024-10-16 05:59:54 -0400
dcd0e301c8 Add 0.7d-fastscc and slowscc dev-0.7d Zane Kaminski 2024-10-16 00:05:31 -0400
a3da23b94a 0.7d-fastscc compiled and works dev-0.7d-fastscc Zane Kaminski 2024-10-16 00:04:17 -0400
7942e8e6de 0.7d-slowscc compiled and working dev-0.7d-slowscc Zane Kaminski 2024-10-15 23:55:48 -0400
d012753234 0.7d compiled and working Zane Kaminski 2024-10-15 23:31:26 -0400
5608448ee2 idk Zane Kaminski 2024-10-15 22:12:36 -0400
009e0edf75 New QoS with speedup counter Zane Kaminski 2024-10-15 22:12:25 -0400
f94cf51fcd Merge remote-tracking branch 'origin/dev-0.7c' into dev Zane Kaminski 2024-10-15 04:45:31 -0400
f5d5f66521 Go back to 0.7c dev-0.7c Zane Kaminski 2024-10-15 03:43:52 -0400
622efc7916 0.7c-slow compiled and working dev-0.7c-slow Zane Kaminski 2024-10-15 03:41:01 -0400
9447084bb3 0.7c-fast compiled and working dev-0.7c-fast Zane Kaminski 2024-10-15 03:35:45 -0400
8735cfe40c 0.7c compiled and working Zane Kaminski 2024-10-15 03:29:31 -0400
b2561e1d1f Merge branch 'dev-0.7b' into dev Zane Kaminski 2024-10-14 06:14:18 -0400
48cd502a7e 0.7b compiled and working dev-0.7b Zane Kaminski 2024-10-14 00:53:32 -0400
789ed488c3 Clock always gated during sound slowdown but immediately resumes 25 MHz after Zane Kaminski 2024-10-13 17:55:19 -0400
9718db0ebd Make QoS slowdown respect timeout setting Zane Kaminski 2024-10-13 17:54:21 -0400
d53ebd1ba5 Differentiate sound and other I/O QoS selects in CNT Zane Kaminski 2024-10-13 17:54:10 -0400
4cda4a77d5 Change default settings Zane Kaminski 2024-10-13 17:53:43 -0400
a1d07e308f put 0.7a source, .jed, etc back and recompile dev-0.7a Zane Kaminski 2024-10-12 02:20:41 -0400
44f59d8bd1 0.7a-fastiack-fastscc-fastscsi-noclockgate compiled dev-0.7a-fastiack-fastscc-fastscsi-noclockgate Zane Kaminski 2024-10-12 02:17:18 -0400
823c1bf55a 0.7a-fastiack-fastscc-fastscsi-35us-noclockgate compiled dev-0.7a-fastiack-fastscc-fastscsi-35us-noclockgate Zane Kaminski 2024-10-12 02:15:06 -0400
f06f157d29 0.7a-fastiack-fastscc-fastscsi-35us compiled dev-0.7a-fastiack-fastscc-fastscsi-35us Zane Kaminski 2024-10-12 02:13:14 -0400
8d7b09a2f4 0.7a-fastiack-fastscc-fastscsi compiled dev-0.7a-fastiack-fastscc-fastscsi Zane Kaminski 2024-10-12 02:09:30 -0400
23a75bf6db 0.7a-fastiack-fastscc-noclockgate compiled dev-0.7a-fastiack-fastscc-noclockgate Zane Kaminski 2024-10-12 02:05:59 -0400
e5319295b0 0.7a-fastiack-fastscc-35us-noclockgate compiled dev-0.7a-fastiack-fastscc-35us-noclockgate Zane Kaminski 2024-10-12 02:03:13 -0400
14557e03de 0.7a-fastiack-fastscc-35us compiled dev-0.7a-fastiack-fastscc-35us Zane Kaminski 2024-10-12 02:01:19 -0400
2a9538db96 0.7a-fastiack-fastscc compiled dev-0.7a-fastiack-fastscc Zane Kaminski 2024-10-12 01:58:23 -0400
02763c30c3 0.7a-fastscc-noclockgate compiled dev-0.7a-fastscc-noclockgate Zane Kaminski 2024-10-12 01:55:16 -0400
f37b840c8b 0.7a-fastscc-35us-noclockgate dev-0.7a-fastscc-35us-noclockgate Zane Kaminski 2024-10-12 01:50:33 -0400
b4eedc2cb2 0.7a-fastscc-35us compiled 0.7a-fastscc-35us Zane Kaminski 2024-10-12 01:48:28 -0400
20a1763713 0.7a-fastscc compiled dev-0.7a-fastscc Zane Kaminski 2024-10-12 01:45:42 -0400
823de53370 0.7a-fastiack-fastscsi-noclockgate compiled dev-0.7a-fastiack-fastscsi-noclockgate Zane Kaminski 2024-10-12 01:33:05 -0400
581968c5cf 0.7a-fastiack-fastscsi-35us-noclockgate compiled dev-0.7a-fastiack-fastscsi-35us-noclockgate Zane Kaminski 2024-10-12 01:09:12 -0400
1138c88977 0.7a-fastiack-fastscsi-35us compiled dev-0.7a-fastiack-fastscsi-35us Zane Kaminski 2024-10-12 01:02:39 -0400
1ea0196721 0.7a-fastiack-fastscsi dev-0.7a-fastiack-fastscsi Zane Kaminski 2024-10-12 00:39:35 -0400
de00b7801e 0.7a-fastiack-noclockgate compiled dev-0.7a-fastiack-noclockgate Zane Kaminski 2024-10-12 00:30:18 -0400
d697b086ac 0.7a-fastiack-35us-noclockgate dev-0.7a-fastiack-35us-noclockgate Zane Kaminski 2024-10-12 00:27:06 -0400
c666de2126 0.7a-fastiack-35us compiled dev-0.7a-fastiack-35us Zane Kaminski 2024-10-12 00:19:33 -0400
57292bccbb 0.7a-fastiack compiled Zane Kaminski 2024-10-12 00:15:33 -0400
cd6b04cce1 0.7a-fastscsi-35us compiled dev-0.7a-fastscsi-35us Zane Kaminski 2024-10-12 00:08:33 -0400
bf23aa4f9d 0.7a-fastscsi-35us-noclockgate compiled dev-0.7a-fastscsi-35us-noclockgate Zane Kaminski 2024-10-12 00:04:30 -0400
3cf2ffc342 0.6a-fastscsi-noclockgate compiled dev-0.7a-fastscsi-noclockgate Zane Kaminski 2024-10-12 00:01:05 -0400
e03000dd37 0.7a-fast compiled dev-0.7a-fast Zane Kaminski 2024-10-11 23:55:37 -0400
b626c9decf 0.7a-35us-noclockgate compiled dev-0.7a-35us-noclockgate Zane Kaminski 2024-10-11 23:51:17 -0400
2ec96aac2e 0.6a-noclockgate compiled dev-0.7a-noclockgate Zane Kaminski 2024-10-11 23:47:41 -0400
f7e3ae2376 0.7a-fastscsi compiled dev-0.7a-fastscsi Zane Kaminski 2024-10-11 17:47:15 -0400
1c2b6508f8 0.7a-slow-noclockgate compiled dev-0.7a-slow-noclockgate Zane Kaminski 2024-10-11 17:44:04 -0400
be721bbde7 0.7a-slow compiled dev-0.7a-slow Zane Kaminski 2024-10-11 17:40:49 -0400
317e928a4e 0.7a-35us compiled dev-0.7a-35us Zane Kaminski 2024-10-11 17:37:34 -0400
381bed2832 0.7a compiled and working Zane Kaminski 2024-10-11 17:29:20 -0400
4788ad7fe0 Add settings module power-on reset Zane Kaminski 2024-10-11 17:28:08 -0400
d92e235e25 Add slowdown settings Zane Kaminski 2024-10-11 16:41:31 -0400
cfe5cf936c Hm actual 0.6i dev-0.6i Zane Kaminski 2024-10-09 08:04:44 -0400
89e2e575fe 0.6i compiled and working Zane Kaminski 2024-10-09 08:02:20 -0400
a9665dd8a8 Add back 68k clock gated slowdown Zane Kaminski 2024-10-09 08:00:35 -0400
bc75f67fb2 Output ASrf from FSB unit Zane Kaminski 2024-10-09 07:59:55 -0400
6419beb4cf 0.6h compiled and working dev-0.6h Zane Kaminski 2024-10-09 04:29:32 -0400
6efaf0da6a Make PDS /BR open-drain Zane Kaminski 2024-10-09 04:17:31 -0400
1d48cad261 Delete "new old" Zane Kaminski 2024-10-09 04:17:25 -0400
ffad08ffb5 Undo I/O R/W gate for now. Will have to re-add this later for new revision with PDS R/W connected to CPLD. Zane Kaminski 2024-10-09 04:15:23 -0400
e44991266c 0.6g compiled. Should work but untested dev-0.6g Zane Kaminski 2024-10-08 23:13:39 -0400
209685c956 Actually assign PDS R/W signal to I/O pin Zane Kaminski 2024-10-08 22:48:55 -0400
48633d0847 RAM RefDone reset by RefReqIn only. No longer depends on RefUrg too Zane Kaminski 2024-10-08 22:48:11 -0400
14ef33904f Remove BACTr from ROM /WE equation Zane Kaminski 2024-10-08 21:13:29 -0400
b21da9baee RAM /OE asynchronously reset by /AS rising Zane Kaminski 2024-10-08 21:13:18 -0400
07da9cd645 Revise comments in RAM.v Zane Kaminski 2024-10-08 21:12:13 -0400
582def5b32 Gate writes to motherboard RAM/ROM into reads. Zane Kaminski 2024-10-08 07:32:06 -0400
da1220315e Fix PDS R/W constraint Zane Kaminski 2024-10-08 07:30:28 -0400
28bf6e78ad PDS R/W output in IOBM latches IORW after assertion Zane Kaminski 2024-10-08 07:21:29 -0400
8d2f868d42 Turn off FSB data output onto PDS bus when PDS bus idle Zane Kaminski 2024-10-08 07:21:01 -0400
6e3d76ad80 Reformat DoutOE equation in IOBM Zane Kaminski 2024-10-08 07:20:23 -0400
42657b5167 Revised comments in IOBM Zane Kaminski 2024-10-08 07:20:01 -0400
705b15cf47 Gate RAM /OE with RAMCS instead of RAMCS0X Zane Kaminski 2024-10-08 07:19:35 -0400
41dc054172 Formatting changes in RAM.v Zane Kaminski 2024-10-08 07:19:18 -0400
1f8df60eb7 Add PDS R/W back Zane Kaminski 2024-10-08 07:18:59 -0400
6d565f39d4 Remove sound-specific QoS Zane Kaminski 2024-10-08 07:18:53 -0400
882b1d9ce6 0.6f compiled and working dev-0.6f Zane Kaminski 2024-10-07 07:54:05 -0400
11ea9524c4 Better comments in RAM controller Zane Kaminski 2024-10-07 07:53:56 -0400
53bc4c08bd New RAM /OE control so it doesn't bus fight Zane Kaminski 2024-10-07 07:53:41 -0400
a7632a3057 /ROMWE gated with BACTr Zane Kaminski 2024-10-07 07:53:23 -0400
d7b8063e1a Slow slew rate on more outputs Zane Kaminski 2024-10-07 07:53:13 -0400
7c6787352b Extra 1/2 FCLK IODONE delay Zane Kaminski 2024-10-07 06:09:43 -0400
d14ca62644 Register /DTACK at C16M clock edge instead Zane Kaminski 2024-10-07 06:09:25 -0400
b240a054f2 More /VMA setup time matching MC68k timing Zane Kaminski 2024-10-07 06:09:02 -0400