2021-07-23 01:16:23 +00:00
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//
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// Chipset.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 22/07/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef Chipset_hpp
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#define Chipset_hpp
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2021-10-22 03:48:57 +00:00
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#include <algorithm>
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2021-10-09 01:11:47 +00:00
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#include <array>
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2021-10-22 03:48:57 +00:00
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#include <cassert>
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2021-07-23 01:16:23 +00:00
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#include <cstddef>
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#include <cstdint>
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2021-10-04 13:44:54 +00:00
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#include "../../Activity/Source.hpp"
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2021-10-05 22:38:56 +00:00
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#include "../../ClockReceiver/ClockingHintSource.hpp"
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2021-11-11 14:24:15 +00:00
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#include "../../ClockReceiver/JustInTime.hpp"
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2021-10-04 13:44:54 +00:00
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#include "../../Components/6526/6526.hpp"
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2021-10-24 03:17:13 +00:00
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#include "../../Inputs/Mouse.hpp"
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2021-07-26 22:44:20 +00:00
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#include "../../Outputs/CRT/CRT.hpp"
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2021-10-04 13:44:54 +00:00
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#include "../../Processors/68000/68000.hpp"
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2021-10-04 23:45:05 +00:00
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#include "../../Storage/Disk/Controller/DiskController.hpp"
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2021-10-04 15:12:13 +00:00
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#include "../../Storage/Disk/Drive.hpp"
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2021-07-23 01:16:23 +00:00
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2021-11-09 12:11:23 +00:00
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#include "Audio.hpp"
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2021-07-23 01:16:23 +00:00
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#include "Blitter.hpp"
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2021-09-17 01:17:23 +00:00
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#include "Copper.hpp"
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#include "DMADevice.hpp"
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2021-10-13 22:09:19 +00:00
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#include "Flags.hpp"
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2021-11-06 19:03:09 +00:00
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#include "Keyboard.hpp"
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2021-10-04 13:44:54 +00:00
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#include "MemoryMap.hpp"
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2021-07-23 01:16:23 +00:00
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namespace Amiga {
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2021-08-10 00:31:14 +00:00
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enum class DMAFlag: uint16_t {
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AudioChannel0 = 1 << 0,
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AudioChannel1 = 1 << 1,
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AudioChannel2 = 1 << 2,
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AudioChannel3 = 1 << 3,
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Disk = 1 << 4,
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Sprites = 1 << 5,
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Blitter = 1 << 6,
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Copper = 1 << 7,
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Bitplane = 1 << 8,
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AllBelow = 1 << 9,
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BlitterPriority = 1 << 10,
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BlitterZero = 1 << 13,
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BlitterBusy = 1 << 14,
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};
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2021-10-05 22:38:56 +00:00
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class Chipset: private ClockingHint::Observer {
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2021-07-23 01:16:23 +00:00
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public:
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2021-10-04 15:12:13 +00:00
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Chipset(MemoryMap &memory_map, int input_clock_rate);
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2021-07-23 01:16:23 +00:00
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2021-07-24 01:24:07 +00:00
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struct Changes {
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2021-07-26 20:40:42 +00:00
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int interrupt_level = 0;
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2021-07-27 00:13:06 +00:00
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HalfCycles duration;
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2021-08-09 01:52:28 +00:00
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Changes &operator += (const Changes &rhs) {
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duration += rhs.duration;
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return *this;
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}
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2021-07-24 01:24:07 +00:00
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};
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2021-07-27 20:41:18 +00:00
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/// Advances the stated amount of time.
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Changes run_for(HalfCycles);
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/// Advances to the next available CPU slot.
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Changes run_until_cpu_slot();
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2021-07-23 01:16:23 +00:00
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/// Performs the provided microcycle, which the caller guarantees to be a memory access.
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void perform(const CPU::MC68000::Microcycle &);
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2021-07-28 23:36:30 +00:00
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/// Sets the current state of the CIA interrupt lines.
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void set_cia_interrupts(bool cia_a, bool cia_b);
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2021-07-26 20:40:42 +00:00
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/// Provides the chipset's current interrupt level.
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int get_interrupt_level() {
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return interrupt_level_;
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}
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2021-10-05 23:12:30 +00:00
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/// Inserts the disks provided.
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/// @returns @c true if anything was inserted; @c false otherwise.
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bool insert(const std::vector<std::shared_ptr<Storage::Disk::Disk>> &disks);
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2021-07-26 22:44:20 +00:00
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// The standard CRT set.
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void set_scan_target(Outputs::Display::ScanTarget *scan_target);
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Outputs::Display::ScanStatus get_scaled_scan_status() const;
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void set_display_type(Outputs::Display::DisplayType);
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Outputs::Display::DisplayType get_display_type() const;
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2021-10-04 13:44:54 +00:00
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// Activity observation.
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void set_activity_observer(Activity::Observer *observer) {
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cia_a_handler_.set_activity_observer(observer);
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2021-10-06 11:54:40 +00:00
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disk_controller_.set_activity_observer(observer);
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2021-10-04 13:44:54 +00:00
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}
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2021-11-06 19:03:09 +00:00
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Keyboard &get_keyboard() {
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return keyboard_;
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}
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2021-11-12 20:30:52 +00:00
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void flush();
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2021-07-23 01:16:23 +00:00
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private:
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2021-09-15 00:51:32 +00:00
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friend class DMADeviceBase;
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2021-08-09 21:35:09 +00:00
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2021-11-07 13:19:16 +00:00
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// MARK: - E Clock and keyboard dividers.
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2021-10-04 13:44:54 +00:00
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HalfCycles cia_divider_;
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2021-11-07 13:19:16 +00:00
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HalfCycles keyboard_divider_;
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2021-10-04 13:44:54 +00:00
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2021-07-23 01:16:23 +00:00
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// MARK: - Interrupts.
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uint16_t interrupt_enable_ = 0;
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uint16_t interrupt_requests_ = 0;
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2021-07-26 20:40:42 +00:00
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int interrupt_level_ = 0;
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2021-07-23 01:16:23 +00:00
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2021-07-26 20:40:42 +00:00
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void update_interrupts();
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2021-08-10 00:31:14 +00:00
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void posit_interrupt(InterruptFlag);
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2021-07-23 01:16:23 +00:00
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2021-07-27 20:41:18 +00:00
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// MARK: - Scheduler.
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2021-08-09 01:52:28 +00:00
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template <bool stop_on_cpu> Changes run(HalfCycles duration = HalfCycles::max());
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2021-07-28 01:59:27 +00:00
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template <bool stop_on_cpu> int advance_slots(int, int);
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2021-07-27 20:41:18 +00:00
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template <int cycle, bool stop_if_cpu> bool perform_cycle();
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2021-07-28 01:33:07 +00:00
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template <int cycle> void output();
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2021-07-27 20:41:18 +00:00
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// MARK: - DMA Control, Scheduler and Blitter.
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2021-07-23 01:16:23 +00:00
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uint16_t dma_control_ = 0;
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Blitter blitter_;
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// MARK: - Sprites.
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2021-10-22 04:57:46 +00:00
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class Sprite: public DMADevice<1> {
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public:
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using DMADevice::DMADevice;
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void set_start_position(uint16_t value);
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void set_stop_and_control(uint16_t value);
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void set_image_data(int slot, uint16_t value);
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2021-11-13 20:53:41 +00:00
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bool advance_dma(int y);
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2021-10-22 21:32:59 +00:00
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void reset_dma();
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2021-10-22 04:57:46 +00:00
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2021-10-23 02:50:35 +00:00
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uint16_t data[2]{};
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bool attached = false;
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bool active = false;
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2021-10-26 03:58:48 +00:00
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uint16_t h_start = 0;
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2021-10-23 02:50:35 +00:00
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2021-10-22 04:57:46 +00:00
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private:
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2021-10-23 02:50:35 +00:00
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uint16_t v_start_ = 0, v_stop_ = 0;
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2021-10-22 21:32:59 +00:00
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enum class DMAState {
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2021-10-31 23:52:48 +00:00
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Stopped,
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2021-10-22 21:32:59 +00:00
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FetchStart,
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FetchStopAndControl,
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WaitingForStart,
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2021-10-31 23:52:48 +00:00
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2021-10-22 21:32:59 +00:00
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FetchData1,
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FetchData0,
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} dma_state_ = DMAState::FetchStart;
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2021-07-23 01:16:23 +00:00
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} sprites_[8];
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2021-07-23 01:45:51 +00:00
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2021-10-25 23:30:30 +00:00
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class TwoSpriteShifter {
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public:
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/// Installs new pixel data for @c sprite (either 0 or 1),
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/// with @c delay being either 0 or 1 to indicate whether
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/// output should begin now or in one pixel's time.
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template <int sprite> void load(
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uint16_t lsb,
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uint16_t msb,
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int delay);
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/// Shifts two pixels.
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void shift() {
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data_ <<= 8;
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data_ |= overflow_;
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overflow_ = 0;
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}
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2021-10-26 03:58:48 +00:00
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/// @returns The next two pixels to output, formulated as
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2021-10-25 23:30:30 +00:00
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/// abcd efgh where ab and ef are two pixels of the first sprite
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/// and cd and gh are two pixels of the second. In each case the
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/// more significant two are output first.
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uint8_t get() {
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2021-10-26 03:58:48 +00:00
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return uint8_t(data_ >> 56);
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2021-10-25 23:30:30 +00:00
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}
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private:
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uint64_t data_;
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uint8_t overflow_;
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} sprite_shifters_[4];
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2021-08-10 23:01:41 +00:00
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// MARK: - Raster position and state.
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2021-07-23 01:45:51 +00:00
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2021-08-10 23:01:41 +00:00
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// Definitions related to PAL/NTSC.
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2021-11-02 21:34:03 +00:00
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// (Default values are PAL).
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2021-07-28 01:33:07 +00:00
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int line_length_ = 227;
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2021-11-02 21:34:03 +00:00
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int short_field_height_ = 312;
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2021-07-26 22:51:01 +00:00
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int vertical_blank_height_ = 29;
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2021-07-23 02:00:53 +00:00
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2021-08-10 23:01:41 +00:00
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// Current raster position.
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int line_cycle_ = 0, y_ = 0;
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// Parameters affecting bitplane collection and output.
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2021-07-23 02:00:53 +00:00
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uint16_t display_window_start_[2] = {0, 0};
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uint16_t display_window_stop_[2] = {0, 0};
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uint16_t fetch_window_[2] = {0, 0};
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2021-07-26 22:44:20 +00:00
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2021-08-10 23:01:41 +00:00
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// Ephemeral bitplane collection state.
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bool fetch_vertical_ = false, fetch_horizontal_ = false;
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2021-08-12 00:31:37 +00:00
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bool display_horizontal_ = false;
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2021-08-11 01:28:48 +00:00
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bool did_fetch_ = false;
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2021-10-31 16:01:38 +00:00
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uint16_t fetch_stop_ = 0xffff;
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2021-08-10 23:01:41 +00:00
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2021-08-12 00:31:37 +00:00
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// Output state.
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uint16_t border_colour_ = 0;
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bool is_border_ = true;
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int zone_duration_ = 0;
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uint16_t *pixels_ = nullptr;
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void flush_output();
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2021-09-09 00:57:26 +00:00
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struct BitplaneData: public std::array<uint16_t, 6> {
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2021-09-29 02:12:13 +00:00
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BitplaneData &operator <<= (int c) {
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(*this)[0] <<= c;
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(*this)[1] <<= c;
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(*this)[2] <<= c;
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(*this)[3] <<= c;
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(*this)[4] <<= c;
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(*this)[5] <<= c;
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2021-09-09 00:57:26 +00:00
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return *this;
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}
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2021-10-22 03:48:57 +00:00
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void clear() {
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std::fill(begin(), end(), 0);
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}
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2021-09-09 00:57:26 +00:00
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};
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2021-08-11 01:28:48 +00:00
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2021-10-29 18:29:22 +00:00
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class Bitplanes: public DMADevice<6, 2> {
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2021-08-11 01:28:48 +00:00
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public:
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using DMADevice::DMADevice;
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2021-11-13 20:53:41 +00:00
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bool advance_dma(int cycle);
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2021-08-11 01:28:48 +00:00
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void do_end_of_line();
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2021-08-11 22:47:35 +00:00
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void set_control(uint16_t);
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2021-08-11 01:28:48 +00:00
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private:
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bool is_high_res_ = false;
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2021-08-12 00:31:37 +00:00
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int plane_count_ = 0;
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2021-08-11 01:28:48 +00:00
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BitplaneData next;
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} bitplanes_;
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void post_bitplanes(const BitplaneData &data);
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2021-11-01 21:18:58 +00:00
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BitplaneData next_bitplanes_, previous_bitplanes_;
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bool has_next_bitplanes_ = false;
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2021-10-22 03:48:57 +00:00
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2021-11-02 00:15:36 +00:00
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int odd_priority_ = 0, even_priority_ = 0;
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bool even_over_odd_ = false;
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bool hold_and_modify_ = false;
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bool dual_playfields_ = false;
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bool interlace_ = false;
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2021-11-02 10:47:39 +00:00
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bool is_long_field_ = false;
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2021-11-02 00:15:36 +00:00
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2021-10-25 23:30:30 +00:00
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class BitplaneShifter {
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public:
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/// Installs a new set of output pixels.
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void set(
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const BitplaneData &previous,
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const BitplaneData &next,
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int odd_delay,
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int even_delay);
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/// Shifts either two pixels (in low-res mode) and four pixels (in high-res).
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void shift(bool high_res) {
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constexpr int shifts[] = {16, 32};
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data_[1] = (data_[1] << shifts[high_res]) | (data_[0] >> (64 - shifts[high_res]));
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data_[0] <<= shifts[high_res];
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}
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2021-10-22 03:48:57 +00:00
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2021-10-25 23:30:30 +00:00
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/// @returns The next four pixels to output; in low-resolution mode only two
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/// of them will be unique. The value is arranges so that MSB = first pixel to output,
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/// LSB = last. Each byte is formed as 00[bitplane 5][bitplane 4]...[bitplane 0].
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uint32_t get(bool high_res) {
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if(high_res) {
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return uint32_t(data_[1] >> 32);
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} else {
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uint32_t result = uint16_t(data_[1] >> 48);
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result = ((result & 0xff00) << 8) | (result & 0x00ff);
|
|
|
|
result |= result << 8;
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
}
|
2021-10-25 20:34:36 +00:00
|
|
|
|
2021-10-25 23:30:30 +00:00
|
|
|
private:
|
|
|
|
std::array<uint64_t, 2> data_{};
|
2021-10-22 03:48:57 +00:00
|
|
|
|
|
|
|
} bitplane_pixels_;
|
2021-08-10 23:01:41 +00:00
|
|
|
|
2021-08-11 22:47:35 +00:00
|
|
|
int odd_delay_ = 0, even_delay_ = 0;
|
2021-09-20 23:00:52 +00:00
|
|
|
bool is_high_res_ = false;
|
2021-08-11 22:47:35 +00:00
|
|
|
|
2021-07-26 22:44:20 +00:00
|
|
|
// MARK: - Copper.
|
|
|
|
|
2021-09-17 01:17:23 +00:00
|
|
|
Copper copper_;
|
2021-07-30 22:24:27 +00:00
|
|
|
|
2021-11-09 12:11:23 +00:00
|
|
|
// MARK: - Audio.
|
|
|
|
|
2021-11-13 20:53:41 +00:00
|
|
|
Audio audio_;
|
2021-11-09 12:11:23 +00:00
|
|
|
|
2021-07-30 22:24:27 +00:00
|
|
|
// MARK: - Serial port.
|
|
|
|
|
|
|
|
class SerialPort {
|
|
|
|
public:
|
|
|
|
void set_control(uint16_t) {}
|
|
|
|
|
|
|
|
private:
|
|
|
|
uint16_t value = 0, reload = 0;
|
|
|
|
uint16_t shift = 0, receive_shift = 0;
|
|
|
|
uint16_t status;
|
|
|
|
} serial_;
|
2021-07-26 22:44:20 +00:00
|
|
|
|
2021-10-09 11:08:59 +00:00
|
|
|
// MARK: - Pixel output.
|
|
|
|
|
|
|
|
Outputs::CRT::CRT crt_;
|
|
|
|
uint16_t palette_[32]{};
|
2021-11-01 21:44:30 +00:00
|
|
|
uint16_t swizzled_palette_[64]{};
|
2021-10-09 11:08:59 +00:00
|
|
|
|
2021-10-24 03:17:13 +00:00
|
|
|
// MARK: - Mouse.
|
|
|
|
private:
|
2021-10-28 01:38:02 +00:00
|
|
|
class Mouse: public Inputs::Mouse {
|
|
|
|
public:
|
|
|
|
uint16_t get_position();
|
|
|
|
uint8_t get_cia_button();
|
|
|
|
|
|
|
|
private:
|
|
|
|
int get_number_of_buttons() final;
|
|
|
|
void set_button_pressed(int, bool) final;
|
|
|
|
void reset_all_buttons() final;
|
|
|
|
void move(int, int) final;
|
|
|
|
|
|
|
|
uint8_t declared_position_[2]{};
|
|
|
|
uint8_t cia_state_ = 0xff;
|
|
|
|
std::array<std::atomic<int>, 2> position_{};
|
2021-10-24 03:17:13 +00:00
|
|
|
} mouse_;
|
|
|
|
|
|
|
|
public:
|
|
|
|
Inputs::Mouse &get_mouse();
|
|
|
|
|
|
|
|
// MARK: - CIAs.
|
2021-10-09 11:08:59 +00:00
|
|
|
private:
|
|
|
|
class DiskController;
|
|
|
|
|
|
|
|
class CIAAHandler: public MOS::MOS6526::PortHandler {
|
|
|
|
public:
|
2021-10-24 03:17:13 +00:00
|
|
|
CIAAHandler(MemoryMap &map, DiskController &controller, Mouse &mouse);
|
2021-10-09 11:08:59 +00:00
|
|
|
void set_port_output(MOS::MOS6526::Port port, uint8_t value);
|
|
|
|
uint8_t get_port_input(MOS::MOS6526::Port port);
|
|
|
|
void set_activity_observer(Activity::Observer *observer);
|
|
|
|
|
|
|
|
private:
|
|
|
|
MemoryMap &map_;
|
|
|
|
DiskController &controller_;
|
2021-10-24 03:17:13 +00:00
|
|
|
Mouse &mouse_;
|
2021-10-09 11:08:59 +00:00
|
|
|
Activity::Observer *observer_ = nullptr;
|
|
|
|
inline static const std::string led_name = "Power";
|
|
|
|
} cia_a_handler_;
|
|
|
|
|
|
|
|
class CIABHandler: public MOS::MOS6526::PortHandler {
|
|
|
|
public:
|
|
|
|
CIABHandler(DiskController &controller);
|
|
|
|
void set_port_output(MOS::MOS6526::Port port, uint8_t value);
|
|
|
|
uint8_t get_port_input(MOS::MOS6526::Port);
|
|
|
|
|
|
|
|
private:
|
|
|
|
DiskController &controller_;
|
|
|
|
} cia_b_handler_;
|
|
|
|
|
|
|
|
public:
|
|
|
|
using CIAA = MOS::MOS6526::MOS6526<CIAAHandler, MOS::MOS6526::Personality::P8250>;
|
|
|
|
using CIAB = MOS::MOS6526::MOS6526<CIABHandler, MOS::MOS6526::Personality::P8250>;
|
|
|
|
|
|
|
|
// CIAs are provided for direct access; it's up to the caller properly
|
|
|
|
// to distinguish relevant accesses.
|
|
|
|
CIAA cia_a;
|
|
|
|
CIAB cia_b;
|
|
|
|
|
|
|
|
private:
|
2021-08-09 21:35:09 +00:00
|
|
|
// MARK: - Disk drives.
|
|
|
|
|
2021-10-09 00:18:11 +00:00
|
|
|
class DiskDMA: public DMADevice<1> {
|
|
|
|
public:
|
|
|
|
using DMADevice::DMADevice;
|
|
|
|
|
2021-11-03 01:18:59 +00:00
|
|
|
void set_length(uint16_t);
|
|
|
|
void set_control(uint16_t);
|
2021-11-13 20:53:41 +00:00
|
|
|
bool advance_dma();
|
2021-10-09 00:18:11 +00:00
|
|
|
|
|
|
|
void enqueue(uint16_t value, bool matches_sync);
|
|
|
|
|
|
|
|
private:
|
|
|
|
uint16_t length_;
|
|
|
|
bool dma_enable_ = false;
|
|
|
|
bool write_ = false;
|
2021-10-11 13:16:01 +00:00
|
|
|
uint16_t last_set_length_ = 0;
|
2021-11-03 01:18:59 +00:00
|
|
|
bool sync_with_word_ = false;
|
2021-10-09 01:11:47 +00:00
|
|
|
|
|
|
|
std::array<uint16_t, 4> buffer_;
|
|
|
|
size_t buffer_read_ = 0, buffer_write_ = 0;
|
2021-11-03 01:18:59 +00:00
|
|
|
|
|
|
|
enum class State {
|
|
|
|
Inactive,
|
|
|
|
WaitingForSync,
|
|
|
|
Reading,
|
|
|
|
} state_ = State::Inactive;
|
2021-10-09 00:18:11 +00:00
|
|
|
} disk_;
|
|
|
|
|
2021-10-05 22:38:56 +00:00
|
|
|
class DiskController: public Storage::Disk::Controller {
|
2021-10-04 23:45:05 +00:00
|
|
|
public:
|
2021-10-14 23:36:17 +00:00
|
|
|
DiskController(Cycles clock_rate, Chipset &chipset, DiskDMA &disk_dma, CIAB &cia);
|
2021-10-04 23:45:05 +00:00
|
|
|
|
2021-10-05 12:12:01 +00:00
|
|
|
void set_mtr_sel_side_dir_step(uint8_t);
|
|
|
|
uint8_t get_rdy_trk0_wpro_chng();
|
2021-10-04 23:45:05 +00:00
|
|
|
|
2021-10-05 22:38:56 +00:00
|
|
|
void run_for(Cycles duration) {
|
|
|
|
Storage::Disk::Controller::run_for(duration);
|
|
|
|
}
|
|
|
|
|
2021-10-05 23:12:30 +00:00
|
|
|
bool insert(const std::shared_ptr<Storage::Disk::Disk> &disk, size_t drive);
|
2021-10-06 11:54:40 +00:00
|
|
|
void set_activity_observer(Activity::Observer *);
|
2021-10-05 23:12:30 +00:00
|
|
|
|
2021-10-07 12:11:32 +00:00
|
|
|
void set_sync_word(uint16_t);
|
|
|
|
void set_control(uint16_t);
|
|
|
|
|
2021-10-04 23:45:05 +00:00
|
|
|
private:
|
|
|
|
void process_input_bit(int value) final;
|
|
|
|
void process_index_hole() final;
|
|
|
|
|
2021-10-05 12:12:01 +00:00
|
|
|
// Implement the Amiga's drive ID shift registers
|
|
|
|
// directly in the controller for now.
|
|
|
|
uint32_t drive_ids_[4]{};
|
|
|
|
uint32_t previous_select_ = 0;
|
|
|
|
|
2021-10-07 12:11:32 +00:00
|
|
|
uint16_t data_ = 0;
|
|
|
|
int bit_count_ = 0;
|
2021-10-14 23:36:17 +00:00
|
|
|
uint16_t sync_word_ = 0x4489; // TODO: confirm or deny guess.
|
2021-10-07 12:11:32 +00:00
|
|
|
bool sync_with_word_ = false;
|
|
|
|
|
2021-10-14 23:36:17 +00:00
|
|
|
Chipset &chipset_;
|
2021-10-09 00:18:11 +00:00
|
|
|
DiskDMA &disk_dma_;
|
2021-10-09 11:08:59 +00:00
|
|
|
CIAB &cia_;
|
2021-10-09 00:18:11 +00:00
|
|
|
|
2021-10-04 23:45:05 +00:00
|
|
|
} disk_controller_;
|
2021-10-14 23:36:17 +00:00
|
|
|
friend DiskController;
|
2021-10-07 12:11:32 +00:00
|
|
|
|
2021-10-05 22:38:56 +00:00
|
|
|
void set_component_prefers_clocking(ClockingHint::Source *, ClockingHint::Preference) final;
|
|
|
|
bool disk_controller_is_sleeping_ = false;
|
2021-10-07 12:11:32 +00:00
|
|
|
uint16_t paula_disk_control_ = 0;
|
2021-11-06 19:03:09 +00:00
|
|
|
|
|
|
|
// MARK: - Keyboard.
|
|
|
|
|
|
|
|
Keyboard keyboard_;
|
2021-07-23 01:16:23 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* Chipset_hpp */
|