Thomas Harte
90c7056d12
Started devolving timed event loop logic down to the drives, moving them closer to modelling real life.
2017-09-10 14:43:20 -04:00
Thomas Harte
ff510f3b84
Explicitly disallows copying of VIAs, and marks the constructor as noexcept.
2017-09-05 21:21:23 -04:00
Thomas Harte
7fd6699e0b
Corrects comment indentation.
2017-09-05 21:15:15 -04:00
Thomas Harte
450712f39c
Improves and corrects 6522 header documentation.
2017-09-04 14:32:34 -04:00
Thomas Harte
24b3faa427
Deconstitutes the 6522 into component parts, templated and non-templated.
...
Adjusts the Oric, Vic-20 and C-1540 accordingly, albeit with the quickest possible solutions.
2017-09-04 14:26:04 -04:00
Thomas Harte
b30bb2a234
Adds an initial implementation of display skew, as a completely live property.
2017-08-29 22:16:40 -04:00
Thomas Harte
334afbc710
Removes const from get_status and get_register, as both may now logically mutate the object.
2017-08-27 18:13:55 -04:00
Thomas Harte
17c13624e5
Improved comments.
2017-08-27 18:11:40 -04:00
Thomas Harte
113349d272
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 18:10:07 -04:00
Thomas Harte
bdda701207
Reverts previous unevidenced change.
2017-08-26 22:58:16 -04:00
Thomas Harte
487fe83dca
Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments.
2017-08-26 17:54:54 -04:00
Thomas Harte
6c5a03187b
Relocates the HSYNC start test, in order to pass Arnold's cpctest HSYNC start position conformance test.
2017-08-26 17:22:48 -04:00
Thomas Harte
7d7aa2f5d5
Eliminates repetition of the unpacking of register 3 into a horizontal sync count.
2017-08-26 14:37:03 -04:00
Thomas Harte
28550c0227
Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
2017-08-26 13:56:23 -04:00
Thomas Harte
6e99169348
Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.
2017-08-26 12:59:59 -04:00
Thomas Harte
3caa4705ca
Limits sync counter size.
2017-08-26 12:31:19 -04:00
Thomas Harte
039aed1bd1
Switches the two sync counters to upward-going rather than downward, as a more likely match to the way the rest of the 6845 implementation.
2017-08-25 21:26:01 -04:00
Thomas Harte
a914eadc85
Ensured that register 6 is checked on every loop.
2017-08-22 22:17:45 -04:00
Thomas Harte
e956740c56
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-22 21:54:48 -04:00
Thomas Harte
e88a51e75e
Worked logic all the way down to the CPC. If the 8272 announces that it is asleep, it is now no longer clocked. Also very slightly cut down on IRQ line chatter to the Z80.
2017-08-20 12:05:00 -04:00
Thomas Harte
2d9efccc98
Introduced a master 'is sleeping' flag. I'm starting to think there's a pattern forming here.
2017-08-20 10:43:53 -04:00
Thomas Harte
8ce46b6e49
Having spotted that I was using my single-character loop counter names incorrectly (quelle surprise!), got a bit more explicit. Also flattened into a single loop so that I can break rather than returning.
2017-08-20 10:32:09 -04:00
Thomas Harte
669e0caff5
Ensured the head_unload_delay values are properly seeded, and generalised the quick escape.
2017-08-19 22:06:56 -04:00
Thomas Harte
e208f03636
Corrects the US colour palette, effectively undoing what was a mistaken adjustment for the time when Oric-centric phase alignment was built into the CRT based on a false calculation that it wouldn't affect the machines that generate chrominance functionally.
2017-08-16 09:58:34 -04:00
Thomas Harte
cc9d23f23b
Inverted meaning of register_masks, as it's a bit weird that the mask is inverted immediately upon usage. It's a left-over from thinking the unused bits should be 1s; unit tests reveal they should be 0s. Comment updated appropriately.
2017-08-16 09:29:48 -04:00
Thomas Harte
1a831bcf9b
Quick fix: supply the port being written to correctly.
2017-08-16 09:15:57 -04:00
Thomas Harte
82367a2246
Added documentation.
2017-08-16 09:14:56 -04:00
Thomas Harte
3947347d88
Introduces active input handling for the AY and uses it in the CPC to give proper, active keyboard input, rather than push-on-select, which was only ever a temporary hack. Also maps a few more keys for the Amstrad.
2017-08-15 22:47:17 -04:00
Thomas Harte
aefbafa18d
Centralised the 8272's actions of setting the non-DMA execution flag, picking the drive and head and loading the head for accessing commands, and switched error flag if read ID doesn't find anything.
2017-08-15 21:49:10 -04:00
Thomas Harte
d12c834f9c
Increased amount reported.
2017-08-15 20:35:33 -04:00
Thomas Harte
56de5cb2b3
Removed one further logging event.
2017-08-15 20:18:32 -04:00
Thomas Harte
709257a0c5
Quick fix: also treat reception of sync as a reason not to stop looking for a data address mark.
2017-08-15 20:16:56 -04:00
Thomas Harte
75a9d2bb33
Started withdrawing logging, reduced index hole count back to the correct number and tried to increase read_data rigour.
2017-08-15 20:12:01 -04:00
Thomas Harte
73080d6c36
Added an easy way for disk controllers to clamp termination of written data exactly to the index hole.
...
This commit also temporarily provides a whole load of extra logging and minor logic improvements from the 8272. I'm mid-flow on finding a particularly vicious error in its handling of writing; wait for the pull request. But, at least: now waits for the first part of a post-ID gap before writing data, and attempts partially to handle appearance of the index hole during writing a track. More work to do on that though.
2017-08-15 16:05:10 -04:00
Thomas Harte
9d77f33611
Dealt with another source of repeating magic constants: the command numbers.
2017-08-15 11:06:10 -04:00
Thomas Harte
7d132f81f7
Increased logging by quite a distance and made an attempt once again to allow the processor some time to supply the first byte when writing before declaring overrun.
2017-08-15 10:50:28 -04:00
Thomas Harte
6553bf05b4
Corrected multi-sector reads: ensured the incremented sector number isn't replaced by the original, and that the controller returns to scanning mode.
2017-08-14 22:27:31 -04:00
Thomas Harte
0816d3f5a9
Corrected 'read deleted data' command. It's 0xc, not 0xb.
2017-08-14 21:41:20 -04:00
Thomas Harte
55055c7847
Minor: ensured immediate line comparison works. But I think my problem might be trying to do this as straight line logic?
2017-08-14 19:08:20 -04:00
Thomas Harte
cddcd0fb79
Put my money where my mouth is and switched the superclass of WD1770 to MFMController, eliminating duplicated (/factored out) code.
2017-08-14 16:32:53 -04:00
Thomas Harte
a366298022
Factored out the standard [M]FM gap and mark groups, to increase 8272 readability and because it's pretty-much certain I'll need them again if ever I try to tackle e.g. the 8271.
2017-08-14 16:03:35 -04:00
Thomas Harte
4df9307d25
Factored out the dull and repetitious stuff of writing n bytes of the same value.
2017-08-14 15:50:36 -04:00
Thomas Harte
9038ba622e
Added a quick version of read track.
2017-08-14 14:34:56 -04:00
Thomas Harte
7b8bb0297a
Implemented single density version of format track.
2017-08-14 13:03:17 -04:00
Thomas Harte
0da02d3902
Added read/write escape clauses if faced with a read-only disk.
2017-08-14 12:53:18 -04:00
Thomas Harte
2e5ad19fe1
Minor tidying.
2017-08-14 12:42:48 -04:00
Thomas Harte
a10389a22c
Factored out the stuff of stuffing the bus.
2017-08-14 12:42:22 -04:00
Thomas Harte
cefec7a19f
Sought more robustly (i.e. less repetitively) to handle dispatch, including cancelling seeks where appropriate.
2017-08-14 10:37:39 -04:00
Thomas Harte
7264fbb3d2
read_id now clears status. I probably need to find a way to generalise this.
2017-08-14 09:58:55 -04:00
Thomas Harte
8a7b23dc9e
Ensured data-accessing commands cancel seeks on their drives. Also introduced a count of drives currently seeking in order to make for a slightly better broad-phase test in run_for.
2017-08-14 09:45:39 -04:00
Thomas Harte
b7065575f3
Added (empty) call-ins for DMA usage; switched to having the 'is seeking' bit in the status register stay high until sense interrupt status, but now it goes high even for seeks that don't actually go anywhere, and corrected interpretation of the specify command, with a positive result: the received step rate time, now that it's being interpreted correctly, is much shorter.
2017-08-14 09:04:22 -04:00
Thomas Harte
7ea703f150
Started making provisions for a DMA-compatible implementation. Re: the CPC, it sounds like DMA acknowledge might be permanently wired, causing DMA mode seemingly to work from the 8272's point of view.
2017-08-14 08:38:00 -04:00
Thomas Harte
1011143dbe
Sought to correct my interpretation of 'gap 3'.
2017-08-13 21:52:48 -04:00
Thomas Harte
9ace6e1f71
Applied minimum constraints for specified parameters.
2017-08-13 19:25:57 -04:00
Thomas Harte
5221837be8
Fixed Non-DMA flag for the format track execution phase. The emulated machine now provides sector details.
2017-08-13 18:51:06 -04:00
Thomas Harte
e1e9a06712
Made an attempt at format a track.
2017-08-13 18:05:19 -04:00
Thomas Harte
b0a7208cc7
Strung together a very basic version of 8272 write [/deleted] data. Lots of cases as-yet unhandled.
2017-08-13 12:50:07 -04:00
Thomas Harte
eec42aa7ae
Entrusted further status to drives; also adjusted them to report read only if diskless, which I now believe to be correct.
2017-08-13 11:50:49 -04:00
Thomas Harte
5f42022c1d
Added a tester for the control mark.
2017-08-12 17:35:14 -04:00
Thomas Harte
11d0c37506
Attempted to find a more expressive way for maintaining state — macros for all conditions, to bind both values and destinations.
2017-08-12 17:33:52 -04:00
Thomas Harte
27d1dc5c37
Removed some old printfs.
2017-08-12 16:49:20 -04:00
Thomas Harte
7135259cc1
Sought to flesh out error conditions.
2017-08-12 16:36:37 -04:00
Thomas Harte
4909325e79
Implemented read deleted data.
2017-08-12 13:01:17 -04:00
Thomas Harte
a4ee697ed1
Quickie: head unload is scheduled only if the head is presently loaded.
2017-08-12 12:53:45 -04:00
Thomas Harte
0f15a2f97f
Relented: it actually looks like status bytes aren't per-drive. But each drive may fail at seeking individually. So that piece of state accumulates at the 8272 drive.
2017-08-12 12:52:36 -04:00
Thomas Harte
89ace671a4
Corrected unload time. Was 8000 times too short.
2017-08-12 09:44:01 -04:00
Thomas Harte
e7db2a2f6d
Sought to introduce head loading and unloading delays.
2017-08-12 09:36:21 -04:00
Thomas Harte
ffb1a14ace
Minor: clear status registers before a read data.
2017-08-11 18:56:33 -04:00
Thomas Harte
e4f04d0977
Merge branch 'master' into AYFidelity
2017-08-11 14:41:08 -04:00
Thomas Harte
a5593bec79
Threw in support for the light-pen trigger.
2017-08-10 15:00:14 -04:00
Thomas Harte
a1e2646301
Imposed counter size limits.
2017-08-10 14:58:24 -04:00
Thomas Harte
6a6e5ae79c
Forced users of the 6845 to be explicit about which type. So far with no effect.
2017-08-10 12:28:57 -04:00
Thomas Harte
02d792c003
Simplified logic slightly, avoiding repetition.
2017-08-10 11:48:37 -04:00
Thomas Harte
be8e7a4144
Eliminated false register aliasing, restricted register sizes and locked out reading and writing where appropriate.
2017-08-10 11:22:30 -04:00
Thomas Harte
b1dbd7833a
Merge branch 'master' into 6845Address
2017-08-10 11:15:08 -04:00
Thomas Harte
a4c910f1de
This appears to be a more accurate take on 6845 address advancement — it is necessary that character output has finished for the line address to be updated.
2017-08-10 11:12:53 -04:00
Thomas Harte
2eed24e859
Made an initial attempt at [a subset of] multi-sector reads.
2017-08-10 11:11:26 -04:00
Thomas Harte
b11d142cff
Switched to descriptive names.
2017-08-08 20:35:41 -04:00
Thomas Harte
021ff8674e
Added something for sense drive status.
2017-08-08 20:30:54 -04:00
Thomas Harte
e3d1f4fe1e
Subjectively, this might be more correct. It definitely prevents intermediate frequencies. More research required.
2017-08-08 17:58:35 -04:00
Thomas Harte
3bdedfd749
Improved comments.
2017-08-08 07:44:46 -04:00
Thomas Harte
46278ff297
Experimental: is this meant to be a compare-before-increment?
2017-08-07 23:02:29 -04:00
Thomas Harte
390ecec3d9
Added: now declines to pass on output if in input mode for ports A and B.
2017-08-07 19:56:22 -04:00
Thomas Harte
41a30c147d
Adjusted: invalid register selection simply deselects all registers.
2017-08-07 19:51:36 -04:00
Thomas Harte
4709ae80cb
Added port direction tests.
2017-08-07 19:36:55 -04:00
Thomas Harte
7fbb455836
Per the CPC test I'm checking, 0s should be returned for non-retained bits, not 1s.
2017-08-07 19:07:12 -04:00
Thomas Harte
745afd217f
The port input/output flags are now honoured; reading a port that is set as an output returns the current output value.
2017-08-07 19:01:18 -04:00
Thomas Harte
47732ffb98
Prevented the 8272 from overreading ID fields (and, by doing so, overrunning its internal buffer). Exposed the MFMController's CRC generator for inspection.
2017-08-07 12:37:22 -04:00
Thomas Harte
d07f3216ab
Added a broad phase on whether seeking is ongoing.
2017-08-07 12:12:59 -04:00
Thomas Harte
68c73184b1
Had failed to spot that by taking control of stepping at this level, the appropriate invalidate_tracks were not being sent.
2017-08-07 10:36:53 -04:00
Thomas Harte
7f824d6494
Ensured seeks and recalibrates end immediately if no seeking is required.
2017-08-07 10:31:32 -04:00
Thomas Harte
3219212f03
A closer inspection of the data sheet seems to suggest that invalid command sequences will post ST0.
2017-08-07 07:35:41 -04:00
Thomas Harte
d90e35e5bd
Added a bunch of comments, and ensured that the data request bit remains set for the entire period that command bytes are accepted.
2017-08-07 07:27:00 -04:00
Thomas Harte
73f8488150
Reaching the end of the usable part of my day, decided to tidy up a little before bed with indentation that reflects a distinction between top-level entry points and mere loops.
2017-08-06 22:14:18 -04:00
Thomas Harte
3853966a1e
Removed formal storage of ST3, as it just seems to be composed live. This may turn out also to be the best way to deal with ST0–2, time will tell. Also took a stab at the error in responding properly to the ROM's intended use of seek might be accepting new commands as replacements for old ones rather than rejecting them. That didn't seem to do the trick.
2017-08-06 22:10:12 -04:00
Thomas Harte
d63893a437
Collapsed implementations of recalibrate and seek, and decided to intend to go for an upward count on steps taken rather than a downward one. But seek continues presently to fail.
2017-08-06 21:52:52 -04:00
Thomas Harte
90c74043f5
Remembered to toggle off RQM between bytes. CAT now works.
2017-08-06 21:21:59 -04:00
Thomas Harte
600445d90a
Made a first attempt to return sector contents.
2017-08-06 20:40:29 -04:00
Thomas Harte
e4b405fd3d
With the ROM now using a read ID to set its expectations, implemented that and fixed FIND/READ_HEADER macros for multiple use. Execution now reaches the unimplemented section of read data.
2017-08-06 20:32:46 -04:00
Thomas Harte
3b7ecbdf0d
Renamed result_ to result_stack_ to emphasis the fact that it goes backwards. Switched meaning of CB so that it is set for the entire command, execution and result phases.
2017-08-06 20:17:12 -04:00
Thomas Harte
01efb645cb
Took a reasonable gamble that the CHRN reported is from internal registers, not from the last-found header.
2017-08-06 19:57:34 -04:00
Thomas Harte
b5ec1f42d5
Started resetting 'busy' when entering the result phase. AMSDOS now complains of a missing disk after failing to find sector 01. My belief is that it should end up asking for C1. So this is not even getting through a failure to find a sector correctly yet.
2017-08-06 19:48:17 -04:00
Thomas Harte
e9972aa0dd
Added respect for the index-hole limit on reading, and an error phase.
2017-08-06 19:25:44 -04:00
Thomas Harte
1c9a744b01
Made an effort to start inspecting ID fields, at least. Discovered that my emulation has somehow stopped proceeding beyond sense interrupt status though. Fix one in that area: adjust ST0 just in time for the sense interrupt status response, as that'll need to specify the drive number properly.
2017-08-06 18:06:20 -04:00
Thomas Harte
e6d4bb29d8
Discovered correct sense interrupt status result if nobody is in the completed seeking state, and switched to it. It's a single 0x80 rather than two bytes.
2017-08-06 15:34:33 -04:00
Thomas Harte
6c5b562d97
Made an attempt at some of the correct seek/recalibrate behaviour: it's now asynchronous from command processing and able to work on up to four drives at once. I just probably am not yet hitting all the status flags I need to hit.
2017-08-06 15:22:07 -04:00
Thomas Harte
a7103f9333
Disks are now communicated to the 8272. Which is able to handle four of them.
2017-08-06 13:24:14 -04:00
Thomas Harte
c12425e141
Added storage for the extended four status registers, and made an attempt at implementing the two most trivial result-phase commands. Am slightly paused momentarily trying to figure out whether seek activity is orthogonal to read/write activity.
2017-08-06 12:55:57 -04:00
Thomas Harte
89f6de1383
Started on a real ugly-implementation coroutine approach, and implemented specify as a fairly trivial first command: it has no result phase, and is the only thing called by AMSDOS as part of the initialisation sequence.
2017-08-06 12:36:18 -04:00
Thomas Harte
34eaf75352
Fixed WAIT_FOR_TIME macro.
2017-08-06 12:08:54 -04:00
Thomas Harte
29288b690e
Switched disk controllers to be instantiated explicitly in terms of cycles, created an Amstrad-specific subclass of the 8272 to record the direct programmatic availability of all disk motors bundled together, and otherwise adjusted to ensure the thing is clocked and that the motor is enabled and disabled appropriately. The 8272 is also now formally a subclass of the incoming MDM controller.
2017-08-06 09:45:16 -04:00
Thomas Harte
25fd3f7e50
Mildly increased work in here, still primarily oriented towards logging what I actually need to get done.
2017-08-05 22:26:59 -04:00
Thomas Harte
3e984e75b6
Strung up an empty shell that eventually should contain the 8272, and added appropriate IO decoding to the Amstrad.
2017-08-05 19:45:52 -04:00
Thomas Harte
26ce6cdab2
Permitted register 3 to dictate vertical sync length.
2017-08-04 08:56:36 -04:00
Thomas Harte
3ca9c38777
Attempted to move to more accurate bus reading — if control lines are set then all subsequent data inputs should act according to the current control lines; changes to port input should be reflected live upon readings, etc.
2017-08-02 19:45:58 -04:00
Thomas Harte
0267bc237f
Added the ability to set a port input, and relaxed bus state testing. I think my on-demand bus reactions here are inappropriate, so more work to do here probably.
2017-08-01 18:04:51 -04:00
Thomas Harte
e6854ff8db
Corrected typo: the input to an AY is BDIR, not BCDIR.
2017-08-01 17:06:57 -04:00
Thomas Harte
2d4e202be3
Completed dangling comment.
2017-08-01 17:01:36 -04:00
Thomas Harte
64da8e17d1
Fixed: of course this should take a reference to an existing port handler rather than hatching its own; otherwise additional communication with a port handler by an i8255 owner doesn't work as intended.
2017-08-01 17:01:20 -04:00
Thomas Harte
08ad35efd9
It's barely an implementation of the 8255, but ensured that data is bounced into the PortHandler, conveniently assuming the interaction mode used by the CPC.
2017-08-01 16:34:13 -04:00
Thomas Harte
58b98267fc
Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.
2017-08-01 16:15:19 -04:00
Thomas Harte
ace71280a0
Removed implementation file; this is only ever going to be a template.
2017-08-01 16:00:17 -04:00
Thomas Harte
1d99c116e7
Actually, this is probably more correct: increment and then compare, but increment the refresh address once more after the final character, to avoid repeating it.
2017-08-01 15:29:37 -04:00
Thomas Harte
ee27e16fb1
Switched to post-tests increment. Seems to give proper screen width, but also eliminates that 'compare to +1' step that felt unlikely.
2017-08-01 15:19:25 -04:00
Thomas Harte
3b1db14817
Made a quick attempt at properly updating the refresh address.
2017-08-01 07:36:03 -04:00
Thomas Harte
e3f677fa37
I was under-counting row lines. Adjusted comparison. The emulator now produces a solid white square of approximately correct proportions. I'm sure that filling in pixels will reveal the next set of bugs.
2017-07-31 22:21:46 -04:00
Thomas Harte
5c68b6cc21
Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor.
2017-07-31 22:16:08 -04:00
Thomas Harte
ffaa627820
Fixed frame restart when there is no adjustment period.
2017-07-31 22:13:45 -04:00
Thomas Harte
5a396f6787
Added an explicit cast.
2017-07-31 22:04:31 -04:00
Thomas Harte
cb0dc7b434
I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.
2017-07-31 22:01:54 -04:00
Thomas Harte
e28829bd1b
Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
2017-07-31 20:14:46 -04:00
Thomas Harte
68ceeab610
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 19:56:59 -04:00
Thomas Harte
4abd62e62b
Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
2017-07-27 22:05:29 -04:00
Thomas Harte
1da24d10fd
Corrected a couple of build errors.
2017-07-27 08:05:14 -04:00
Thomas Harte
8361756dc4
Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
2017-07-27 07:40:02 -04:00
Thomas Harte
1c2f68f129
Removed, as it's been relocated.
2017-07-25 20:43:05 -04:00
Thomas Harte
75d67ee770
Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
2017-07-25 20:20:55 -04:00
Thomas Harte
a1e9a54765
Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
2017-07-25 20:09:13 -04:00
Thomas Harte
545683df6f
Added some documentation, got explicit again about cycle/half-cycle intermingling, and added flush as what amounts to divide(1), for cleaner usage without a clock divider.
2017-07-25 19:50:40 -04:00
Thomas Harte
cfbd62a5dc
Attempted to fix implementation of divide, and marked everything as-yet unmarked as inline.
2017-07-25 07:43:39 -04:00
Thomas Harte
40339a12e1
Formalised the use of a cycles count with a divider, bringing a few additional plain-int users into the fold.
2017-07-25 07:15:31 -04:00
Thomas Harte
9be9bd9106
Neatened layout.
2017-07-24 22:52:35 -04:00
Thomas Harte
c1527cc9e2
Reduced back-and-forth between Cycles and ints within the Oric.
2017-07-24 22:46:31 -04:00
Thomas Harte
a1a3aab115
Fixed implicit sign conversion.
2017-07-24 22:40:15 -04:00
Thomas Harte
c77a83d86f
The 6560 is now a ClockReceiver. This reduces to zero the number of remaining instances of the text run_for_cycles in this codebase.
2017-07-24 22:38:35 -04:00
Thomas Harte
efdac2ce8c
The 6522 is now a ClockReceiver.
2017-07-24 22:29:09 -04:00
Thomas Harte
2912d7055b
The 6532 is now a ClockReceiver.
2017-07-24 21:57:24 -04:00
Thomas Harte
b7f88e8f61
Filter is now a ClockReciever, affecting all sound output devices.
2017-07-24 21:29:13 -04:00
Thomas Harte
8a2bdb8d22
Converted the TimedEventLoop and the things that sit atop it into ClockReceivers.
2017-07-24 21:19:05 -04:00
Thomas Harte
b82bef95f3
Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
2017-07-24 20:10:05 -04:00
