Thomas Harte
a1c00e9318
Adds BSR tests.
2019-06-28 21:31:41 -04:00
Thomas Harte
241d29ff7c
Imports SBCD and NBCD tests, and fixes corresponding operation.
2019-06-28 19:39:08 -04:00
Thomas Harte
c5039a4719
Imports ANDI, ORI and EORI to SR tests.
...
Hence corrects supervisor/user privileges for SR/CCR.
2019-06-28 15:05:46 -04:00
Thomas Harte
fd604048db
Imports SUBX tests.
2019-06-28 14:30:26 -04:00
Thomas Harte
6a77ed1e07
Imports SUBI test.
2019-06-28 13:53:53 -04:00
Thomas Harte
9e38815ec4
Imports SUBQ tests.
2019-06-28 13:48:02 -04:00
Thomas Harte
86c325c4ec
Imports MOVEA tests.
2019-06-28 13:41:37 -04:00
Thomas Harte
bfcc6cf12c
Imports MULU tests.
...
Timing is wrong for now.
2019-06-28 13:33:41 -04:00
Thomas Harte
8ba8cf7c23
Imports TST tests.
2019-06-28 13:17:21 -04:00
Thomas Harte
651fd9c4a5
Imports EOR tests.
2019-06-28 13:03:27 -04:00
Thomas Harte
5d0db2198c
Imports BRA, EORI CCR and ORI CCR tests, extends PEA tests.
2019-06-27 23:05:00 -04:00
Thomas Harte
da351a3e32
Imports MOVEQ tests.
2019-06-26 22:36:48 -04:00
Thomas Harte
c0591090f5
Imports DIVU tests.
2019-06-26 22:25:48 -04:00
Thomas Harte
538aecb46e
Imports CMP tests, and fixes CMP.l timing.
2019-06-26 22:02:04 -04:00
Thomas Harte
dbdbea85c2
Imports CMPA tests, and fixes CMPA.w.
2019-06-26 21:42:48 -04:00
Thomas Harte
ba2224dd06
Imports NEGX tests and thereby fixes NEGX's zero flag.
2019-06-26 19:39:04 -04:00
Thomas Harte
44e2aa9183
Imports MOVEP tests; code corrections to come.
2019-06-26 19:01:09 -04:00
Thomas Harte
202bff70fe
Imports BCLR and BTST tests.
2019-06-26 17:51:07 -04:00
Thomas Harte
26c0cd7f7c
Imports ADDI tests.
2019-06-26 16:42:23 -04:00
Thomas Harte
cb76301fbe
Imports BCHG tests.
2019-06-26 16:33:23 -04:00
Thomas Harte
8bfa12edf1
Adds lengths to ADD tests, imports ANDI ,CCR and MOVE to CCR.
2019-06-26 16:12:27 -04:00
Thomas Harte
7daa969a5a
Imports SUBA tests.
2019-06-26 15:47:59 -04:00
Thomas Harte
4aeb60100d
Completes import of MOVEM tests.
2019-06-26 15:31:21 -04:00
Thomas Harte
e2c7aaac5a
Imports CLR tests.
2019-06-25 22:47:30 -04:00
Thomas Harte
6ff661c30d
Imports OR tests.
2019-06-25 22:34:04 -04:00
Thomas Harte
79066f8628
Imports NOT tests, fixes NOT overflow and carry flags.
2019-06-25 22:18:11 -04:00
Thomas Harte
2c813a2692
Imports CMPM tests and fixes CMPM.bw source/destination order.
2019-06-25 21:46:01 -04:00
Thomas Harte
cc4abcb00a
Imports ADDQ tests.
2019-06-25 21:19:04 -04:00
Thomas Harte
c1ca85987f
Incorporates MOVE to SR test.
2019-06-25 19:30:51 -04:00
Thomas Harte
ecb5a0b8cc
Incorporates ADDX tests and fixes ADDX PreDec.
2019-06-25 19:18:07 -04:00
Thomas Harte
e12e8fc616
Incorporates ASR tests, and fixes ASR (xxx).w.
...
... which was re-injecting the wrong bit to preserve sign.
2019-06-25 18:44:31 -04:00
Thomas Harte
1fbbf32cd2
Adds ASL tests, and corrects ASL (xxx).w.
...
Overflow is wrong on other ASLs though, I think.
2019-06-25 18:09:01 -04:00
Thomas Harte
d7883d18d4
Imports CHK tests.
...
Proving that I need to do some research on CHK's flags.
2019-06-25 14:55:03 -04:00
Thomas Harte
40100773d3
Imports LSR tests.
2019-06-25 13:57:42 -04:00
Thomas Harte
4048ed3a33
Imports ROR tests.
2019-06-25 13:16:44 -04:00
Thomas Harte
11f2d3cea7
Imports EXT tests.
2019-06-24 22:12:29 -04:00
Thomas Harte
aa656a39b8
Imports SUB tests.
2019-06-24 22:00:37 -04:00
Thomas Harte
e830d23533
Incorporates TRAPV tests.
2019-06-24 21:21:35 -04:00
Thomas Harte
9a666fb8cc
Imports NEG tests and fixes NEG.l Dn timing.
2019-06-24 19:43:30 -04:00
Thomas Harte
0e208ed432
Fixes cycle counting in the test machine.
2019-06-24 17:55:09 -04:00
Thomas Harte
c8b769de8a
Completes import of LSL tests and fixes various LSL issues.
...
Including LSL (xxx).w actually being LSR, and the carry flag generally being questionable.
2019-06-24 17:45:38 -04:00
Thomas Harte
c447655047
Resolves assumption that shifts greater than the bit count of the relevant int are well-defined in C.
2019-06-24 16:51:43 -04:00
Thomas Harte
3ec9a1d869
Incorporates JMP tests, fixes JSR (xxx).l timing.
2019-06-24 15:36:33 -04:00
Thomas Harte
d326886852
Completes BSET tests.
2019-06-24 14:04:08 -04:00
Thomas Harte
faef917cbd
Improves resizeable microcycle test.
2019-06-24 10:55:22 -04:00
Thomas Harte
d27ba90c07
Attempts to introduce more rigour to variable-length instruction handling.
2019-06-24 10:43:28 -04:00
Thomas Harte
db4ca746e3
Introduces BSET tests, fixes BSET timing.
2019-06-23 22:53:37 -04:00
Thomas Harte
d50fbfb506
Imports EXG and PEA tests, and fixes EXG timing.
2019-06-23 22:21:25 -04:00
Thomas Harte
5d283a9f1f
Imports LEA tests.
2019-06-23 21:48:47 -04:00
Thomas Harte
86fdc75feb
Incorporates RTR test, adding a ProcessorState helper.
2019-06-23 18:37:32 -04:00
Thomas Harte
b63231523a
Completes import of ROL tests.
2019-06-23 17:33:12 -04:00
Thomas Harte
70e296674d
Starts import of ROL tests.
...
Including time tests, this time.
2019-06-22 22:42:57 -04:00
Thomas Harte
5089fcd2f6
Makes a slightly futile attempt to resolve Heisen-failures.
2019-06-22 18:52:06 -04:00
Thomas Harte
df2ce8ca6f
Imports MOVE tests.
2019-06-21 22:03:27 -04:00
Thomas Harte
7e209353bb
Imports UNLINK and NOP tests.
2019-06-21 21:29:02 -04:00
Thomas Harte
c2806a94e2
Imports further MOVEM tests.
2019-06-21 21:20:13 -04:00
Thomas Harte
d428120776
Completes import of LINK tests.
2019-06-21 18:33:44 -04:00
Thomas Harte
6b996ae57d
Improves test machine and incorporates a first test of LINK.
2019-06-21 18:20:13 -04:00
Thomas Harte
ccfe1b13cb
Imports DIVS, MULS and MOVE from SR tests.
...
Not all passing.
2019-06-21 16:03:11 -04:00
Thomas Harte
0c1c10bc66
Introduces a test that proves that DIVS' attempt to set proper timing isn't working.
2019-06-20 19:29:02 -04:00
Thomas Harte
fafd1801fe
Introduces first DIVS test, and associated fixes.
2019-06-20 19:02:03 -04:00
Thomas Harte
bcf6f665b8
Simplifies and completes DBcc tests.
...
Subject to omitting a few that look to me like duplicates.
2019-06-20 17:19:25 -04:00
Thomas Harte
bd069490b5
Incorporates approximately half of the DBcc tests.
2019-06-20 16:29:32 -04:00
Thomas Harte
624b0b6372
Adds Scc tests. No implementation fixes required.
2019-06-19 21:42:54 -04:00
Thomas Harte
7976cf5b3c
Adds ADDA tests. All passing without 68000 changes.
2019-06-19 21:31:14 -04:00
Thomas Harte
440f52c943
Incorporates TRAP test.
2019-06-19 21:18:30 -04:00
Thomas Harte
47b1218a68
Adds a couple of the one-shots: SWAP, MOVE USP.
2019-06-19 19:10:36 -04:00
Thomas Harte
91ced056d2
Adds tests for ADD. No failures.
2019-06-19 18:56:21 -04:00
Thomas Harte
8dace34e63
Imports third-party tests for ABCD, and thereby fixes ABCD.
2019-06-19 18:13:06 -04:00
Thomas Harte
b98f10cb45
Substitutes working GCR test.
2019-06-18 14:24:55 -04:00
Thomas Harte
df56e6fe53
Fixed: the sector number also goes into sector bodies.
...
Also the checksum is written in the other order, and the final byte of data isn't output.
2019-06-18 10:34:10 -04:00
Thomas Harte
5c8aacdc17
Fixes the more obvious issues with GCR encoding: byte order, top bit selection.
2019-06-16 17:17:24 -04:00
Thomas Harte
745a5ab749
Introduces failing test of Macintosh GCR data encoding.
2019-06-16 16:53:03 -04:00
Thomas Harte
fe0dc4df88
Starts building out some tests for Apple GCR encoding.
2019-06-15 22:48:24 -04:00
Thomas Harte
5e2496d59c
Simplifies and corrects MOVE logic.
2019-05-28 15:17:03 -04:00
Thomas Harte
c52da9d802
Adds some logging preparatory to a MOVE change.
2019-05-28 15:05:42 -04:00
Thomas Harte
4f9f73ca81
Corrects tests affected by change in run_for_instructions semantics and new program base address.
2019-05-03 15:05:14 -04:00
Thomas Harte
93616a4903
Completes test of a vectored interrupt.
...
Correcting issues uncovered.
2019-05-02 00:00:09 -04:00
Thomas Harte
bb07206c55
Corrects internet response to work as currently implemented.
...
Also makes corrections to the bus error and address error exceptions.
2019-05-01 21:59:06 -04:00
Thomas Harte
e430f2658f
Adds a test and by that means fixes divide-by-zero exception return addresses.
2019-04-29 23:09:50 -04:00
Thomas Harte
7332c64964
Improves testing of function as distinct from timing.
2019-04-29 22:08:37 -04:00
Thomas Harte
d6e16d0042
Adds a test of TOS 1.00, as far as it goes without meaningful hardware.
2019-04-29 18:04:57 -04:00
Thomas Harte
8e02d29ae6
Trims test to length of trace capture.
2019-04-29 17:56:49 -04:00
Thomas Harte
c0e9c37cc7
Improves memory map model, as far as it goes.
2019-04-29 17:27:44 -04:00
Thomas Harte
5b5bfc8445
Applies trace testing to EmuTOS.
2019-04-29 16:55:21 -04:00
Thomas Harte
c466b6f9e7
Factors out the [unit testing] stuff of being a trace-checking 68000 bus handler.
2019-04-29 16:11:01 -04:00
Thomas Harte
407643c575
Tweaks test length slightly to ensure this doesn't run beyond the final line's end.
2019-04-29 15:40:17 -04:00
Thomas Harte
d9071ee9f1
Starts sketching out the asynchronous bus.
2019-04-29 13:45:53 -04:00
Thomas Harte
d9278e9827
Attempts to complete the list of things I can't disassemble.
...
Mysteries to be solved here, definitely. But: 13 missing opcodes remaining.
2019-04-28 23:11:49 -04:00
Thomas Harte
0298b1b3b7
Implements LINK and UNLINK.
...
Also starts excluding opcodes that I can't determine the mapping of from the list of those tested against.
Due to those two things together, the latter incomplete: 627 opcodes outstanding. But only STOP and MOVEP remain on my list of things to implement prior to exceptions.
2019-04-28 17:12:31 -04:00
Thomas Harte
cf547ef569
Improves semantic communications and temporarily omits A- and F-line instructions.
...
So it looks like 2773 instructions left to go.
2019-04-27 15:15:03 -04:00
Thomas Harte
40f68b70c1
Adds quantification of reports.
...
Depressingly; 11,841 opcodes are still missing. Better get on with it!
2019-04-26 13:25:34 -04:00
Thomas Harte
a3b6d2d16e
Corrects test and resolves all instances of opcodes that are valid but shouldn't be.
...
The converse case will require implementation of the remaining instructions.
2019-04-25 22:54:58 -04:00
Thomas Harte
3983f8303f
Introduces failing test of 68000 opcode coverage.
2019-04-25 22:06:05 -04:00
Thomas Harte
7cbd5e0ef6
Imports additional files used as test cases.
2019-04-25 21:43:47 -04:00
Thomas Harte
7df85ea695
Cleans up and formally introduces a comparative source for QL startup.
2019-04-25 15:42:41 -04:00
Thomas Harte
a08043ae88
Ensures that MOVE.b #, (xxx).l writes only a byte.
...
Also rearranges some of the temporary logging functionality.
2019-04-23 19:01:58 -04:00
Thomas Harte
6d6046757d
Fixes predecrementing MOVEM to leave the proper address in the relevant register.
2019-04-22 15:41:09 -04:00
Thomas Harte
44eb4e51ed
Ensures DBcc properly signals program fetches.
2019-04-21 22:54:20 -04:00
Thomas Harte
3cb042a49d
Corrects the carry and extend flags for various long-word operations.
2019-04-21 22:08:18 -04:00
Thomas Harte
0be9a0cb88
Corrects Scc (and other conditionals) for complex addressing modes.
2019-04-20 18:35:19 -04:00
Thomas Harte
ef33b004f9
Corrects word access order of MOVEM.l.
2019-04-20 15:13:12 -04:00
Thomas Harte
2cac4b0d74
Corrects EA usage for ADDA and SUBA.
2019-04-19 23:02:41 -04:00
Thomas Harte
a49f516265
Corrects direction of MOVE [to/from] USP.
2019-04-19 22:41:06 -04:00
Thomas Harte
2d97fc1f59
Beefs up documentation and developer support.
2019-04-19 13:29:35 -04:00
Thomas Harte
ee7ae11e90
Implements EXG and SWAP.
2019-04-19 11:27:43 -04:00
Thomas Harte
c265ea9847
Corrects byte writes in both test machines.
2019-04-17 16:39:10 -04:00
Thomas Harte
b64da2710a
Corrects a few MOVE #s.
2019-04-17 10:00:14 -04:00
Thomas Harte
82b08d0e3a
Corrects addressing behaviour of nRd[+-].
2019-04-17 08:53:34 -04:00
Thomas Harte
62e4c23961
Corrects memory map, causing the RAM test no longer to fail.
2019-04-15 13:03:32 -04:00
Thomas Harte
a223cd90a1
Adds predecrement TSTs, increases QL running time, reduces logging.
2019-04-15 12:36:08 -04:00
Thomas Harte
fba210f7ce
Corrects MOVE.l Dn, (An)[+].
2019-04-15 09:30:49 -04:00
Thomas Harte
52e33e861c
Starts to introduce the QL as a second source for 68000 testing.
...
It's advantageous over the ST in that a commented disassembly of the ROM is available.
2019-04-14 22:15:09 -04:00
Thomas Harte
2ba66c4457
Corrects MOVEA, adds extra test safeguards.
2019-04-12 16:10:17 -04:00
Thomas Harte
06a2f59bd0
Implements DBcc.
2019-04-06 23:21:01 -04:00
Thomas Harte
0af57806da
Adds a hard-coded value sufficient to advance in TOS startup.
2019-04-06 20:00:34 -04:00
Thomas Harte
73e1c8c780
Corrects now-unimplemented ADD/SUB.
2019-04-03 19:43:54 -04:00
Thomas Harte
2c5ff9ada0
Switches to running the real TOS, at least temporarily, and enables better testing.
2019-03-31 22:27:57 -04:00
Thomas Harte
b0b2798f39
Updates to track Swift.
2019-03-27 21:25:51 -04:00
Thomas Harte
47359dc8f1
Adds tests for MOVE.l (An), Dn, and thereby correct their implementation.
2019-03-23 21:41:47 -04:00
Thomas Harte
d7c3d4ce52
Adds test for MOVEA.w (0x1000), A1 and fixes implementation thereof.
2019-03-22 23:27:48 -04:00
Thomas Harte
87420881c8
Extends to a failing test.
2019-03-21 23:32:03 -04:00
Thomas Harte
fdc598f2e1
Starts MOVE tests; in pursuit of which talks the 68000 into obeying run lengths.
2019-03-21 22:30:41 -04:00
Thomas Harte
0d7bbdad54
Begins a basic get/set state API, allowing some actual unit tests, implying an ABCD fix.
2019-03-17 21:57:00 -04:00
Thomas Harte
388d808536
Switches to providing UDS and LDS implicitly via address.
...
Also makes sure that the difference between a non-data cycle that starts without the address strobe active and one that starts with it active can be discerned.
2019-03-16 17:54:58 -04:00
Thomas Harte
720aba3f2d
Adds an implementation of SBCD and slightly neatens syntax for building programs.
2019-03-14 21:22:02 -04:00
Thomas Harte
f9101de956
This might very well be the 68000's first real gasp: performing an ABCD.
2019-03-14 19:32:15 -04:00
Thomas Harte
9e8928aad9
Implements as much as I currently care about of the Atari ST memory map.
2019-03-11 22:47:37 -04:00
Thomas Harte
89c71f9119
Introduces EmuTOS, and starts constructing test cases around it.
2019-03-10 18:40:12 -04:00
Thomas Harte
a4f6db6719
Removes ArrayBuilderTests as the ArrayBuilder is long gone. Disables TIA tests for now.
2019-03-10 18:07:23 -04:00
Thomas Harte
6a93d2d006
Corrects some minor spaces-instead-of-tabs errors.
2019-01-24 22:59:03 -05:00
Thomas Harte
ee89be6730
Removes many stray spaces.
2018-11-23 22:32:32 -05:00
Thomas Harte
a8645f80bf
Introduces 'non-exclusive' emulator-space keyboards.
...
i.e. sets of keys that don't amount to an entire keyboard in the modern sense. Experimentally used by the Master System for its reset key.
2018-10-24 21:59:30 -04:00
Thomas Harte
c07f9fed99
Corrects test and implementation to pass the exhaustive VDP interrupt prediction test.
2018-10-21 18:42:49 -04:00
Thomas Harte
616777517d
Makes the failing test more communicative, in the hope of more easily debugging errors.
2018-10-21 14:35:44 -04:00
Thomas Harte
b3f1677da5
Introduces new failing test for rational continuous interrupt prediction.
2018-10-21 13:59:14 -04:00
Thomas Harte
725b364bbc
Improves testing; now tests for time to the first interrupt.
2018-10-20 18:25:55 -04:00
Thomas Harte
acdc84e08c
Improves test slightly, and fixes line interrupt reload value setting.
2018-10-09 22:14:35 -04:00
Thomas Harte
c128ddb549
Introduces a first unit test for line interrupts and corrects backup behaviour.
2018-10-09 21:49:21 -04:00
Thomas Harte
fc84ae611e
Resolves various instances of spaces in place of tabs.
2018-09-09 20:33:56 -04:00
Thomas Harte
ddf45a0010
Ensures NMI and RST reset D on 65C02s.
2018-08-14 19:49:14 -04:00
Thomas Harte
261fb3d4f8
Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing.
...
This gets Klaus Dorman's test to pass.
2018-08-10 22:42:35 -04:00
Thomas Harte
b63e0cff72
Improves has-completed test.
2018-08-10 22:27:01 -04:00
Thomas Harte
5d6e479338
Implements RMB and SMB, and fixes SBC (zero).
2018-08-10 22:13:51 -04:00
Thomas Harte
90094529a5
Implements TSB and TRB, and adds the extra BIT instructions.
2018-08-10 22:04:45 -04:00
Thomas Harte
aed4c0539e
Implements STZ.
2018-08-10 21:17:02 -04:00
Thomas Harte
95164b79c9
Attempted implementation of (zp) addressing mode.
2018-08-09 21:51:14 -04:00
Thomas Harte
bb680b40d8
Implements the 65C02's JMPs.
2018-08-08 22:26:57 -04:00
Thomas Harte
e3f6da6994
Implements the 65C02 NOPs.
2018-08-08 20:00:14 -04:00
Thomas Harte
32338bea4d
Implements BRA.
2018-08-06 22:37:30 -04:00