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9,327 Commits 7 Branches 121 Tags 500 MiB
93615f6647
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148 Commits

Author SHA1 Message Date
Thomas Harte
93615f6647 Apply new status before entering STOP loop. 2022-06-15 10:50:03 -04:00
Thomas Harte
0ace9634ce Fix MOVEA. 2022-06-14 21:56:48 -04:00
Thomas Harte
48d51759cd At huge copy-and-paste cost, fix MOVE.l. 2022-06-14 21:22:28 -04:00
Thomas Harte
bfd0b683bf Extend MOVE.b fix to cover MOVE.w. 2022-06-14 17:04:11 -04:00
Thomas Harte
61e0f60e94 Add specialised MOVE.b to correct bus sequencing. 
This is a bit of a trial balloon; .w and .l to come.
 2022-06-13 21:49:00 -04:00
Thomas Harte
7fa715e37a Provide more thorough documentation. 2022-06-13 15:27:23 -04:00
Thomas Harte
e066546c13 Resolve PEA timing errors. 2022-06-13 14:08:42 -04:00
Thomas Harte
4a75691005 Avoid double conditional for CalcEffectiveAddressIdleFor8bitDisplacementAndPreDec. 2022-06-13 10:27:22 -04:00
Thomas Harte
8ada73b283 Use the outer switch for addressing mode dispatch, saving a lot of syntax. 2022-06-13 08:57:49 -04:00
Thomas Harte
2a9a05785c Bus and address error don't affect interrupt level. 2022-06-11 21:10:24 -04:00
Thomas Harte
c3345dd839 Fix MOVEM timing. 2022-06-10 21:52:07 -04:00
Thomas Harte
aec4bf9d45 Correct TAS timing. 2022-06-10 15:57:35 -04:00
Thomas Harte
f8643a62e6 Change RTE and RTR read order. 2022-06-09 21:47:28 -04:00
Thomas Harte
64053d697f Take improved guess at address error stacking order. 2022-06-09 16:17:09 -04:00
Thomas Harte
da8e6737c6 Fix standard exception stack write order. 2022-06-08 16:15:11 -04:00
Thomas Harte
ab35016aae Clear any time debt upon phoney reset. 2022-06-08 15:12:32 -04:00
Thomas Harte
079c3fd263 Abort address error-causing exceptions before they begin. 2022-06-08 14:43:31 -04:00
Thomas Harte
8cbf929671 Don't duplicate work that the RESET program already does. 2022-06-08 11:42:56 -04:00
Thomas Harte
9009645cea Add 'reset' functions. 2022-06-07 16:55:39 -04:00
Thomas Harte
a4baa33e2f Ensure RTE triggers a stack pointer change if needed. 2022-06-06 16:08:50 -04:00
Thomas Harte
cfafbfd141 Fix interrupt acknowledge cycle: signals and data size. 2022-06-04 21:23:57 -04:00
Thomas Harte
542126194a Capture interrupt input at the end of an access cycle, not the beginning. 
All still a guess.
 2022-06-03 15:39:53 -04:00
Thomas Harte
02b6ea6c46 Factor out would-accept-interrupt test, per uncertainty re: level 7. 2022-06-03 08:31:56 -04:00
Thomas Harte
6fcaf3571e Fix bus/address error exception frame: order and contents. 2022-06-03 08:27:49 -04:00
Thomas Harte
f8e933438e Add missing tail cost. 2022-06-02 12:26:25 -04:00
Thomas Harte
2bd20446bb Merge branch '68000Mk2' of github.com:TomHarte/CLK into 68000Mk2 2022-06-02 05:39:32 -04:00
Thomas Harte
659e4f6987 Include fixed cost of rolls. Which includes providing slightly more information to did_shift. 2022-06-01 20:30:51 -04:00
Thomas Harte
cd5f3c90c2 Ensure proper resumption after a forced exit in will_perform. 2022-06-01 15:27:09 -04:00
Thomas Harte
91a6911a51 Correct ADDA/SUBA timing. 2022-06-01 15:03:03 -04:00
Thomas Harte
0857dd0ae5 Include fixed base cost in MULU and MULS. 2022-06-01 14:05:23 -04:00
Thomas Harte
62ed1ca2fd Fix MOVE CCR permissions. 2022-06-01 09:22:47 -04:00
Thomas Harte
d1298c8863 Correct MOVE timing without breaking PEA, LEA, etc. 2022-06-01 09:06:08 -04:00
Thomas Harte
75e85b80aa Factor out the common stuff of exception state. 2022-06-01 08:20:33 -04:00
Thomas Harte
d6f72d9862 Avoid runtime checking of instruction supervisor requirements. 2022-05-29 14:56:44 -04:00
Thomas Harte
dbf7909b85 Fix timing of CMPM. 2022-05-29 14:49:42 -04:00
Thomas Harte
57aa8d2f17 Correct timing of ADDQ. 2022-05-29 14:34:06 -04:00
Thomas Harte
35e73b77f4 Fix interrupt stack frame. 2022-05-27 21:55:17 -04:00
Thomas Harte
d17d77714f Remove outdated TODO. 2022-05-27 15:40:06 -04:00
Thomas Harte
e8dd8215ba Tweak per empirical results. 2022-05-27 15:39:02 -04:00
Thomas Harte
e11990e453 Make an attempt at DIVS timing. 2022-05-27 15:38:54 -04:00
Thomas Harte
165ebe8ae3 Add time calculation for MULU and MULS. 2022-05-27 15:38:14 -04:00
Thomas Harte
e746637bee Fill in dynamic cost of shifts. 2022-05-27 15:38:08 -04:00
Thomas Harte
67b340fa5e Fix interrupt request address. 2022-05-27 10:33:36 -04:00
Thomas Harte
c97245e626 Fix CalcEA timing; make MOVEfromSR a read-modify-write. 2022-05-27 10:32:28 -04:00
Thomas Harte
367ad8079a Add a call to set register state with population of the prefetch. 2022-05-25 20:22:05 -04:00
Thomas Harte
80c1bedffb Eliminate false prefetch for BSR. 2022-05-25 16:32:02 -04:00
Thomas Harte
56ad6d24ee Fix ANDI/ORI/EORI to CCR/SR timing. 2022-05-25 16:20:26 -04:00
Thomas Harte
4ad0e04c23 Fix macro for n being an expression. 2022-05-25 16:05:45 -04:00
Thomas Harte
ee58301a46 Add RaiseException macro. 2022-05-25 15:45:09 -04:00
Thomas Harte
72425fc2e1 Fix bus data size of MOVE.b xx, -(An). 2022-05-25 13:00:36 -04:00