Thomas Harte
df29a50738
Attempt to support the DMA interface.
2022-08-31 15:33:48 -04:00
Thomas Harte
ea4bf5f31a
Provide card's SCSI ID.
2022-08-23 15:05:36 -04:00
Thomas Harte
8f2e94a1d8
Switch name back to emphasise _async_.
2022-07-16 14:41:04 -04:00
Thomas Harte
bf03bda314
Generalise AsyncTaskQueue, DeferringAsyncTaskQueue and AsyncUpdater into a single template.
2022-07-14 16:39:26 -04:00
Thomas Harte
55af6681af
Avoid unnecessary get_port_input calls.
2021-11-24 17:15:48 -05:00
Thomas Harte
2a7a42ff8f
Add header for assert.
2021-11-24 16:28:18 -05:00
Thomas Harte
0ad1529f3f
Retain delegate bit length for non-self-clocked data.
2021-11-24 16:15:27 -05:00
Thomas Harte
0df8173536
Merge branch 'master' into Amiga
2021-11-24 08:58:03 -05:00
Thomas Harte
f5d3d6bcea
Splits the lowpass filter into push and pull variants.
2021-11-21 15:37:29 -05:00
Thomas Harte
4fc25fb798
Adds basic shift input.
2021-11-07 05:18:54 -08:00
Thomas Harte
941d9a46a2
Makes a better effort at exposition; better implements clocked line.
2021-11-07 05:18:40 -08:00
Thomas Harte
ecfe68d70f
Introduce the principle that a Serial::Line can be two-wire — clock + data.
2021-11-06 16:54:20 -07:00
Thomas Harte
f102d8a4b4
Extend to allow full-[byte/word/dword] writes, in LSB or MSB order.
2021-11-06 12:01:32 -07:00
Thomas Harte
6d34432988
Starts to build in a serial line for input.
2021-11-04 18:54:28 -07:00
Thomas Harte
b827b9e33e
Add necessary shift storage.
2021-11-03 19:26:45 -07:00
Thomas Harte
29e5ecc282
Add TODOs rather than complete stop on shift register acccesses.
2021-11-02 18:19:31 -07:00
Thomas Harte
9ecd43238f
Correct 8520 TOD setting and getting.
2021-10-30 12:02:43 -07:00
Thomas Harte
5ffe71346c
Eliminate interrupt magic constants.
2021-10-29 19:04:06 -07:00
Thomas Harte
d9d20d9d30
Walk back slightly.
2021-10-14 18:02:58 -07:00
Thomas Harte
689bfbbdb3
Be overt in initialiser list.
2021-10-14 16:57:26 -07:00
Thomas Harte
eb157f15f3
Adds index hole interrupt.
2021-10-09 04:08:59 -07:00
Thomas Harte
73e45511dc
Add missing #include.
2021-10-04 05:26:38 -07:00
Thomas Harte
e47eab1d40
Merge branch 'master' into Amiga
2021-09-14 20:27:59 -04:00
Thomas Harte
dfcd1508c9
Establishes valid initial BRAM.
2021-09-10 19:56:20 -04:00
Thomas Harte
0ca4631279
Switch to zero-initialised state; be more careful about resetting data.
2021-09-09 23:08:13 -04:00
Thomas Harte
a6221ca322
Reload data only if an output is found.
2021-09-09 22:07:03 -04:00
Thomas Harte
f8380d2d4c
Add 8250 feature of 'count, regardless'.
2021-08-08 22:32:41 -04:00
Thomas Harte
1f9e41e9cb
Ensure TOD isn't firing from power-on.
2021-08-08 18:51:58 -04:00
Thomas Harte
98bd6fc240
Adds a further logging hint.
2021-08-06 23:16:06 -04:00
Thomas Harte
b9f78f5d33
Fix final timer B test.
2021-08-03 22:27:23 -04:00
Thomas Harte
b4ec9d70da
Adds the CNT input.
2021-08-03 22:19:41 -04:00
Thomas Harte
dd91d793d9
Correct typo.
2021-08-03 21:45:44 -04:00
Thomas Harte
8e51e8eb77
Does just a touch of 6526 TOD work.
2021-08-03 21:13:08 -04:00
Thomas Harte
6210605bc7
Transfers full TOD responsibility onto the chip-specific templates.
2021-08-03 19:10:09 -04:00
Thomas Harte
0245b040b0
Splits TOD storage by model.
...
TOD storage will probably end up being a full-on class.
2021-08-03 18:50:58 -04:00
Thomas Harte
8795719c18
This counts reloads, most accurately.
2021-08-03 17:12:08 -04:00
Thomas Harte
6bbbf43341
At least attempts to chain correctly.
2021-08-03 17:03:58 -04:00
Thomas Harte
ee6039bfa5
Writes to a timer _during reload_ now have effect.
...
Net: one CIA test passed.
2021-08-03 16:57:05 -04:00
Thomas Harte
ef58ce6277
Gets a bit more rigorous about the clocking stage.
...
Albeit without advancing relative to the test.
2021-08-02 21:04:00 -04:00
Thomas Harte
15de5e98c4
Adds [partial] test for whether counters are linked.
2021-08-02 20:17:37 -04:00
Thomas Harte
38848ca2db
Rationalises reload logic and cuts storage.
...
Failure point is now chaining, I think.
2021-08-02 20:14:01 -04:00
Thomas Harte
77c627e822
Ensure that reading the interrupt flags really clears the master bit.
...
Also makes some guesses on one-shot and reload timing. Alas the test isn't in itself specific enough to be more systematic here.
2021-08-02 07:47:08 -04:00
Thomas Harte
c640132699
Reinstates clocking.
2021-08-01 21:35:08 -04:00
Thomas Harte
57dd38aef2
Reintroduces reload-on-off, adds interrupt delay.
2021-08-01 21:09:02 -04:00
Thomas Harte
460a6cb6fe
Attempts a more literal implementation.
2021-08-01 18:14:10 -04:00
Thomas Harte
3d160ce85f
Add another potential warning.
2021-07-30 18:21:38 -04:00
Thomas Harte
759007ffc1
Attempts to route CIA interrupts.
2021-07-28 19:36:30 -04:00
Thomas Harte
37a55c3a77
Corrects 6526 interrupt control write.
...
This seems to imply that the 6526 should be interrupting too.
2021-07-28 19:26:02 -04:00
Thomas Harte
bcb7bb5cce
Improves logging further.
...
To investigate the new perpetual loop.
2021-07-26 17:02:30 -04:00
Thomas Harte
34d4420e8c
Correct reading of top byte of counter 2.
2021-07-25 20:41:15 -04:00
Thomas Harte
fcd6b7b0ea
Takes further aim at the conters.
...
I think test cases are needed, probably.
2021-07-24 16:06:49 -04:00
Thomas Harte
ceca32ceb3
Takes a guess at one-shot mode.
2021-07-24 15:53:18 -04:00
Thomas Harte
77a8ddb95c
Edges towards working counters.
2021-07-23 22:43:47 -04:00
Thomas Harte
c733a4dbf8
Beefs up interrupt awareness.
2021-07-23 21:58:52 -04:00
Thomas Harte
d898a43dff
Implements time-of-day counters, provisionally.
...
Interrupts to do.
2021-07-23 21:24:07 -04:00
Thomas Harte
6123349b79
Stubs in control registers and disables exit-on-miss.
...
I think I may be running up against the limits of stubbing now. Probably time to implement some stuff.
2021-07-22 19:28:01 -04:00
Thomas Harte
56b62a5e49
Adds a dummy interrupt control register.
2021-07-22 16:09:32 -04:00
Thomas Harte
a030d9935e
Adds port input.
2021-07-18 20:25:04 -04:00
Thomas Harte
c425dec4d5
Makes some attempt to get as far as the overlay being disabled.
2021-07-18 17:17:41 -04:00
Thomas Harte
67d53601d5
Latch and return data direction.
...
Albeit with no port-handling effect yet.
2021-07-18 12:23:47 -04:00
Thomas Harte
622cca0acf
Adds sufficient address decoding to print a more helpful exit message.
2021-07-18 12:13:56 -04:00
Thomas Harte
48999c03a5
Adds concept of time, captured port handler.
2021-07-18 11:49:10 -04:00
Thomas Harte
377cc7bdcd
Start to introduce a 6526/8250.
2021-07-18 11:36:13 -04:00
Thomas Harte
a5d0976c2d
Eliminate unused #includes.
2021-07-18 11:35:57 -04:00
Thomas Harte
ae05010255
Improve indentation.
2021-07-18 11:29:26 -04:00
Thomas Harte
66cacbd0e0
Be overt about the type being supplied.
2021-07-18 11:28:18 -04:00
Thomas Harte
c8699d9770
Correct Disk II sleeping test to allow for spin-down.
2021-07-16 17:12:57 -04:00
Thomas Harte
69c0734975
WD1770: switch motor on even if spin-up is disabled.
2021-06-21 23:26:55 -04:00
Thomas Harte
1d5144b912
Correct no-interrupt signal.
2021-06-04 22:38:07 -04:00
Thomas Harte
b7a62e0121
Adds SZX support.
...
Tweaking exposed Spectrum state object as relevant.
2021-04-26 20:47:28 -04:00
Thomas Harte
3348167c46
Ensures AY registers are conveyed.
2021-04-26 17:39:11 -04:00
Thomas Harte
73c8157197
Retain 6850 time tracking at all times.
2021-04-20 22:26:43 -04:00
Thomas Harte
af1dc2d3b2
Switches to correct non-value sentinel.
2021-04-20 21:56:58 -04:00
Thomas Harte
1266bbb224
Makes the TMS a sequence-point-generating JustInTimeActor.
2021-04-05 21:02:37 -04:00
Thomas Harte
8a11a5832c
Uses GI::AY38910::Utility far and wide.
2021-03-26 23:19:47 -04:00
Thomas Harte
f37f89a7d3
Merge branch 'master' into ZXSpectrum
2021-03-21 22:44:37 -04:00
Thomas Harte
58be770eaa
Factors out some boilerplate.
...
When I'm confident this is correct, I can fix up the other call sites.
2021-03-21 00:14:48 -04:00
Thomas Harte
650b9a139b
Tweak Master System blue scale.
2021-03-19 08:38:21 -04:00
Thomas Harte
6839e9e3b3
Ensures no double definition of NDEBUG.
2021-03-07 12:52:54 -05:00
Thomas Harte
86fd47545d
Silences.
2021-03-03 20:51:33 -05:00
Thomas Harte
71a107fe75
Silences the IWM again, for now.
2021-02-23 21:57:19 -05:00
Thomas Harte
a3e98907ca
Removes temporary printf.
2021-02-14 21:03:54 -05:00
Thomas Harte
ee5f45c979
Merge branch 'master' into AppleIIgs
2020-12-29 22:16:23 -05:00
Thomas Harte
dfe4e49110
Ensure proper in-memory ordering of the b72a2c70 ROM.
2020-12-29 22:08:48 -05:00
Thomas Harte
8ace258fbc
Tackles outstanding GCC warnings.
2020-11-22 21:43:56 -05:00
Thomas Harte
9b45c5a1cd
Resolves out-of-bounds reads.
2020-11-21 22:36:10 -05:00
Thomas Harte
4a42de4f18
Attempts to add 5.25" drive support to the IIgs.
...
I want to try some classic software.
2020-11-20 21:37:17 -05:00
Thomas Harte
98347cb1c3
Starts in the direction of audio support.
2020-11-18 18:39:11 -05:00
Thomas Harte
cddd72876f
Flips meaning of ejected bit, to please the IIgs.
2020-11-18 17:20:48 -05:00
Thomas Harte
37815a982a
Much logging later, corrects 7Mhz IWM windows.
...
Confirmed by mathematics — the new ones are seven-eighths the length of the established 8Mhz windows — and with reference to suitable Apple documentation.
2020-11-13 22:05:45 -05:00
Thomas Harte
b0fc2f6ecf
Amps up logging.
...
Current suspicion is that the IIgs isn't getting a clean byte stream, never mind whether my assumption of exactly-Mac-style GCR holds (which it probably doesn't).
2020-11-12 21:54:54 -05:00
Thomas Harte
81969bbea9
Improves logging, at least for now.
2020-11-12 21:17:14 -05:00
Thomas Harte
1f5908dc51
Corrects logging output.
2020-11-11 20:26:04 -05:00
Thomas Harte
72884c3ead
Does a better job of shifting output; takes a new guess at the no-receiver case.
...
ROM03 at least now reaches "check startup device!"
2020-11-11 20:19:35 -05:00
Thomas Harte
80358cf5bd
Shift output even if nobody is listening.
2020-11-11 20:04:48 -05:00
Thomas Harte
6d511f01a4
Ensures intended no-drive behaviour; no more risks with dangling pointers or nullptr.
2020-11-11 17:54:21 -05:00
Thomas Harte
6d3d7c6006
It seems like this fix is no longer needed.
2020-11-11 17:30:22 -05:00
Thomas Harte
03d1aff6c0
Fixes 8-bit read/write.
2020-10-30 22:17:55 -04:00
Thomas Harte
034056d0cd
Adds full 8-bit clock addressing; stubs clock into the IIgs.
2020-10-29 21:38:36 -04:00
Thomas Harte
1249fb598b
Factors Apple's RTC out of the Macintosh.
2020-10-29 21:03:02 -04:00
