Thomas Harte
3a05ce36de
Adds a reference to the calling keyboard in reset_all_keys.
2017-10-14 22:07:11 -04:00
Thomas Harte
4f289ab10b
Corrects some deficiencies in Vic-20 keyboard mapping.
...
... albeit without yet being clear on the wiring behind restore.
2017-10-12 22:33:00 -04:00
Thomas Harte
78ee46270b
Transfers possession of keyboard mappings from the Mac side over to individual machines.
...
Specifically by establishing an intermediate representation of a useful mix between the American and British IBM and Mac keyboard layouts, and routing through that.
2017-10-12 22:25:02 -04:00
Thomas Harte
97a2be71e3
Introduces flush_tracks to Drive, while switching its interface to using Track::Address and adjusting associated integer types.
2017-10-06 21:45:12 -04:00
Thomas Harte
edb9fd301c
Begins this project's conversion to functional-style casts.
2017-10-03 22:04:15 -04:00
Thomas Harte
698e4fe550
Tidies the Disk file hierarchy.
2017-09-22 22:39:23 -04:00
Thomas Harte
da082673d7
Drives now have a finite number of heads.
...
The Amstrad volunteers itself to be single sided. Everything else stays as it was.
2017-09-15 21:18:36 -04:00
Thomas Harte
42616da7ff
Adjusts the Oric Microdisc to propagate motor control more widely.
2017-09-11 22:15:54 -04:00
Thomas Harte
2f13517f38
Adjusts the 1770 not to talk directly to the drive about motor status.
2017-09-11 22:10:56 -04:00
Thomas Harte
fb9fd26af7
Updates the 1540 for the slightly-more modern world of decoupled drives and disks (!).
2017-09-11 22:08:10 -04:00
Thomas Harte
d3c385b471
Separates the 8272's drive selection signalling from actual drive ownership.
...
Thereby returns working motor control to the CPC.
2017-09-11 21:25:26 -04:00
Thomas Harte
96bf133924
Withdraws requirement for DiskController users to specify a PLL multiplier or to provide rotation speed.
...
In the latter case because it's no longer of any interest to the controller, and in the former because I'd rather it be picked automatically.
2017-09-10 22:56:05 -04:00
Thomas Harte
0622187ddf
Strips Controller of all capabilities now housed on the Drive.
2017-09-10 19:23:23 -04:00
Thomas Harte
90c7056d12
Started devolving timed event loop logic down to the drives, moving them closer to modelling real life.
2017-09-10 14:43:20 -04:00
Thomas Harte
3b12fca417
Corrects non-recurring-pattern adaptation bug: the 'SerialPortVIA' should keep a reference to its VIA, not a copy of it.
2017-09-05 21:19:56 -04:00
Thomas Harte
8eeb7e73cd
Adds a commented-out printf that I might like to use again later.
2017-09-05 21:15:56 -04:00
Thomas Harte
6547102511
Attempts better to hide C1540 implementation details from the reader.
...
In this case not from the compiler, as it's desireable to keep `run_for` as a non-virtual call, and therefore everything else comes alone for the ride.
2017-09-04 20:58:00 -04:00
Thomas Harte
a49594c6a3
Tweaks Vic20 Machine parent class order so that when turned into a CRTMachine, still successfully dynamically casts as a ConfigurationTarget.
...
More thorough thought is required.
2017-09-04 20:56:00 -04:00
Thomas Harte
a42ca290cb
Reformulates the Oric more cleanly into the modern world.
...
Specifically: now that the implementation is contained within the CPP file, there's no need to embed the keyboard, tape player and VIA port handler as private classes. Also the pain of additional syntax is reduced, so the keyboard has been bumped up to a fully data-hiding class. I've also transferred overall ownership of the tape player, AY and keyboard up to the Oric itself, with the VIA merely being wired to them, and added a whole bunch of extra documentation.
2017-09-04 18:22:14 -04:00
Thomas Harte
da09098e49
Updates clipped area per latest CRT response to vertical sync.
2017-09-04 17:51:02 -04:00
Thomas Harte
24b3faa427
Deconstitutes the 6522 into component parts, templated and non-templated.
...
Adjusts the Oric, Vic-20 and C-1540 accordingly, albeit with the quickest possible solutions.
2017-09-04 14:26:04 -04:00
Thomas Harte
96648df5fe
Ensures all parts of the Electron have a fully-defined initial state.
...
Specifically to resolve an error with shift being pressed at startup due to a failure to establish a default value for that flag, but applying the same principle across the board.
2017-08-31 22:29:24 -04:00
Thomas Harte
53a88a7e12
Causes the ZX80/81 to omit support for the wait line if being configured as a ZX80.
2017-08-27 16:45:36 -04:00
Thomas Harte
4a66dd9e82
Arranges for the ZX80/81 to get a peek at target configuration prior to construction. I'm as yet undecided on whether to make this the norm.
2017-08-27 16:42:16 -04:00
Thomas Harte
57bfec285f
Makes it optional whether the Z80 supports the wait line. If the wait line isn't in use, runtime costs are decreased because the optional wait cycles need not be iterated over.
2017-08-26 23:08:57 -04:00
Thomas Harte
e7ad79c79a
Breaks apart the CPC's 6845 bus handler to obey phase 1 and phase 2, and now back-dates interrupts when appropriate.
2017-08-26 14:07:51 -04:00
Thomas Harte
6e99169348
Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.
2017-08-26 12:59:59 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Thomas Harte
cde29c4bf4
Added forceinlines and properly declared finals and overrides.
2017-08-21 21:07:10 -04:00
Thomas Harte
e1aded0d95
Allows Z80 users to opt out of support for the bus request line. Which both now do.
2017-08-21 20:43:12 -04:00
Thomas Harte
0cbc1753b9
Quick fixes: the binary tape player now considers talk to the sleep observer only if motor control changes. The Amstrad CPC no longer attempts to use the component argument to identify the caller, since this will often be that of the superclass and not that of the derived class known to the CPC.
2017-08-20 13:18:46 -04:00
Thomas Harte
8f5ae4a326
The CPC now responds to tape-originating sleeper observations.
2017-08-20 12:21:02 -04:00
Thomas Harte
e88a51e75e
Worked logic all the way down to the CPC. If the 8272 announces that it is asleep, it is now no longer clocked. Also very slightly cut down on IRQ line chatter to the Z80.
2017-08-20 12:05:00 -04:00
Thomas Harte
f2699a3f2b
Okay, even if releasing it is unsafe, I can at least move the typer so that it is no longer called.
2017-08-20 10:24:01 -04:00
Thomas Harte
85253a5876
Sought further to reduce the processing footprint of palette changes by updating only those table entries that are affected by a change.
2017-08-20 10:13:23 -04:00
Thomas Harte
911ee5a0d3
At least added a fast return.
2017-08-19 22:22:51 -04:00
Thomas Harte
57c5b38a6d
Step one towards cutting much of this cost: build only the table that's appropriate for the current mode, and at least declare when a more minimal change would be sufficient.
2017-08-19 22:19:46 -04:00
Thomas Harte
f68565a33f
Split the static analyser functionality so that it's possible just to ask for the set of media implied by a particular file. Extended ConfigurationTarget so that media alone can be pushed to a machine.
2017-08-17 10:48:29 -04:00
Thomas Harte
b476f06524
Slowed the typer, having discovered that otherwise it has problems transitioning from a shifted to an unshifted character.
2017-08-16 22:12:16 -04:00
Thomas Harte
925e774015
Added a decent portion of documentation. But started feeling like I should address my various ownership decisions. Which would justify a separate pull request.
2017-08-16 16:23:33 -04:00
Thomas Harte
4c15e46fd1
Performed the normative removal from public view of Vic-20 implementation details. Which were hefty.
2017-08-16 16:05:30 -04:00
Thomas Harte
75208b0762
Moves the Electron implementation behind a more opaque interface, in line with changes elsewhere.
2017-08-16 15:33:40 -04:00
Thomas Harte
903a17ae11
Corrected typo and removed replication of what's already declared formally.
2017-08-16 14:53:03 -04:00
Thomas Harte
de1c526789
Cut the amount disclosed by the Atari 2600 for public inspection down to the minimum, relocating implementation into the .cpp.
2017-08-16 14:52:40 -04:00
Thomas Harte
148591b7f2
Hid most of the Oric innards, and corrected a potential multi-thread access error emanating from the Mac side of the world.
2017-08-16 14:35:53 -04:00
Thomas Harte
3c148f5721
Fixed clanger of an error.
2017-08-16 14:02:46 -04:00
Thomas Harte
360c8a99a3
Adjusted Atari2600 actually to use the nominated type of bus extender.
2017-08-16 12:57:32 -04:00
Thomas Harte
06e31f5102
Consequential to the 6502 change, severs the Atari 2600's cartridge container from its former attempt at runtime polymorphism, in favour of each cartridge's specific hardware being defined as a 'bus extender'.
2017-08-16 12:39:15 -04:00
Thomas Harte
42b5b66305
Remove the 6502's use of runtime polymorphism in favour of ordinary templating.
2017-08-16 11:56:52 -04:00
Thomas Harte
3947347d88
Introduces active input handling for the AY and uses it in the CPC to give proper, active keyboard input, rather than push-on-select, which was only ever a temporary hack. Also maps a few more keys for the Amstrad.
2017-08-15 22:47:17 -04:00
Thomas Harte
334872d374
Clarified, slightly.
2017-08-14 12:47:11 -04:00
Thomas Harte
7ea703f150
Started making provisions for a DMA-compatible implementation. Re: the CPC, it sounds like DMA acknowledge might be permanently wired, causing DMA mode seemingly to work from the 8272's point of view.
2017-08-14 08:38:00 -04:00
Thomas Harte
3831fbaca2
Ensured the ZX80 and '81 also provide the necessary hook for destruction.
2017-08-11 12:11:01 -04:00
Thomas Harte
1d8edf58dd
Ensured that a virtual destructor is declared, so that the various automatically-generated real constructors get in on the action.
2017-08-11 12:07:48 -04:00
Thomas Harte
4785e316ff
Now with exposition.
2017-08-11 11:36:03 -04:00
Thomas Harte
44da9de5b0
Tweaked typing timing expectations.
2017-08-11 11:35:28 -04:00
Thomas Harte
4ecd093891
Fixed test for termination of a key sequence; the previous error will have seen this reduce all multi-key sequences to just the one, and expand single-key sequences to "probably" two, posting an out-of-bounds code to the machine at completion.
2017-08-11 11:35:14 -04:00
Thomas Harte
dd4bc87d52
Fixed: should be a full-path #ifdef guard, given that this is one of the classes named relative to its namespace.
2017-08-11 11:21:33 -04:00
Thomas Harte
570d25214e
Made an initial attempt at typer support for the CPC.
2017-08-11 11:21:07 -04:00
Thomas Harte
cf810d8357
Minor: ensure the CRT is set to output as a monitor.
2017-08-10 14:42:47 -04:00
Thomas Harte
4961fda2a9
Ensured counter-intuitive CRTC writes get through, taking the opportunity to correct my handling of port IO in general: selecting multiple devices for input results in a logical AND (i.e. open collector mode), and both the CRTC and gate array will receive data from 'input's if applicable.
2017-08-10 12:39:19 -04:00
Thomas Harte
6a6e5ae79c
Forced users of the 6845 to be explicit about which type. So far with no effect.
2017-08-10 12:28:57 -04:00
Thomas Harte
484524d781
Implements RAM paging. The 6128 is now emulated.
2017-08-08 16:01:56 -04:00
Thomas Harte
a7103f9333
Disks are now communicated to the 8272. Which is able to handle four of them.
2017-08-06 13:24:14 -04:00
Thomas Harte
29288b690e
Switched disk controllers to be instantiated explicitly in terms of cycles, created an Amstrad-specific subclass of the 8272 to record the direct programmatic availability of all disk motors bundled together, and otherwise adjusted to ensure the thing is clocked and that the motor is enabled and disabled appropriately. The 8272 is also now formally a subclass of the incoming MDM controller.
2017-08-06 09:45:16 -04:00
Thomas Harte
3e984e75b6
Strung up an empty shell that eventually should contain the 8272, and added appropriate IO decoding to the Amstrad.
2017-08-05 19:45:52 -04:00
Thomas Harte
9e8645ca7a
Fixed ROM paging port decoding. It should have been fd00 if completely decoded, not df00, but also shouldn't be completely decoded.
2017-08-05 19:24:03 -04:00
Thomas Harte
caf3ac0645
Sought: (i) to instruct the CPC that it should be a 664, not a 464, if given a disk image (at least until I have RAM paging implemented for a 6128); (ii) to support ROM selection within the CPC and allow paging in of AMSDOS.
2017-08-05 19:20:38 -04:00
Thomas Harte
4b19cf60df
Added omitted semicolon.
2017-08-05 09:18:55 -04:00
Thomas Harte
b3788fed41
Fixed AY queuing behaviour as handled by the Amstrad. I think I need to come up with clearer semantics here.
2017-08-05 09:12:17 -04:00
Thomas Harte
a63aa80dc9
Merge branch 'master' of github.com:TomHarte/CLK
2017-08-04 16:51:52 -04:00
Thomas Harte
63f57c8c4f
Adjusted visible portion of frame; completely empirical, as I'm chasing a machine that shipped with a monitor.
2017-08-04 16:51:46 -04:00
Thomas Harte
f075fea78c
Introduces filtering of the CRTC's vsync signal into the gate array.
2017-08-04 16:36:55 -04:00
Thomas Harte
c0f0c68f4f
Corrects quick-hack version of border drawing: the assumption that the colour must be the same over a plotted period. Also corrects my entry for colour 15.
2017-08-04 12:13:05 -04:00
Thomas Harte
d9097facf1
Found documentation that makes more sense, and in practice seems to be more correct: the test after vertical sync is for greater than 32, not less. Also I decided to chance my arm on counter reset also resetting interrupt request. The raster effects of Ghouls 'n' Ghosts is now pretty much correct but one line off. I think probably either something is off in my wait-two logic on the post-vsync timer event, or possibly the vsync bit exposed via the PPI doesn't mean exactly what I think it means.
2017-08-04 08:56:09 -04:00
Thomas Harte
b927500487
Clarified code a little, but this is mostly fiddling in the margins.
2017-08-03 22:00:30 -04:00
Thomas Harte
e71eabedf9
Fixed timer clearing tet.
2017-08-03 21:30:04 -04:00
Thomas Harte
33ed27c3ad
Minor tidiness: included missing headers, and spaced out the ROM type and key lists for readability.
2017-08-03 12:45:42 -04:00
Thomas Harte
575b1dba75
Formally declared the ZX80/81 and Amstrad CPC as keyboard machines in their public interface. Which means not having to repeat the meaning of set_key_state and clear_all_keys. So: a minor DRY improvement.
2017-08-03 12:38:22 -04:00
Thomas Harte
bbb17acf3a
Expanded interface so that an external machine caller can request a string be typed without any knowledge of whatever it intends to do re: CharacterMappers. Which is immediately useful in paste functionality.
2017-08-03 11:50:50 -04:00
Thomas Harte
ad3a98387f
Within the Typer framework: hatched out CharacterMapper as a distinct thing from the target for keypresses, better to formalise responsibility but also to make it easy cleanly to sever that stuff into its own little part.
2017-08-03 11:42:31 -04:00
Thomas Harte
2f2071be8a
These should actually both be in the public header, as the types are used in an exposed method.
2017-08-02 22:18:30 -04:00
Thomas Harte
6d510e4e70
Made it no longer public knowledge that any sort of Typer is involved in being a ZX80/81.
2017-08-02 22:17:22 -04:00
Thomas Harte
8e0736fbe6
Reinstated typing ability, albeit with an ugly inline insertion. But I think I can defer dealing with typers to another pull request. The whole issue of keyboard mapping probably needs reappraisal.
2017-08-02 22:16:09 -04:00
Thomas Harte
681d1e2f8d
Breaking its typer for now, adapted the ZX80/81 to having a Z80, not being one.
2017-08-02 22:12:59 -04:00
Thomas Harte
42e70ef993
Adjusted slightly as per Z80 change, and to pull everything internally declared into the Amstrad CPC namespace.
2017-08-02 22:11:03 -04:00
Thomas Harte
d3bf8fa53b
Upped the documentation.
2017-08-02 20:37:26 -04:00
Thomas Harte
f5e2dd410e
Constrained output to the centre 90%.
2017-08-02 19:55:44 -04:00
Thomas Harte
e50adf1cc8
Were my TZX support up to it, this would likely be sufficient for tape emulation.
2017-08-02 13:50:14 -04:00
Thomas Harte
dcab10f53e
Ensured the AY's async queue doesn't just fill and fill.
2017-08-02 07:38:35 -04:00
Thomas Harte
f602f9b6ec
Adds an attempt to clock the AY.
2017-08-02 07:21:33 -04:00
Thomas Harte
4d5d5041df
Attempted to ensure a clean startup.
2017-08-01 22:18:42 -04:00
Thomas Harte
587eb3a67c
Factored interrupt counting out of the CRTCBusHandler.
2017-08-01 22:15:39 -04:00
Thomas Harte
8d39a20088
Added proper output of mode 3, were anything ever to try to use it.
2017-08-01 21:51:41 -04:00
Thomas Harte
4b6370eb86
Realised my colour error: mapping the ROM numbers as though they were the hardware numbers. Having fixed that, spotted that I was deserialising R and B the wrong way around and dividing by too much. Colours now appear to be correct.
2017-08-01 21:47:52 -04:00
Thomas Harte
c6e340a8a2
Wired up the vsync signal. Pen 15 no longer flashes like crazy. Still can't figure out why the palette is so askew; was looking for perhaps some sort of detection of a green screen rather than a colour one, but there's no obvious input for that.
2017-08-01 21:21:59 -04:00
Thomas Harte
31c7153301
Corrected bit to colour mapping for modes 0 and 1. The total palette is still way off but there's consistency between modes now.
2017-08-01 20:52:42 -04:00
Thomas Harte
7e04d00cc1
Fixed key values, causing the new set of keys to work, decreased quantity of output and ensured that pixels appear in modes 0 and 2.
2017-08-01 20:39:10 -04:00
Thomas Harte
eca9586a0f
Fixed: input value is no longer overwritten by 0xff. The '0' key now works.
2017-08-01 20:19:02 -04:00
Thomas Harte
2e4577f741
Made a game attempt at implementing a (sticky) keyboard. No effect yet.
2017-08-01 17:52:05 -04:00
Thomas Harte
f5b278d683
Added enough stuff to put the emulated Amstrad CPC in a state of knowing whether its '0' key is pressed.
2017-08-01 17:31:56 -04:00
Thomas Harte
e6854ff8db
Corrected typo: the input to an AY is BDIR, not BCDIR.
2017-08-01 17:06:57 -04:00
Thomas Harte
3b292273c7
Fixed: BC2 is always implicitly set. The machine is now periodically checking the AY's register 14 (i.e. the first input port), so probably there's enough here now to implement keyboard input.
2017-08-01 17:05:11 -04:00
Thomas Harte
cb732e5d5f
Made an attempt to wire in an [unclocked] AY, in an endeavour to get to keyboard reading.
2017-08-01 17:01:58 -04:00
Thomas Harte
08ad35efd9
It's barely an implementation of the 8255, but ensured that data is bounced into the PortHandler, conveniently assuming the interaction mode used by the CPC.
2017-08-01 16:34:13 -04:00
Thomas Harte
58b98267fc
Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.
2017-08-01 16:15:19 -04:00
Thomas Harte
a27946102a
Took a shot at the interrupt counter. Attempts at keyboard reading now recur so it'll probably do for now. I think that next puts me into the realm of needing to implement the 8255.
2017-08-01 15:49:16 -04:00
Thomas Harte
6ac7132799
Had a quick go at properly outputting Mode 1, adding wiring to communicate palette and mode changes to the CRTC bus handler. Colours are off but it's sufficient for now.
2017-08-01 15:16:13 -04:00
Thomas Harte
ca42abab70
Doubled up to ensure that every byte that should be inspected is represented. This makes it clearer that I'm on the right road. A garbled version of 'Amstrad 64k Microcomputer' can be discerned, in a weird grayscale and with the right-hand column missing and skewed output as a result.
2017-08-01 07:56:44 -04:00
Thomas Harte
933d69a256
Fixed slightly: the CPC wiki has a typo. It's 12 and 13 that move up to 14 and 15.
2017-08-01 07:51:13 -04:00
Thomas Harte
10a5581aea
Made first attempt at offering some sort of pictographic of actual RAM contents.
2017-08-01 07:34:12 -04:00
Thomas Harte
3ae699964f
Ensured an actual pixel stream is supplied for pixel regions. Though it's just a long stream of white pixels for now. So visual output is unchanged.
2017-08-01 07:24:29 -04:00
Thomas Harte
9d953421d8
After a quick check, added a couple of other _delegate initialisations. I should probably find a way to template this.
2017-08-01 07:07:43 -04:00
Thomas Harte
763e3b65d1
Ensured a proper initial value for delegate_.
2017-07-31 22:46:06 -04:00
Thomas Harte
42dd27c9b1
Shunted method bodies inline, given that there's no need for a declaration/definition distinction.
2017-07-31 22:39:25 -04:00
Thomas Harte
3df13cddd4
As per my keenness for cleanliness improvements corresponding to my ever-increasing C++ ability: turned the Amstrad into something that a factory produces, allowing me completely to hide a bunch of implementation details.
2017-07-31 22:32:04 -04:00
Thomas Harte
c2253c1e0f
Fixed multiplier: the dot clock I've used to instantiate the CRT is the pixel clock, not the character clock.
2017-07-31 22:17:46 -04:00
Thomas Harte
f742fd5d4a
Made basic attempt to get something on screen: white where the display is enabled, black for the border.
2017-07-31 22:13:20 -04:00
Thomas Harte
69b99fe127
Transferred ownership of the CRT to the CRTC bus handler, to give it easy access.
2017-07-31 22:04:52 -04:00
Thomas Harte
e28829bd1b
Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
2017-07-31 20:14:46 -04:00
Thomas Harte
68ceeab610
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 19:56:59 -04:00
Thomas Harte
68dca9d047
Made a first attempt at ROM paging, with pretty much the same scheme that'll be needed for 128kb support.
2017-07-31 19:37:28 -04:00
Thomas Harte
d88ca151f4
Added a first attempt at output port decoding. Just logging for now.
2017-07-31 19:25:10 -04:00
Thomas Harte
3c90218c3d
With a very basic stab at something a bit like the memory map (sans paging), execution begins.
2017-07-31 19:15:43 -04:00
Thomas Harte
afd409c883
Ensured that ROM images are loaded and passed to the Amstrad CPC.
2017-07-31 18:44:49 -04:00
Thomas Harte
9c04d851e4
Added the basics necessary to get the CPU ticking over, at a nominal 4Mhz but with the wait states that I currently believe to be accurate.
2017-07-31 07:29:50 -04:00
Thomas Harte
1d6fe11906
Added an instance of Outputs::CRT::CRT. So progress is now: select CDT, up comes a blank window.
2017-07-31 07:16:51 -04:00
Thomas Harte
c0f1313830
Performed sufficient wiring to get to the point where attempting to load a CDT creates an instance of the Amstrad CPC and then fails only because the thing vends a nullptr CRT.
2017-07-30 22:05:29 -04:00
Thomas Harte
4abd62e62b
Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
2017-07-27 22:05:29 -04:00
Thomas Harte
968d2bb8ba
Brought Typer into the new run_for orthodoxy, making it easier to clock consistently regardless of unit. Which necessitated adding a negative operator for WrappedInts.
2017-07-27 21:53:45 -04:00
Thomas Harte
9ef232157b
Revoked the operator bool() on WrappedInt as providing an indirect means for implicit but incorrect assignment to unwrapped ints. Got explicit about run_for intention and simplified HalfClockReceiver slightly by building a lossy and a flushing conversion to Cycles into HalfCycles. Adapted the all-RAM Z80 properly to return HalfCycles.
2017-07-27 21:38:50 -04:00
Thomas Harte
8848ebbd4f
Formalised set_interrupt_line's optional parameter as being a count of HalfCycles; corrected PartialMachineCycle.is_wait and effected the proper timing for counter reset on a ZX81.
2017-07-27 21:10:14 -04:00
Thomas Harte
8361756dc4
Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
2017-07-27 07:40:02 -04:00
Thomas Harte
81a3899381
Adjusted the Z80 formally to communicate in terms of half cycles rather than whole.
2017-07-26 19:42:00 -04:00
Thomas Harte
cda223ffc0
Added explicit signedness cast.
2017-07-25 22:49:03 -04:00
Thomas Harte
966b5e6372
Adapted the Z80's perform_machine_cycle to return Cycles.
2017-07-25 22:25:44 -04:00
Thomas Harte
279c369a1f
Switched to Cycles as the result from the 6502 perform_bus_operation, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
2017-07-25 22:21:09 -04:00
Thomas Harte
d9c6b3bcf7
Corrected TIA's WSYNC lookahead to accept Cycles.
2017-07-25 22:13:41 -04:00
Thomas Harte
296c7cec05
Adopted flush widely.
2017-07-25 20:42:51 -04:00
Thomas Harte
75d67ee770
Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
2017-07-25 20:20:55 -04:00
Thomas Harte
a1e9a54765
Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
2017-07-25 20:09:13 -04:00
Thomas Harte
8d1dacd951
Clean ups along the Electron::Tape line: ensured that the ClockReceiver is opted into only once, and that its run_for propagates all the way along the chain.
2017-07-25 20:01:30 -04:00
Thomas Harte
40339a12e1
Formalised the use of a cycles count with a divider, bringing a few additional plain-int users into the fold.
2017-07-25 07:15:31 -04:00
Thomas Harte
90bf6565d0
Reduced int/Cycle conversions in the Electron and on the Atari 2600, where the current framework makes it possible to do so.
2017-07-24 22:53:13 -04:00
Thomas Harte
c1527cc9e2
Reduced back-and-forth between Cycles and ints within the Oric.
2017-07-24 22:46:31 -04:00
Thomas Harte
c77a83d86f
The 6560 is now a ClockReceiver. This reduces to zero the number of remaining instances of the text run_for_cycles in this codebase.
2017-07-24 22:38:35 -04:00
Thomas Harte
a6e377aa57
The Electron's video is now a ClockReceiver.
2017-07-24 22:36:42 -04:00
Thomas Harte
9435c1e12a
The 1540 is now a ClockReceiver.
2017-07-24 22:32:41 -04:00
Thomas Harte
efdac2ce8c
The 6522 is now a ClockReceiver.
2017-07-24 22:29:09 -04:00
Thomas Harte
2912d7055b
The 6532 is now a ClockReceiver.
2017-07-24 21:57:24 -04:00
Thomas Harte
55ecb0c022
Converted the Microdisc into a ClockReceiver.
2017-07-24 21:51:13 -04:00
Thomas Harte
13f7aa4063
The TIA is now a ClockReceiver.
2017-07-24 21:48:34 -04:00
Thomas Harte
915f587ef1
Updated the Electron's tape class to be a ClockReceiver.
2017-07-24 21:36:30 -04:00
Thomas Harte
b7f88e8f61
Filter is now a ClockReciever, affecting all sound output devices.
2017-07-24 21:29:13 -04:00
Thomas Harte
8a2bdb8d22
Converted the TimedEventLoop and the things that sit atop it into ClockReceivers.
2017-07-24 21:19:05 -04:00
Thomas Harte
b82bef95f3
Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
2017-07-24 20:10:05 -04:00
Thomas Harte
ba088e5545
Adapted the Z80 into a clock receiver, which also vends Cycles rather than a raw int within its PartialMachineCycle struct. The objective is to update it to vend HalfCycles within its struct, but I think I need to do some work on cycle/half-cycle arithmetic first.
2017-07-23 22:15:04 -04:00
Thomas Harte
6369138bd1
Converted the Oric's video output into a ClockReceiver.
2017-07-22 23:11:30 -04:00
Thomas Harte
c2a7dffa7d
Converted the ZX80/81 video component into a ClockReceiver. As it happens, it's most convenient to take the half-cycle bus here.
2017-07-22 23:02:28 -04:00
Thomas Harte
2ff157cf7a
Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.
2017-07-22 22:17:29 -04:00
Thomas Harte
83628b285b
Experimentally turned the 6502 into a clock receiver. No problem encountered.
2017-07-22 21:52:21 -04:00
Thomas Harte
1bbb4cb478
Increased documentation.
2017-07-22 17:39:51 -04:00
Thomas Harte
d46da6ac9d
Added documentation.
2017-07-22 17:31:12 -04:00
Thomas Harte
dddb30477b
Used a different inner-loop variable, for clarity.
2017-07-21 21:52:08 -04:00
Thomas Harte
37459a3ebc
Fixed parameter shadowing.
2017-07-21 21:51:18 -04:00
Thomas Harte
3f609e17b3
Factored out the table-lookup approach to being a typer, and adjusted so as definitely to limit myself to positive offset table lookups.
2017-07-21 21:18:51 -04:00
Thomas Harte
2471ef805b
Fixed signed/unsigned comparison and potential negative table reference.
2017-07-21 20:45:49 -04:00
Thomas Harte
a3e0024980
Chopped time accumulation out of the default Tape process because it's proving to be sufficiently expensive for a TZX as not to be worthwhile. Introduced a cheaper position capturing/restoring method.
2017-07-21 18:55:03 -04:00
Thomas Harte
44e5a03cf2
Removed just-don't-power-the-tape approach to pausing and playing, in favour of being fully communicative.
2017-07-19 19:21:27 -04:00
Thomas Harte
b3861ff755
Reduced copying of Pulses.
2017-07-16 19:49:31 -04:00
Thomas Harte
1d3ae31755
Abstracted the concept of an Acorn shifter away from being a PLLParser. The Acorn tape parser now skips using that class and uses the shifter. The actual Electron also uses the shifter. So the two are completely aligned. Net result: the Electron should successfully load exactly when static analysis was successful.
2017-07-16 19:24:01 -04:00
Thomas Harte
f931cd582d
Switched to use of std::vector in those few remaining places where I was still using a unique_ptr to a native type and newing for myself. So, some of my earliest bits of code.
2017-07-16 13:54:07 -04:00
Thomas Harte
481487f084
Oh yuck, it looks like I've repeated this same test in two different places. Must figure out where to factor it out to. But in the meantime, the emulated Electron has just loaded its first CSW.
2017-07-13 22:39:30 -04:00
Thomas Harte
ac59dd8b1d
Added enough typing to issue a load command. No thoughts as to running yet though.
2017-07-09 22:07:12 -04:00
Thomas Harte
353c854734
Removed a TODO that is no longer appropriate.
2017-07-09 22:06:50 -04:00
Thomas Harte
3e5c209039
Added basic Typer support for the ZX80 and '81.
2017-07-09 22:00:34 -04:00
Thomas Harte
ed28260aaf
Hardens the ZX80/81 video routines to ensure they never try to push data into the future and don't double-count time when pixels would ostensibly run into sync. You could previously see the CRT being handed negative run lengths if sync interrupted pixels or if a run of more than 320 pixels (my arbitrary buffer size) occurred, with corresponding poor behaviour given my use of unsigned numbers.
2017-07-09 19:33:05 -04:00
Thomas Harte
87658e83c1
Moved line counter reset logic; I think this is actually correct.
2017-07-09 00:05:30 -04:00
Thomas Harte
4509c3ce34
By observation, it appears that disabling vsync occurs on any port output whatsoever, as long as NMI isn't blocking it.
2017-07-08 21:01:52 -04:00
Thomas Harte
30e93979d2
Removed data work if sync is enabled; in that case no data is output.
2017-07-08 21:01:07 -04:00
Thomas Harte
d6b87053bf
Introduced an explicit record of whether a video byte is latched. It's definitely incorrect to treat the latching of 0 as equivalent to no latching, as the byte that will eventually become video is not strongly implied.
2017-07-08 20:40:19 -04:00
Thomas Harte
22389a5d2d
Merge branch 'master' into HiRes
2017-07-08 20:38:25 -04:00
Thomas Harte
54efcb7e2f
Made a game attempt at automatic motor control and ensured setting is initialised correctly from the user defaults.
2017-07-08 19:31:20 -04:00
Thomas Harte
e2575d6de4
Routed tape motor selections through to the C++ side of the world, and ensured that manual tape playback works properly.
2017-07-08 19:21:12 -04:00
Thomas Harte
46fff8e8a2
Ensured bit 8 is uniquely from the latched video byte, not an OR of that with the refresh address.
2017-07-06 22:48:48 -04:00
Thomas Harte
a3684545b5
Added a block on the tape motor for a short period after each time the ROM routine is intercepted for a substituted byte read. To reduce the collision between fast tape and real tape loading.
2017-07-06 22:33:54 -04:00
Thomas Harte
b842c5b8bb
Merge branch 'master' into ZX81FastLoading
2017-07-06 22:03:24 -04:00
Thomas Harte
0c037627fc
Typer fixes: the recipient no longer releases the caller, and a duplicate call to strlen and piece of arithmetic is corrected.
2017-07-06 21:38:56 -04:00
Thomas Harte
a72a2e0a1a
Ensured tape doesn't proceed of its own volition when in fast-loading mode.
2017-06-23 20:21:37 -04:00
Thomas Harte
50375fb373
Ensured tape position is unaffected if the attempt at loading quickly fails.
2017-06-23 20:18:19 -04:00
Thomas Harte
cb105fdeb4
Took a first stab at high-res support.
2017-06-22 22:48:17 -04:00
Thomas Harte
acfd4dde36
Reduced port writes which can adjust programmatic sync, and prevented anything while NMI generation is active. Moved line counter increment from triggered by interrupt acknowledge to triggered by horizontal sync. In both cases, cribbing from my own earlier work. Initial results suggest that sync issues are resolved in third-party software.
2017-06-22 22:44:06 -04:00
Thomas Harte
644ef13acd
Connected up the fast-tape GUI option for the ZX80 and '81.
2017-06-22 20:20:31 -04:00
Thomas Harte
b7c978e078
Added getters for most of the input lines, and attempted to round out the ZX81's wait logic.
2017-06-22 20:11:19 -04:00
Thomas Harte
52d9ddf9e5
Gave the binary tape player a more logical assignment of wave level to output level. Which miraculously appears to have been the issue with the ZX80/81 tape loading — the inconsistency of silences seems to have been the issue.
2017-06-21 22:13:24 -04:00
Thomas Harte
a6810fc3ef
Removed some minor duplicity and ensured that hsync/NMI ends on the nominated cycle, not one afterwards.
2017-06-21 21:44:42 -04:00
Thomas Harte
15f6c51062
Added the most trivial implementation of the ZX81 wait line.
2017-06-21 21:28:14 -04:00
Thomas Harte
e1355d4b62
Restored proper video output.
2017-06-21 21:18:09 -04:00
Thomas Harte
4bf13610ce
Reinstated interrupts by moving the refresh test back into the refresh cycle.
2017-06-21 21:03:39 -04:00
Thomas Harte
0e0ce379b4
Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
2017-06-21 20:38:08 -04:00
